wm8400-core.c 12 KB

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  1. /*
  2. * Core driver for WM8400.
  3. *
  4. * Copyright 2008 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of the
  11. * License, or (at your option) any later version.
  12. *
  13. */
  14. #include <linux/module.h>
  15. #include <linux/bug.h>
  16. #include <linux/err.h>
  17. #include <linux/i2c.h>
  18. #include <linux/kernel.h>
  19. #include <linux/mfd/core.h>
  20. #include <linux/mfd/wm8400-private.h>
  21. #include <linux/mfd/wm8400-audio.h>
  22. #include <linux/regmap.h>
  23. #include <linux/slab.h>
  24. static struct {
  25. u16 readable; /* Mask of readable bits */
  26. u16 writable; /* Mask of writable bits */
  27. u16 vol; /* Mask of volatile bits */
  28. int is_codec; /* Register controlled by codec reset */
  29. u16 default_val; /* Value on reset */
  30. } reg_data[] = {
  31. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
  32. { 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
  33. { 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
  34. { 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
  35. { 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */
  36. { 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */
  37. { 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */
  38. { 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */
  39. { 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */
  40. { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */
  41. { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
  42. { 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
  43. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
  44. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
  45. { 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
  46. { 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
  47. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
  48. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
  49. { 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
  50. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
  51. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
  52. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
  53. { 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
  54. { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
  55. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
  56. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
  57. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
  58. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
  59. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
  60. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
  61. { 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
  62. { 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
  63. { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
  64. { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
  65. { 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
  66. { 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
  67. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
  68. { 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
  69. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
  70. { 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
  71. { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
  72. { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
  73. { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
  74. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
  75. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
  76. { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
  77. { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
  78. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
  79. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
  80. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
  81. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
  82. { 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
  83. { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
  84. { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
  85. { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
  86. { 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
  87. { 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
  88. { 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
  89. { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
  90. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
  91. { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
  92. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
  93. { 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
  94. { 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
  95. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
  96. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
  97. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
  98. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
  99. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
  100. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
  101. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
  102. { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
  103. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
  104. { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
  105. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
  106. { 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
  107. { 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
  108. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
  109. { 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
  110. { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
  111. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
  112. { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
  113. { 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
  114. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
  115. { 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
  116. };
  117. static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
  118. {
  119. int i, ret = 0;
  120. BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));
  121. /* If there are any volatile reads then read back the entire block */
  122. for (i = reg; i < reg + num_regs; i++)
  123. if (reg_data[i].vol) {
  124. ret = regmap_bulk_read(wm8400->regmap, reg, dest,
  125. num_regs);
  126. return ret;
  127. }
  128. /* Otherwise use the cache */
  129. memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
  130. return 0;
  131. }
  132. static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
  133. u16 *src)
  134. {
  135. int ret, i;
  136. BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));
  137. for (i = 0; i < num_regs; i++) {
  138. BUG_ON(!reg_data[reg + i].writable);
  139. wm8400->reg_cache[reg + i] = src[i];
  140. ret = regmap_write(wm8400->regmap, reg, src[i]);
  141. if (ret != 0)
  142. return ret;
  143. }
  144. return 0;
  145. }
  146. /**
  147. * wm8400_reg_read - Single register read
  148. *
  149. * @wm8400: Pointer to wm8400 control structure
  150. * @reg: Register to read
  151. *
  152. * @return Read value
  153. */
  154. u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
  155. {
  156. u16 val;
  157. mutex_lock(&wm8400->io_lock);
  158. wm8400_read(wm8400, reg, 1, &val);
  159. mutex_unlock(&wm8400->io_lock);
  160. return val;
  161. }
  162. EXPORT_SYMBOL_GPL(wm8400_reg_read);
  163. int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
  164. {
  165. int ret;
  166. mutex_lock(&wm8400->io_lock);
  167. ret = wm8400_read(wm8400, reg, count, data);
  168. mutex_unlock(&wm8400->io_lock);
  169. return ret;
  170. }
  171. EXPORT_SYMBOL_GPL(wm8400_block_read);
  172. /**
  173. * wm8400_set_bits - Bitmask write
  174. *
  175. * @wm8400: Pointer to wm8400 control structure
  176. * @reg: Register to access
  177. * @mask: Mask of bits to change
  178. * @val: Value to set for masked bits
  179. */
  180. int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
  181. {
  182. u16 tmp;
  183. int ret;
  184. mutex_lock(&wm8400->io_lock);
  185. ret = wm8400_read(wm8400, reg, 1, &tmp);
  186. tmp = (tmp & ~mask) | val;
  187. if (ret == 0)
  188. ret = wm8400_write(wm8400, reg, 1, &tmp);
  189. mutex_unlock(&wm8400->io_lock);
  190. return ret;
  191. }
  192. EXPORT_SYMBOL_GPL(wm8400_set_bits);
  193. /**
  194. * wm8400_reset_codec_reg_cache - Reset cached codec registers to
  195. * their default values.
  196. */
  197. void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
  198. {
  199. int i;
  200. mutex_lock(&wm8400->io_lock);
  201. /* Reset all codec registers to their initial value */
  202. for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
  203. if (reg_data[i].is_codec)
  204. wm8400->reg_cache[i] = reg_data[i].default_val;
  205. mutex_unlock(&wm8400->io_lock);
  206. }
  207. EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
  208. static int wm8400_register_codec(struct wm8400 *wm8400)
  209. {
  210. struct mfd_cell cell = {
  211. .name = "wm8400-codec",
  212. .platform_data = wm8400,
  213. .pdata_size = sizeof(*wm8400),
  214. };
  215. return mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0);
  216. }
  217. /*
  218. * wm8400_init - Generic initialisation
  219. *
  220. * The WM8400 can be configured as either an I2C or SPI device. Probe
  221. * functions for each bus set up the accessors then call into this to
  222. * set up the device itself.
  223. */
  224. static int wm8400_init(struct wm8400 *wm8400,
  225. struct wm8400_platform_data *pdata)
  226. {
  227. u16 reg;
  228. int ret, i;
  229. mutex_init(&wm8400->io_lock);
  230. dev_set_drvdata(wm8400->dev, wm8400);
  231. /* Check that this is actually a WM8400 */
  232. ret = regmap_read(wm8400->regmap, WM8400_RESET_ID, &i);
  233. if (ret != 0) {
  234. dev_err(wm8400->dev, "Chip ID register read failed\n");
  235. return -EIO;
  236. }
  237. if (i != reg_data[WM8400_RESET_ID].default_val) {
  238. dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
  239. reg);
  240. return -ENODEV;
  241. }
  242. /* We don't know what state the hardware is in and since this
  243. * is a PMIC we can't reset it safely so initialise the register
  244. * cache from the hardware.
  245. */
  246. ret = regmap_raw_read(wm8400->regmap, 0, wm8400->reg_cache,
  247. ARRAY_SIZE(wm8400->reg_cache));
  248. if (ret != 0) {
  249. dev_err(wm8400->dev, "Register cache read failed\n");
  250. return -EIO;
  251. }
  252. for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
  253. wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
  254. /* If the codec is in reset use hard coded values */
  255. if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
  256. for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
  257. if (reg_data[i].is_codec)
  258. wm8400->reg_cache[i] = reg_data[i].default_val;
  259. ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
  260. if (ret != 0) {
  261. dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
  262. return ret;
  263. }
  264. reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
  265. dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
  266. ret = wm8400_register_codec(wm8400);
  267. if (ret != 0) {
  268. dev_err(wm8400->dev, "Failed to register codec\n");
  269. goto err_children;
  270. }
  271. if (pdata && pdata->platform_init) {
  272. ret = pdata->platform_init(wm8400->dev);
  273. if (ret != 0) {
  274. dev_err(wm8400->dev, "Platform init failed: %d\n",
  275. ret);
  276. goto err_children;
  277. }
  278. } else
  279. dev_warn(wm8400->dev, "No platform initialisation supplied\n");
  280. return 0;
  281. err_children:
  282. mfd_remove_devices(wm8400->dev);
  283. return ret;
  284. }
  285. static void wm8400_release(struct wm8400 *wm8400)
  286. {
  287. mfd_remove_devices(wm8400->dev);
  288. }
  289. static const struct regmap_config wm8400_regmap_config = {
  290. .reg_bits = 8,
  291. .val_bits = 16,
  292. .max_register = WM8400_REGISTER_COUNT - 1,
  293. };
  294. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  295. static int wm8400_i2c_probe(struct i2c_client *i2c,
  296. const struct i2c_device_id *id)
  297. {
  298. struct wm8400 *wm8400;
  299. int ret;
  300. wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL);
  301. if (wm8400 == NULL) {
  302. ret = -ENOMEM;
  303. goto err;
  304. }
  305. wm8400->regmap = regmap_init_i2c(i2c, &wm8400_regmap_config);
  306. if (IS_ERR(wm8400->regmap)) {
  307. ret = PTR_ERR(wm8400->regmap);
  308. goto struct_err;
  309. }
  310. wm8400->dev = &i2c->dev;
  311. i2c_set_clientdata(i2c, wm8400);
  312. ret = wm8400_init(wm8400, i2c->dev.platform_data);
  313. if (ret != 0)
  314. goto map_err;
  315. return 0;
  316. map_err:
  317. regmap_exit(wm8400->regmap);
  318. struct_err:
  319. kfree(wm8400);
  320. err:
  321. return ret;
  322. }
  323. static int wm8400_i2c_remove(struct i2c_client *i2c)
  324. {
  325. struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
  326. wm8400_release(wm8400);
  327. regmap_exit(wm8400->regmap);
  328. kfree(wm8400);
  329. return 0;
  330. }
  331. static const struct i2c_device_id wm8400_i2c_id[] = {
  332. { "wm8400", 0 },
  333. { }
  334. };
  335. MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
  336. static struct i2c_driver wm8400_i2c_driver = {
  337. .driver = {
  338. .name = "WM8400",
  339. .owner = THIS_MODULE,
  340. },
  341. .probe = wm8400_i2c_probe,
  342. .remove = wm8400_i2c_remove,
  343. .id_table = wm8400_i2c_id,
  344. };
  345. #endif
  346. static int __init wm8400_module_init(void)
  347. {
  348. int ret = -ENODEV;
  349. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  350. ret = i2c_add_driver(&wm8400_i2c_driver);
  351. if (ret != 0)
  352. pr_err("Failed to register I2C driver: %d\n", ret);
  353. #endif
  354. return ret;
  355. }
  356. subsys_initcall(wm8400_module_init);
  357. static void __exit wm8400_module_exit(void)
  358. {
  359. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  360. i2c_del_driver(&wm8400_i2c_driver);
  361. #endif
  362. }
  363. module_exit(wm8400_module_exit);
  364. MODULE_LICENSE("GPL");
  365. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");