dm1105.c 29 KB

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  1. /*
  2. * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip
  3. *
  4. * Copyright (C) 2008 Igor M. Liplianin <liplianin@me.by>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. *
  20. */
  21. #include <linux/i2c.h>
  22. #include <linux/i2c-algo-bit.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/proc_fs.h>
  28. #include <linux/pci.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/slab.h>
  31. #include <media/rc-core.h>
  32. #include "demux.h"
  33. #include "dmxdev.h"
  34. #include "dvb_demux.h"
  35. #include "dvb_frontend.h"
  36. #include "dvb_net.h"
  37. #include "dvbdev.h"
  38. #include "dvb-pll.h"
  39. #include "stv0299.h"
  40. #include "stv0288.h"
  41. #include "stb6000.h"
  42. #include "si21xx.h"
  43. #include "cx24116.h"
  44. #include "z0194a.h"
  45. #include "ds3000.h"
  46. #define MODULE_NAME "dm1105"
  47. #define UNSET (-1U)
  48. #define DM1105_BOARD_NOAUTO UNSET
  49. #define DM1105_BOARD_UNKNOWN 0
  50. #define DM1105_BOARD_DVBWORLD_2002 1
  51. #define DM1105_BOARD_DVBWORLD_2004 2
  52. #define DM1105_BOARD_AXESS_DM05 3
  53. #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO 4
  54. /* ----------------------------------------------- */
  55. /*
  56. * PCI ID's
  57. */
  58. #ifndef PCI_VENDOR_ID_TRIGEM
  59. #define PCI_VENDOR_ID_TRIGEM 0x109f
  60. #endif
  61. #ifndef PCI_VENDOR_ID_AXESS
  62. #define PCI_VENDOR_ID_AXESS 0x195d
  63. #endif
  64. #ifndef PCI_DEVICE_ID_DM1105
  65. #define PCI_DEVICE_ID_DM1105 0x036f
  66. #endif
  67. #ifndef PCI_DEVICE_ID_DW2002
  68. #define PCI_DEVICE_ID_DW2002 0x2002
  69. #endif
  70. #ifndef PCI_DEVICE_ID_DW2004
  71. #define PCI_DEVICE_ID_DW2004 0x2004
  72. #endif
  73. #ifndef PCI_DEVICE_ID_DM05
  74. #define PCI_DEVICE_ID_DM05 0x1105
  75. #endif
  76. /* ----------------------------------------------- */
  77. /* sdmc dm1105 registers */
  78. /* TS Control */
  79. #define DM1105_TSCTR 0x00
  80. #define DM1105_DTALENTH 0x04
  81. /* GPIO Interface */
  82. #define DM1105_GPIOVAL 0x08
  83. #define DM1105_GPIOCTR 0x0c
  84. /* PID serial number */
  85. #define DM1105_PIDN 0x10
  86. /* Odd-even secret key select */
  87. #define DM1105_CWSEL 0x14
  88. /* Host Command Interface */
  89. #define DM1105_HOST_CTR 0x18
  90. #define DM1105_HOST_AD 0x1c
  91. /* PCI Interface */
  92. #define DM1105_CR 0x30
  93. #define DM1105_RST 0x34
  94. #define DM1105_STADR 0x38
  95. #define DM1105_RLEN 0x3c
  96. #define DM1105_WRP 0x40
  97. #define DM1105_INTCNT 0x44
  98. #define DM1105_INTMAK 0x48
  99. #define DM1105_INTSTS 0x4c
  100. /* CW Value */
  101. #define DM1105_ODD 0x50
  102. #define DM1105_EVEN 0x58
  103. /* PID Value */
  104. #define DM1105_PID 0x60
  105. /* IR Control */
  106. #define DM1105_IRCTR 0x64
  107. #define DM1105_IRMODE 0x68
  108. #define DM1105_SYSTEMCODE 0x6c
  109. #define DM1105_IRCODE 0x70
  110. /* Unknown Values */
  111. #define DM1105_ENCRYPT 0x74
  112. #define DM1105_VER 0x7c
  113. /* I2C Interface */
  114. #define DM1105_I2CCTR 0x80
  115. #define DM1105_I2CSTS 0x81
  116. #define DM1105_I2CDAT 0x82
  117. #define DM1105_I2C_RA 0x83
  118. /* ----------------------------------------------- */
  119. /* Interrupt Mask Bits */
  120. #define INTMAK_TSIRQM 0x01
  121. #define INTMAK_HIRQM 0x04
  122. #define INTMAK_IRM 0x08
  123. #define INTMAK_ALLMASK (INTMAK_TSIRQM | \
  124. INTMAK_HIRQM | \
  125. INTMAK_IRM)
  126. #define INTMAK_NONEMASK 0x00
  127. /* Interrupt Status Bits */
  128. #define INTSTS_TSIRQ 0x01
  129. #define INTSTS_HIRQ 0x04
  130. #define INTSTS_IR 0x08
  131. /* IR Control Bits */
  132. #define DM1105_IR_EN 0x01
  133. #define DM1105_SYS_CHK 0x02
  134. #define DM1105_REP_FLG 0x08
  135. /* EEPROM addr */
  136. #define IIC_24C01_addr 0xa0
  137. /* Max board count */
  138. #define DM1105_MAX 0x04
  139. #define DRIVER_NAME "dm1105"
  140. #define DM1105_I2C_GPIO_NAME "dm1105-gpio"
  141. #define DM1105_DMA_PACKETS 47
  142. #define DM1105_DMA_PACKET_LENGTH (128*4)
  143. #define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS)
  144. /* */
  145. #define GPIO08 (1 << 8)
  146. #define GPIO13 (1 << 13)
  147. #define GPIO14 (1 << 14)
  148. #define GPIO15 (1 << 15)
  149. #define GPIO16 (1 << 16)
  150. #define GPIO17 (1 << 17)
  151. #define GPIO_ALL 0x03ffff
  152. /* GPIO's for LNB power control */
  153. #define DM1105_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  154. #define DM1105_LNB_OFF GPIO17
  155. #define DM1105_LNB_13V (GPIO16 | GPIO08)
  156. #define DM1105_LNB_18V GPIO08
  157. /* GPIO's for LNB power control for Axess DM05 */
  158. #define DM05_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  159. #define DM05_LNB_OFF GPIO17/* actually 13v */
  160. #define DM05_LNB_13V GPIO17
  161. #define DM05_LNB_18V (GPIO17 | GPIO16)
  162. /* GPIO's for LNB power control for unbranded with I2C on GPIO */
  163. #define UNBR_LNB_MASK (GPIO17 | GPIO16)
  164. #define UNBR_LNB_OFF 0
  165. #define UNBR_LNB_13V GPIO17
  166. #define UNBR_LNB_18V (GPIO17 | GPIO16)
  167. static unsigned int card[] = {[0 ... 3] = UNSET };
  168. module_param_array(card, int, NULL, 0444);
  169. MODULE_PARM_DESC(card, "card type");
  170. static int ir_debug;
  171. module_param(ir_debug, int, 0644);
  172. MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
  173. static unsigned int dm1105_devcount;
  174. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  175. struct dm1105_board {
  176. char *name;
  177. struct {
  178. u32 mask, off, v13, v18;
  179. } lnb;
  180. u32 gpio_scl, gpio_sda;
  181. };
  182. struct dm1105_subid {
  183. u16 subvendor;
  184. u16 subdevice;
  185. u32 card;
  186. };
  187. static const struct dm1105_board dm1105_boards[] = {
  188. [DM1105_BOARD_UNKNOWN] = {
  189. .name = "UNKNOWN/GENERIC",
  190. .lnb = {
  191. .mask = DM1105_LNB_MASK,
  192. .off = DM1105_LNB_OFF,
  193. .v13 = DM1105_LNB_13V,
  194. .v18 = DM1105_LNB_18V,
  195. },
  196. },
  197. [DM1105_BOARD_DVBWORLD_2002] = {
  198. .name = "DVBWorld PCI 2002",
  199. .lnb = {
  200. .mask = DM1105_LNB_MASK,
  201. .off = DM1105_LNB_OFF,
  202. .v13 = DM1105_LNB_13V,
  203. .v18 = DM1105_LNB_18V,
  204. },
  205. },
  206. [DM1105_BOARD_DVBWORLD_2004] = {
  207. .name = "DVBWorld PCI 2004",
  208. .lnb = {
  209. .mask = DM1105_LNB_MASK,
  210. .off = DM1105_LNB_OFF,
  211. .v13 = DM1105_LNB_13V,
  212. .v18 = DM1105_LNB_18V,
  213. },
  214. },
  215. [DM1105_BOARD_AXESS_DM05] = {
  216. .name = "Axess/EasyTv DM05",
  217. .lnb = {
  218. .mask = DM05_LNB_MASK,
  219. .off = DM05_LNB_OFF,
  220. .v13 = DM05_LNB_13V,
  221. .v18 = DM05_LNB_18V,
  222. },
  223. },
  224. [DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = {
  225. .name = "Unbranded DM1105 with i2c on GPIOs",
  226. .lnb = {
  227. .mask = UNBR_LNB_MASK,
  228. .off = UNBR_LNB_OFF,
  229. .v13 = UNBR_LNB_13V,
  230. .v18 = UNBR_LNB_18V,
  231. },
  232. .gpio_scl = GPIO14,
  233. .gpio_sda = GPIO13,
  234. },
  235. };
  236. static const struct dm1105_subid dm1105_subids[] = {
  237. {
  238. .subvendor = 0x0000,
  239. .subdevice = 0x2002,
  240. .card = DM1105_BOARD_DVBWORLD_2002,
  241. }, {
  242. .subvendor = 0x0001,
  243. .subdevice = 0x2002,
  244. .card = DM1105_BOARD_DVBWORLD_2002,
  245. }, {
  246. .subvendor = 0x0000,
  247. .subdevice = 0x2004,
  248. .card = DM1105_BOARD_DVBWORLD_2004,
  249. }, {
  250. .subvendor = 0x0001,
  251. .subdevice = 0x2004,
  252. .card = DM1105_BOARD_DVBWORLD_2004,
  253. }, {
  254. .subvendor = 0x195d,
  255. .subdevice = 0x1105,
  256. .card = DM1105_BOARD_AXESS_DM05,
  257. },
  258. };
  259. static void dm1105_card_list(struct pci_dev *pci)
  260. {
  261. int i;
  262. if (0 == pci->subsystem_vendor &&
  263. 0 == pci->subsystem_device) {
  264. printk(KERN_ERR
  265. "dm1105: Your board has no valid PCI Subsystem ID\n"
  266. "dm1105: and thus can't be autodetected\n"
  267. "dm1105: Please pass card=<n> insmod option to\n"
  268. "dm1105: workaround that. Redirect complaints to\n"
  269. "dm1105: the vendor of the TV card. Best regards,\n"
  270. "dm1105: -- tux\n");
  271. } else {
  272. printk(KERN_ERR
  273. "dm1105: Your board isn't known (yet) to the driver.\n"
  274. "dm1105: You can try to pick one of the existing\n"
  275. "dm1105: card configs via card=<n> insmod option.\n"
  276. "dm1105: Updating to the latest version might help\n"
  277. "dm1105: as well.\n");
  278. }
  279. printk(KERN_ERR "Here is a list of valid choices for the card=<n> "
  280. "insmod option:\n");
  281. for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++)
  282. printk(KERN_ERR "dm1105: card=%d -> %s\n",
  283. i, dm1105_boards[i].name);
  284. }
  285. /* infrared remote control */
  286. struct infrared {
  287. struct rc_dev *dev;
  288. char input_phys[32];
  289. struct work_struct work;
  290. u32 ir_command;
  291. };
  292. struct dm1105_dev {
  293. /* pci */
  294. struct pci_dev *pdev;
  295. u8 __iomem *io_mem;
  296. /* ir */
  297. struct infrared ir;
  298. /* dvb */
  299. struct dmx_frontend hw_frontend;
  300. struct dmx_frontend mem_frontend;
  301. struct dmxdev dmxdev;
  302. struct dvb_adapter dvb_adapter;
  303. struct dvb_demux demux;
  304. struct dvb_frontend *fe;
  305. struct dvb_net dvbnet;
  306. unsigned int full_ts_users;
  307. unsigned int boardnr;
  308. int nr;
  309. /* i2c */
  310. struct i2c_adapter i2c_adap;
  311. struct i2c_adapter i2c_bb_adap;
  312. struct i2c_algo_bit_data i2c_bit;
  313. /* irq */
  314. struct work_struct work;
  315. struct workqueue_struct *wq;
  316. char wqn[16];
  317. /* dma */
  318. dma_addr_t dma_addr;
  319. unsigned char *ts_buf;
  320. u32 wrp;
  321. u32 nextwrp;
  322. u32 buffer_size;
  323. unsigned int PacketErrorCount;
  324. unsigned int dmarst;
  325. spinlock_t lock;
  326. };
  327. #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg]))
  328. #define dm_readb(reg) inb(dm_io_mem(reg))
  329. #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg)))
  330. #define dm_readw(reg) inw(dm_io_mem(reg))
  331. #define dm_writew(reg, value) outw((value), (dm_io_mem(reg)))
  332. #define dm_readl(reg) inl(dm_io_mem(reg))
  333. #define dm_writel(reg, value) outl((value), (dm_io_mem(reg)))
  334. #define dm_andorl(reg, mask, value) \
  335. outl((inl(dm_io_mem(reg)) & ~(mask)) |\
  336. ((value) & (mask)), (dm_io_mem(reg)))
  337. #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit))
  338. #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0)
  339. /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines,
  340. so we can use only 3 GPIO's from GPIO15 to GPIO17.
  341. Here I don't check whether HOST is enebled as it is not implemented yet.
  342. */
  343. static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask)
  344. {
  345. if (mask & 0xfffc0000)
  346. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  347. if (mask & 0x0003ffff)
  348. dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff);
  349. }
  350. static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask)
  351. {
  352. if (mask & 0xfffc0000)
  353. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  354. if (mask & 0x0003ffff)
  355. dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff);
  356. }
  357. static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val)
  358. {
  359. if (mask & 0xfffc0000)
  360. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  361. if (mask & 0x0003ffff)
  362. dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val);
  363. }
  364. static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask)
  365. {
  366. if (mask & 0xfffc0000)
  367. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  368. if (mask & 0x0003ffff)
  369. return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff;
  370. return 0;
  371. }
  372. static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput)
  373. {
  374. if (mask & 0xfffc0000)
  375. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  376. if ((mask & 0x0003ffff) && asoutput)
  377. dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff);
  378. else if ((mask & 0x0003ffff) && !asoutput)
  379. dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff);
  380. }
  381. static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state)
  382. {
  383. if (state)
  384. dm1105_gpio_enable(dev, line, 0);
  385. else {
  386. dm1105_gpio_enable(dev, line, 1);
  387. dm1105_gpio_clear(dev, line);
  388. }
  389. }
  390. static void dm1105_setsda(void *data, int state)
  391. {
  392. struct dm1105_dev *dev = data;
  393. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state);
  394. }
  395. static void dm1105_setscl(void *data, int state)
  396. {
  397. struct dm1105_dev *dev = data;
  398. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state);
  399. }
  400. static int dm1105_getsda(void *data)
  401. {
  402. struct dm1105_dev *dev = data;
  403. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda)
  404. ? 1 : 0;
  405. }
  406. static int dm1105_getscl(void *data)
  407. {
  408. struct dm1105_dev *dev = data;
  409. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl)
  410. ? 1 : 0;
  411. }
  412. static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
  413. struct i2c_msg *msgs, int num)
  414. {
  415. struct dm1105_dev *dev ;
  416. int addr, rc, i, j, k, len, byte, data;
  417. u8 status;
  418. dev = i2c_adap->algo_data;
  419. for (i = 0; i < num; i++) {
  420. dm_writeb(DM1105_I2CCTR, 0x00);
  421. if (msgs[i].flags & I2C_M_RD) {
  422. /* read bytes */
  423. addr = msgs[i].addr << 1;
  424. addr |= 1;
  425. dm_writeb(DM1105_I2CDAT, addr);
  426. for (byte = 0; byte < msgs[i].len; byte++)
  427. dm_writeb(DM1105_I2CDAT + byte + 1, 0);
  428. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  429. for (j = 0; j < 55; j++) {
  430. mdelay(10);
  431. status = dm_readb(DM1105_I2CSTS);
  432. if ((status & 0xc0) == 0x40)
  433. break;
  434. }
  435. if (j >= 55)
  436. return -1;
  437. for (byte = 0; byte < msgs[i].len; byte++) {
  438. rc = dm_readb(DM1105_I2CDAT + byte + 1);
  439. if (rc < 0)
  440. goto err;
  441. msgs[i].buf[byte] = rc;
  442. }
  443. } else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) {
  444. /* prepaired for cx24116 firmware */
  445. /* Write in small blocks */
  446. len = msgs[i].len - 1;
  447. k = 1;
  448. do {
  449. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  450. dm_writeb(DM1105_I2CDAT + 1, 0xf7);
  451. for (byte = 0; byte < (len > 48 ? 48 : len); byte++) {
  452. data = msgs[i].buf[k + byte];
  453. dm_writeb(DM1105_I2CDAT + byte + 2, data);
  454. }
  455. dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));
  456. for (j = 0; j < 25; j++) {
  457. mdelay(10);
  458. status = dm_readb(DM1105_I2CSTS);
  459. if ((status & 0xc0) == 0x40)
  460. break;
  461. }
  462. if (j >= 25)
  463. return -1;
  464. k += 48;
  465. len -= 48;
  466. } while (len > 0);
  467. } else {
  468. /* write bytes */
  469. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  470. for (byte = 0; byte < msgs[i].len; byte++) {
  471. data = msgs[i].buf[byte];
  472. dm_writeb(DM1105_I2CDAT + byte + 1, data);
  473. }
  474. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  475. for (j = 0; j < 25; j++) {
  476. mdelay(10);
  477. status = dm_readb(DM1105_I2CSTS);
  478. if ((status & 0xc0) == 0x40)
  479. break;
  480. }
  481. if (j >= 25)
  482. return -1;
  483. }
  484. }
  485. return num;
  486. err:
  487. return rc;
  488. }
  489. static u32 functionality(struct i2c_adapter *adap)
  490. {
  491. return I2C_FUNC_I2C;
  492. }
  493. static struct i2c_algorithm dm1105_algo = {
  494. .master_xfer = dm1105_i2c_xfer,
  495. .functionality = functionality,
  496. };
  497. static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed)
  498. {
  499. return container_of(feed->demux, struct dm1105_dev, demux);
  500. }
  501. static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe)
  502. {
  503. return container_of(fe->dvb, struct dm1105_dev, dvb_adapter);
  504. }
  505. static int dm1105_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  506. {
  507. struct dm1105_dev *dev = frontend_to_dm1105_dev(fe);
  508. dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1);
  509. if (voltage == SEC_VOLTAGE_18)
  510. dm1105_gpio_andor(dev,
  511. dm1105_boards[dev->boardnr].lnb.mask,
  512. dm1105_boards[dev->boardnr].lnb.v18);
  513. else if (voltage == SEC_VOLTAGE_13)
  514. dm1105_gpio_andor(dev,
  515. dm1105_boards[dev->boardnr].lnb.mask,
  516. dm1105_boards[dev->boardnr].lnb.v13);
  517. else
  518. dm1105_gpio_andor(dev,
  519. dm1105_boards[dev->boardnr].lnb.mask,
  520. dm1105_boards[dev->boardnr].lnb.off);
  521. return 0;
  522. }
  523. static void dm1105_set_dma_addr(struct dm1105_dev *dev)
  524. {
  525. dm_writel(DM1105_STADR, cpu_to_le32(dev->dma_addr));
  526. }
  527. static int __devinit dm1105_dma_map(struct dm1105_dev *dev)
  528. {
  529. dev->ts_buf = pci_alloc_consistent(dev->pdev,
  530. 6 * DM1105_DMA_BYTES,
  531. &dev->dma_addr);
  532. return !dev->ts_buf;
  533. }
  534. static void dm1105_dma_unmap(struct dm1105_dev *dev)
  535. {
  536. pci_free_consistent(dev->pdev,
  537. 6 * DM1105_DMA_BYTES,
  538. dev->ts_buf,
  539. dev->dma_addr);
  540. }
  541. static void dm1105_enable_irqs(struct dm1105_dev *dev)
  542. {
  543. dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);
  544. dm_writeb(DM1105_CR, 1);
  545. }
  546. static void dm1105_disable_irqs(struct dm1105_dev *dev)
  547. {
  548. dm_writeb(DM1105_INTMAK, INTMAK_IRM);
  549. dm_writeb(DM1105_CR, 0);
  550. }
  551. static int dm1105_start_feed(struct dvb_demux_feed *f)
  552. {
  553. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  554. if (dev->full_ts_users++ == 0)
  555. dm1105_enable_irqs(dev);
  556. return 0;
  557. }
  558. static int dm1105_stop_feed(struct dvb_demux_feed *f)
  559. {
  560. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  561. if (--dev->full_ts_users == 0)
  562. dm1105_disable_irqs(dev);
  563. return 0;
  564. }
  565. /* ir work handler */
  566. static void dm1105_emit_key(struct work_struct *work)
  567. {
  568. struct infrared *ir = container_of(work, struct infrared, work);
  569. u32 ircom = ir->ir_command;
  570. u8 data;
  571. if (ir_debug)
  572. printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom);
  573. data = (ircom >> 8) & 0x7f;
  574. rc_keydown(ir->dev, data, 0);
  575. }
  576. /* work handler */
  577. static void dm1105_dmx_buffer(struct work_struct *work)
  578. {
  579. struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work);
  580. unsigned int nbpackets;
  581. u32 oldwrp = dev->wrp;
  582. u32 nextwrp = dev->nextwrp;
  583. if (!((dev->ts_buf[oldwrp] == 0x47) &&
  584. (dev->ts_buf[oldwrp + 188] == 0x47) &&
  585. (dev->ts_buf[oldwrp + 188 * 2] == 0x47))) {
  586. dev->PacketErrorCount++;
  587. /* bad packet found */
  588. if ((dev->PacketErrorCount >= 2) &&
  589. (dev->dmarst == 0)) {
  590. dm_writeb(DM1105_RST, 1);
  591. dev->wrp = 0;
  592. dev->PacketErrorCount = 0;
  593. dev->dmarst = 0;
  594. return;
  595. }
  596. }
  597. if (nextwrp < oldwrp) {
  598. memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp);
  599. nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188;
  600. } else
  601. nbpackets = (nextwrp - oldwrp) / 188;
  602. dev->wrp = nextwrp;
  603. dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets);
  604. }
  605. static irqreturn_t dm1105_irq(int irq, void *dev_id)
  606. {
  607. struct dm1105_dev *dev = dev_id;
  608. /* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */
  609. unsigned int intsts = dm_readb(DM1105_INTSTS);
  610. dm_writeb(DM1105_INTSTS, intsts);
  611. switch (intsts) {
  612. case INTSTS_TSIRQ:
  613. case (INTSTS_TSIRQ | INTSTS_IR):
  614. dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR);
  615. queue_work(dev->wq, &dev->work);
  616. break;
  617. case INTSTS_IR:
  618. dev->ir.ir_command = dm_readl(DM1105_IRCODE);
  619. schedule_work(&dev->ir.work);
  620. break;
  621. }
  622. return IRQ_HANDLED;
  623. }
  624. int __devinit dm1105_ir_init(struct dm1105_dev *dm1105)
  625. {
  626. struct rc_dev *dev;
  627. int err = -ENOMEM;
  628. dev = rc_allocate_device();
  629. if (!dev)
  630. return -ENOMEM;
  631. snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys),
  632. "pci-%s/ir0", pci_name(dm1105->pdev));
  633. dev->driver_name = MODULE_NAME;
  634. dev->map_name = RC_MAP_DM1105_NEC;
  635. dev->driver_type = RC_DRIVER_SCANCODE;
  636. dev->input_name = "DVB on-card IR receiver";
  637. dev->input_phys = dm1105->ir.input_phys;
  638. dev->input_id.bustype = BUS_PCI;
  639. dev->input_id.version = 1;
  640. if (dm1105->pdev->subsystem_vendor) {
  641. dev->input_id.vendor = dm1105->pdev->subsystem_vendor;
  642. dev->input_id.product = dm1105->pdev->subsystem_device;
  643. } else {
  644. dev->input_id.vendor = dm1105->pdev->vendor;
  645. dev->input_id.product = dm1105->pdev->device;
  646. }
  647. dev->dev.parent = &dm1105->pdev->dev;
  648. INIT_WORK(&dm1105->ir.work, dm1105_emit_key);
  649. err = rc_register_device(dev);
  650. if (err < 0) {
  651. rc_free_device(dev);
  652. return err;
  653. }
  654. dm1105->ir.dev = dev;
  655. return 0;
  656. }
  657. void __devexit dm1105_ir_exit(struct dm1105_dev *dm1105)
  658. {
  659. rc_unregister_device(dm1105->ir.dev);
  660. }
  661. static int __devinit dm1105_hw_init(struct dm1105_dev *dev)
  662. {
  663. dm1105_disable_irqs(dev);
  664. dm_writeb(DM1105_HOST_CTR, 0);
  665. /*DATALEN 188,*/
  666. dm_writeb(DM1105_DTALENTH, 188);
  667. /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/
  668. dm_writew(DM1105_TSCTR, 0xc10a);
  669. /* map DMA and set address */
  670. dm1105_dma_map(dev);
  671. dm1105_set_dma_addr(dev);
  672. /* big buffer */
  673. dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES);
  674. dm_writeb(DM1105_INTCNT, 47);
  675. /* IR NEC mode enable */
  676. dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));
  677. dm_writeb(DM1105_IRMODE, 0);
  678. dm_writew(DM1105_SYSTEMCODE, 0);
  679. return 0;
  680. }
  681. static void dm1105_hw_exit(struct dm1105_dev *dev)
  682. {
  683. dm1105_disable_irqs(dev);
  684. /* IR disable */
  685. dm_writeb(DM1105_IRCTR, 0);
  686. dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);
  687. dm1105_dma_unmap(dev);
  688. }
  689. static struct stv0299_config sharp_z0194a_config = {
  690. .demod_address = 0x68,
  691. .inittab = sharp_z0194a_inittab,
  692. .mclk = 88000000UL,
  693. .invert = 1,
  694. .skip_reinit = 0,
  695. .lock_output = STV0299_LOCKOUTPUT_1,
  696. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  697. .min_delay_ms = 100,
  698. .set_symbol_rate = sharp_z0194a_set_symbol_rate,
  699. };
  700. static struct stv0288_config earda_config = {
  701. .demod_address = 0x68,
  702. .min_delay_ms = 100,
  703. };
  704. static struct si21xx_config serit_config = {
  705. .demod_address = 0x68,
  706. .min_delay_ms = 100,
  707. };
  708. static struct cx24116_config serit_sp2633_config = {
  709. .demod_address = 0x55,
  710. };
  711. static struct ds3000_config dvbworld_ds3000_config = {
  712. .demod_address = 0x68,
  713. };
  714. static int __devinit frontend_init(struct dm1105_dev *dev)
  715. {
  716. int ret;
  717. switch (dev->boardnr) {
  718. case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO:
  719. dm1105_gpio_enable(dev, GPIO15, 1);
  720. dm1105_gpio_clear(dev, GPIO15);
  721. msleep(100);
  722. dm1105_gpio_set(dev, GPIO15);
  723. msleep(200);
  724. dev->fe = dvb_attach(
  725. stv0299_attach, &sharp_z0194a_config,
  726. &dev->i2c_bb_adap);
  727. if (dev->fe) {
  728. dev->fe->ops.set_voltage = dm1105_set_voltage;
  729. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  730. &dev->i2c_bb_adap, DVB_PLL_OPERA1);
  731. break;
  732. }
  733. dev->fe = dvb_attach(
  734. stv0288_attach, &earda_config,
  735. &dev->i2c_bb_adap);
  736. if (dev->fe) {
  737. dev->fe->ops.set_voltage = dm1105_set_voltage;
  738. dvb_attach(stb6000_attach, dev->fe, 0x61,
  739. &dev->i2c_bb_adap);
  740. break;
  741. }
  742. dev->fe = dvb_attach(
  743. si21xx_attach, &serit_config,
  744. &dev->i2c_bb_adap);
  745. if (dev->fe)
  746. dev->fe->ops.set_voltage = dm1105_set_voltage;
  747. break;
  748. case DM1105_BOARD_DVBWORLD_2004:
  749. dev->fe = dvb_attach(
  750. cx24116_attach, &serit_sp2633_config,
  751. &dev->i2c_adap);
  752. if (dev->fe) {
  753. dev->fe->ops.set_voltage = dm1105_set_voltage;
  754. break;
  755. }
  756. dev->fe = dvb_attach(
  757. ds3000_attach, &dvbworld_ds3000_config,
  758. &dev->i2c_adap);
  759. if (dev->fe)
  760. dev->fe->ops.set_voltage = dm1105_set_voltage;
  761. break;
  762. case DM1105_BOARD_DVBWORLD_2002:
  763. case DM1105_BOARD_AXESS_DM05:
  764. default:
  765. dev->fe = dvb_attach(
  766. stv0299_attach, &sharp_z0194a_config,
  767. &dev->i2c_adap);
  768. if (dev->fe) {
  769. dev->fe->ops.set_voltage = dm1105_set_voltage;
  770. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  771. &dev->i2c_adap, DVB_PLL_OPERA1);
  772. break;
  773. }
  774. dev->fe = dvb_attach(
  775. stv0288_attach, &earda_config,
  776. &dev->i2c_adap);
  777. if (dev->fe) {
  778. dev->fe->ops.set_voltage = dm1105_set_voltage;
  779. dvb_attach(stb6000_attach, dev->fe, 0x61,
  780. &dev->i2c_adap);
  781. break;
  782. }
  783. dev->fe = dvb_attach(
  784. si21xx_attach, &serit_config,
  785. &dev->i2c_adap);
  786. if (dev->fe)
  787. dev->fe->ops.set_voltage = dm1105_set_voltage;
  788. }
  789. if (!dev->fe) {
  790. dev_err(&dev->pdev->dev, "could not attach frontend\n");
  791. return -ENODEV;
  792. }
  793. ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe);
  794. if (ret < 0) {
  795. if (dev->fe->ops.release)
  796. dev->fe->ops.release(dev->fe);
  797. dev->fe = NULL;
  798. return ret;
  799. }
  800. return 0;
  801. }
  802. static void __devinit dm1105_read_mac(struct dm1105_dev *dev, u8 *mac)
  803. {
  804. static u8 command[1] = { 0x28 };
  805. struct i2c_msg msg[] = {
  806. {
  807. .addr = IIC_24C01_addr >> 1,
  808. .flags = 0,
  809. .buf = command,
  810. .len = 1
  811. }, {
  812. .addr = IIC_24C01_addr >> 1,
  813. .flags = I2C_M_RD,
  814. .buf = mac,
  815. .len = 6
  816. },
  817. };
  818. dm1105_i2c_xfer(&dev->i2c_adap, msg , 2);
  819. dev_info(&dev->pdev->dev, "MAC %pM\n", mac);
  820. }
  821. static int __devinit dm1105_probe(struct pci_dev *pdev,
  822. const struct pci_device_id *ent)
  823. {
  824. struct dm1105_dev *dev;
  825. struct dvb_adapter *dvb_adapter;
  826. struct dvb_demux *dvbdemux;
  827. struct dmx_demux *dmx;
  828. int ret = -ENOMEM;
  829. int i;
  830. dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL);
  831. if (!dev)
  832. return -ENOMEM;
  833. /* board config */
  834. dev->nr = dm1105_devcount;
  835. dev->boardnr = UNSET;
  836. if (card[dev->nr] < ARRAY_SIZE(dm1105_boards))
  837. dev->boardnr = card[dev->nr];
  838. for (i = 0; UNSET == dev->boardnr &&
  839. i < ARRAY_SIZE(dm1105_subids); i++)
  840. if (pdev->subsystem_vendor ==
  841. dm1105_subids[i].subvendor &&
  842. pdev->subsystem_device ==
  843. dm1105_subids[i].subdevice)
  844. dev->boardnr = dm1105_subids[i].card;
  845. if (UNSET == dev->boardnr) {
  846. dev->boardnr = DM1105_BOARD_UNKNOWN;
  847. dm1105_card_list(pdev);
  848. }
  849. dm1105_devcount++;
  850. dev->pdev = pdev;
  851. dev->buffer_size = 5 * DM1105_DMA_BYTES;
  852. dev->PacketErrorCount = 0;
  853. dev->dmarst = 0;
  854. ret = pci_enable_device(pdev);
  855. if (ret < 0)
  856. goto err_kfree;
  857. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  858. if (ret < 0)
  859. goto err_pci_disable_device;
  860. pci_set_master(pdev);
  861. ret = pci_request_regions(pdev, DRIVER_NAME);
  862. if (ret < 0)
  863. goto err_pci_disable_device;
  864. dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
  865. if (!dev->io_mem) {
  866. ret = -EIO;
  867. goto err_pci_release_regions;
  868. }
  869. spin_lock_init(&dev->lock);
  870. pci_set_drvdata(pdev, dev);
  871. ret = dm1105_hw_init(dev);
  872. if (ret < 0)
  873. goto err_pci_iounmap;
  874. /* i2c */
  875. i2c_set_adapdata(&dev->i2c_adap, dev);
  876. strcpy(dev->i2c_adap.name, DRIVER_NAME);
  877. dev->i2c_adap.owner = THIS_MODULE;
  878. dev->i2c_adap.dev.parent = &pdev->dev;
  879. dev->i2c_adap.algo = &dm1105_algo;
  880. dev->i2c_adap.algo_data = dev;
  881. ret = i2c_add_adapter(&dev->i2c_adap);
  882. if (ret < 0)
  883. goto err_dm1105_hw_exit;
  884. i2c_set_adapdata(&dev->i2c_bb_adap, dev);
  885. strcpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME);
  886. dev->i2c_bb_adap.owner = THIS_MODULE;
  887. dev->i2c_bb_adap.dev.parent = &pdev->dev;
  888. dev->i2c_bb_adap.algo_data = &dev->i2c_bit;
  889. dev->i2c_bit.data = dev;
  890. dev->i2c_bit.setsda = dm1105_setsda;
  891. dev->i2c_bit.setscl = dm1105_setscl;
  892. dev->i2c_bit.getsda = dm1105_getsda;
  893. dev->i2c_bit.getscl = dm1105_getscl;
  894. dev->i2c_bit.udelay = 10;
  895. dev->i2c_bit.timeout = 10;
  896. /* Raise SCL and SDA */
  897. dm1105_setsda(dev, 1);
  898. dm1105_setscl(dev, 1);
  899. ret = i2c_bit_add_bus(&dev->i2c_bb_adap);
  900. if (ret < 0)
  901. goto err_i2c_del_adapter;
  902. /* dvb */
  903. ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME,
  904. THIS_MODULE, &pdev->dev, adapter_nr);
  905. if (ret < 0)
  906. goto err_i2c_del_adapters;
  907. dvb_adapter = &dev->dvb_adapter;
  908. dm1105_read_mac(dev, dvb_adapter->proposed_mac);
  909. dvbdemux = &dev->demux;
  910. dvbdemux->filternum = 256;
  911. dvbdemux->feednum = 256;
  912. dvbdemux->start_feed = dm1105_start_feed;
  913. dvbdemux->stop_feed = dm1105_stop_feed;
  914. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  915. DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
  916. ret = dvb_dmx_init(dvbdemux);
  917. if (ret < 0)
  918. goto err_dvb_unregister_adapter;
  919. dmx = &dvbdemux->dmx;
  920. dev->dmxdev.filternum = 256;
  921. dev->dmxdev.demux = dmx;
  922. dev->dmxdev.capabilities = 0;
  923. ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter);
  924. if (ret < 0)
  925. goto err_dvb_dmx_release;
  926. dev->hw_frontend.source = DMX_FRONTEND_0;
  927. ret = dmx->add_frontend(dmx, &dev->hw_frontend);
  928. if (ret < 0)
  929. goto err_dvb_dmxdev_release;
  930. dev->mem_frontend.source = DMX_MEMORY_FE;
  931. ret = dmx->add_frontend(dmx, &dev->mem_frontend);
  932. if (ret < 0)
  933. goto err_remove_hw_frontend;
  934. ret = dmx->connect_frontend(dmx, &dev->hw_frontend);
  935. if (ret < 0)
  936. goto err_remove_mem_frontend;
  937. ret = frontend_init(dev);
  938. if (ret < 0)
  939. goto err_disconnect_frontend;
  940. dvb_net_init(dvb_adapter, &dev->dvbnet, dmx);
  941. dm1105_ir_init(dev);
  942. INIT_WORK(&dev->work, dm1105_dmx_buffer);
  943. sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num);
  944. dev->wq = create_singlethread_workqueue(dev->wqn);
  945. if (!dev->wq)
  946. goto err_dvb_net;
  947. ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED,
  948. DRIVER_NAME, dev);
  949. if (ret < 0)
  950. goto err_workqueue;
  951. return 0;
  952. err_workqueue:
  953. destroy_workqueue(dev->wq);
  954. err_dvb_net:
  955. dvb_net_release(&dev->dvbnet);
  956. err_disconnect_frontend:
  957. dmx->disconnect_frontend(dmx);
  958. err_remove_mem_frontend:
  959. dmx->remove_frontend(dmx, &dev->mem_frontend);
  960. err_remove_hw_frontend:
  961. dmx->remove_frontend(dmx, &dev->hw_frontend);
  962. err_dvb_dmxdev_release:
  963. dvb_dmxdev_release(&dev->dmxdev);
  964. err_dvb_dmx_release:
  965. dvb_dmx_release(dvbdemux);
  966. err_dvb_unregister_adapter:
  967. dvb_unregister_adapter(dvb_adapter);
  968. err_i2c_del_adapters:
  969. i2c_del_adapter(&dev->i2c_bb_adap);
  970. err_i2c_del_adapter:
  971. i2c_del_adapter(&dev->i2c_adap);
  972. err_dm1105_hw_exit:
  973. dm1105_hw_exit(dev);
  974. err_pci_iounmap:
  975. pci_iounmap(pdev, dev->io_mem);
  976. err_pci_release_regions:
  977. pci_release_regions(pdev);
  978. err_pci_disable_device:
  979. pci_disable_device(pdev);
  980. err_kfree:
  981. pci_set_drvdata(pdev, NULL);
  982. kfree(dev);
  983. return ret;
  984. }
  985. static void __devexit dm1105_remove(struct pci_dev *pdev)
  986. {
  987. struct dm1105_dev *dev = pci_get_drvdata(pdev);
  988. struct dvb_adapter *dvb_adapter = &dev->dvb_adapter;
  989. struct dvb_demux *dvbdemux = &dev->demux;
  990. struct dmx_demux *dmx = &dvbdemux->dmx;
  991. dm1105_ir_exit(dev);
  992. dmx->close(dmx);
  993. dvb_net_release(&dev->dvbnet);
  994. if (dev->fe)
  995. dvb_unregister_frontend(dev->fe);
  996. dmx->disconnect_frontend(dmx);
  997. dmx->remove_frontend(dmx, &dev->mem_frontend);
  998. dmx->remove_frontend(dmx, &dev->hw_frontend);
  999. dvb_dmxdev_release(&dev->dmxdev);
  1000. dvb_dmx_release(dvbdemux);
  1001. dvb_unregister_adapter(dvb_adapter);
  1002. if (&dev->i2c_adap)
  1003. i2c_del_adapter(&dev->i2c_adap);
  1004. dm1105_hw_exit(dev);
  1005. synchronize_irq(pdev->irq);
  1006. free_irq(pdev->irq, dev);
  1007. pci_iounmap(pdev, dev->io_mem);
  1008. pci_release_regions(pdev);
  1009. pci_disable_device(pdev);
  1010. pci_set_drvdata(pdev, NULL);
  1011. dm1105_devcount--;
  1012. kfree(dev);
  1013. }
  1014. static struct pci_device_id dm1105_id_table[] __devinitdata = {
  1015. {
  1016. .vendor = PCI_VENDOR_ID_TRIGEM,
  1017. .device = PCI_DEVICE_ID_DM1105,
  1018. .subvendor = PCI_ANY_ID,
  1019. .subdevice = PCI_ANY_ID,
  1020. }, {
  1021. .vendor = PCI_VENDOR_ID_AXESS,
  1022. .device = PCI_DEVICE_ID_DM05,
  1023. .subvendor = PCI_ANY_ID,
  1024. .subdevice = PCI_ANY_ID,
  1025. }, {
  1026. /* empty */
  1027. },
  1028. };
  1029. MODULE_DEVICE_TABLE(pci, dm1105_id_table);
  1030. static struct pci_driver dm1105_driver = {
  1031. .name = DRIVER_NAME,
  1032. .id_table = dm1105_id_table,
  1033. .probe = dm1105_probe,
  1034. .remove = __devexit_p(dm1105_remove),
  1035. };
  1036. static int __init dm1105_init(void)
  1037. {
  1038. return pci_register_driver(&dm1105_driver);
  1039. }
  1040. static void __exit dm1105_exit(void)
  1041. {
  1042. pci_unregister_driver(&dm1105_driver);
  1043. }
  1044. module_init(dm1105_init);
  1045. module_exit(dm1105_exit);
  1046. MODULE_AUTHOR("Igor M. Liplianin <liplianin@me.by>");
  1047. MODULE_DESCRIPTION("SDMC DM1105 DVB driver");
  1048. MODULE_LICENSE("GPL");