vmwgfx_kms.c 49 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836
  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  31. {
  32. if (du->cursor_surface)
  33. vmw_surface_unreference(&du->cursor_surface);
  34. if (du->cursor_dmabuf)
  35. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  36. drm_crtc_cleanup(&du->crtc);
  37. drm_encoder_cleanup(&du->encoder);
  38. drm_connector_cleanup(&du->connector);
  39. }
  40. /*
  41. * Display Unit Cursor functions
  42. */
  43. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  44. u32 *image, u32 width, u32 height,
  45. u32 hotspotX, u32 hotspotY)
  46. {
  47. struct {
  48. u32 cmd;
  49. SVGAFifoCmdDefineAlphaCursor cursor;
  50. } *cmd;
  51. u32 image_size = width * height * 4;
  52. u32 cmd_size = sizeof(*cmd) + image_size;
  53. if (!image)
  54. return -EINVAL;
  55. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  56. if (unlikely(cmd == NULL)) {
  57. DRM_ERROR("Fifo reserve failed.\n");
  58. return -ENOMEM;
  59. }
  60. memset(cmd, 0, sizeof(*cmd));
  61. memcpy(&cmd[1], image, image_size);
  62. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  63. cmd->cursor.id = cpu_to_le32(0);
  64. cmd->cursor.width = cpu_to_le32(width);
  65. cmd->cursor.height = cpu_to_le32(height);
  66. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  67. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  68. vmw_fifo_commit(dev_priv, cmd_size);
  69. return 0;
  70. }
  71. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  72. bool show, int x, int y)
  73. {
  74. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  75. uint32_t count;
  76. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  77. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  78. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  79. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  80. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  81. }
  82. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  83. uint32_t handle, uint32_t width, uint32_t height)
  84. {
  85. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  86. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  87. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  88. struct vmw_surface *surface = NULL;
  89. struct vmw_dma_buffer *dmabuf = NULL;
  90. int ret;
  91. if (handle) {
  92. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  93. handle, &surface);
  94. if (!ret) {
  95. if (!surface->snooper.image) {
  96. DRM_ERROR("surface not suitable for cursor\n");
  97. vmw_surface_unreference(&surface);
  98. return -EINVAL;
  99. }
  100. } else {
  101. ret = vmw_user_dmabuf_lookup(tfile,
  102. handle, &dmabuf);
  103. if (ret) {
  104. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  105. return -EINVAL;
  106. }
  107. }
  108. }
  109. /* takedown old cursor */
  110. if (du->cursor_surface) {
  111. du->cursor_surface->snooper.crtc = NULL;
  112. vmw_surface_unreference(&du->cursor_surface);
  113. }
  114. if (du->cursor_dmabuf)
  115. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  116. /* setup new image */
  117. if (surface) {
  118. /* vmw_user_surface_lookup takes one reference */
  119. du->cursor_surface = surface;
  120. du->cursor_surface->snooper.crtc = crtc;
  121. du->cursor_age = du->cursor_surface->snooper.age;
  122. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  123. 64, 64, du->hotspot_x, du->hotspot_y);
  124. } else if (dmabuf) {
  125. struct ttm_bo_kmap_obj map;
  126. unsigned long kmap_offset;
  127. unsigned long kmap_num;
  128. void *virtual;
  129. bool dummy;
  130. /* vmw_user_surface_lookup takes one reference */
  131. du->cursor_dmabuf = dmabuf;
  132. kmap_offset = 0;
  133. kmap_num = (64*64*4) >> PAGE_SHIFT;
  134. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  135. if (unlikely(ret != 0)) {
  136. DRM_ERROR("reserve failed\n");
  137. return -EINVAL;
  138. }
  139. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  140. if (unlikely(ret != 0))
  141. goto err_unreserve;
  142. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  143. vmw_cursor_update_image(dev_priv, virtual, 64, 64,
  144. du->hotspot_x, du->hotspot_y);
  145. ttm_bo_kunmap(&map);
  146. err_unreserve:
  147. ttm_bo_unreserve(&dmabuf->base);
  148. } else {
  149. vmw_cursor_update_position(dev_priv, false, 0, 0);
  150. return 0;
  151. }
  152. vmw_cursor_update_position(dev_priv, true,
  153. du->cursor_x + du->hotspot_x,
  154. du->cursor_y + du->hotspot_y);
  155. return 0;
  156. }
  157. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  158. {
  159. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  160. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  161. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  162. du->cursor_x = x + crtc->x;
  163. du->cursor_y = y + crtc->y;
  164. vmw_cursor_update_position(dev_priv, shown,
  165. du->cursor_x + du->hotspot_x,
  166. du->cursor_y + du->hotspot_y);
  167. return 0;
  168. }
  169. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  170. struct ttm_object_file *tfile,
  171. struct ttm_buffer_object *bo,
  172. SVGA3dCmdHeader *header)
  173. {
  174. struct ttm_bo_kmap_obj map;
  175. unsigned long kmap_offset;
  176. unsigned long kmap_num;
  177. SVGA3dCopyBox *box;
  178. unsigned box_count;
  179. void *virtual;
  180. bool dummy;
  181. struct vmw_dma_cmd {
  182. SVGA3dCmdHeader header;
  183. SVGA3dCmdSurfaceDMA dma;
  184. } *cmd;
  185. int i, ret;
  186. cmd = container_of(header, struct vmw_dma_cmd, header);
  187. /* No snooper installed */
  188. if (!srf->snooper.image)
  189. return;
  190. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  191. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  192. return;
  193. }
  194. if (cmd->header.size < 64) {
  195. DRM_ERROR("at least one full copy box must be given\n");
  196. return;
  197. }
  198. box = (SVGA3dCopyBox *)&cmd[1];
  199. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  200. sizeof(SVGA3dCopyBox);
  201. if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  202. box->x != 0 || box->y != 0 || box->z != 0 ||
  203. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  204. box->d != 1 || box_count != 1) {
  205. /* TODO handle none page aligned offsets */
  206. /* TODO handle more dst & src != 0 */
  207. /* TODO handle more then one copy */
  208. DRM_ERROR("Cant snoop dma request for cursor!\n");
  209. DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
  210. box->srcx, box->srcy, box->srcz,
  211. box->x, box->y, box->z,
  212. box->w, box->h, box->d, box_count,
  213. cmd->dma.guest.ptr.offset);
  214. return;
  215. }
  216. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  217. kmap_num = (64*64*4) >> PAGE_SHIFT;
  218. ret = ttm_bo_reserve(bo, true, false, false, 0);
  219. if (unlikely(ret != 0)) {
  220. DRM_ERROR("reserve failed\n");
  221. return;
  222. }
  223. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  224. if (unlikely(ret != 0))
  225. goto err_unreserve;
  226. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  227. if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
  228. memcpy(srf->snooper.image, virtual, 64*64*4);
  229. } else {
  230. /* Image is unsigned pointer. */
  231. for (i = 0; i < box->h; i++)
  232. memcpy(srf->snooper.image + i * 64,
  233. virtual + i * cmd->dma.guest.pitch,
  234. box->w * 4);
  235. }
  236. srf->snooper.age++;
  237. /* we can't call this function from this function since execbuf has
  238. * reserved fifo space.
  239. *
  240. * if (srf->snooper.crtc)
  241. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  242. * srf->snooper.image, 64, 64,
  243. * du->hotspot_x, du->hotspot_y);
  244. */
  245. ttm_bo_kunmap(&map);
  246. err_unreserve:
  247. ttm_bo_unreserve(bo);
  248. }
  249. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  250. {
  251. struct drm_device *dev = dev_priv->dev;
  252. struct vmw_display_unit *du;
  253. struct drm_crtc *crtc;
  254. mutex_lock(&dev->mode_config.mutex);
  255. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  256. du = vmw_crtc_to_du(crtc);
  257. if (!du->cursor_surface ||
  258. du->cursor_age == du->cursor_surface->snooper.age)
  259. continue;
  260. du->cursor_age = du->cursor_surface->snooper.age;
  261. vmw_cursor_update_image(dev_priv,
  262. du->cursor_surface->snooper.image,
  263. 64, 64, du->hotspot_x, du->hotspot_y);
  264. }
  265. mutex_unlock(&dev->mode_config.mutex);
  266. }
  267. /*
  268. * Generic framebuffer code
  269. */
  270. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  271. struct drm_file *file_priv,
  272. unsigned int *handle)
  273. {
  274. if (handle)
  275. handle = 0;
  276. return 0;
  277. }
  278. /*
  279. * Surface framebuffer code
  280. */
  281. #define vmw_framebuffer_to_vfbs(x) \
  282. container_of(x, struct vmw_framebuffer_surface, base.base)
  283. struct vmw_framebuffer_surface {
  284. struct vmw_framebuffer base;
  285. struct vmw_surface *surface;
  286. struct vmw_dma_buffer *buffer;
  287. struct list_head head;
  288. struct drm_master *master;
  289. };
  290. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  291. {
  292. struct vmw_framebuffer_surface *vfbs =
  293. vmw_framebuffer_to_vfbs(framebuffer);
  294. struct vmw_master *vmaster = vmw_master(vfbs->master);
  295. mutex_lock(&vmaster->fb_surf_mutex);
  296. list_del(&vfbs->head);
  297. mutex_unlock(&vmaster->fb_surf_mutex);
  298. drm_master_put(&vfbs->master);
  299. drm_framebuffer_cleanup(framebuffer);
  300. vmw_surface_unreference(&vfbs->surface);
  301. ttm_base_object_unref(&vfbs->base.user_obj);
  302. kfree(vfbs);
  303. }
  304. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  305. struct drm_file *file_priv,
  306. struct vmw_framebuffer *framebuffer,
  307. unsigned flags, unsigned color,
  308. struct drm_clip_rect *clips,
  309. unsigned num_clips, int inc)
  310. {
  311. struct drm_clip_rect *clips_ptr;
  312. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  313. struct drm_crtc *crtc;
  314. size_t fifo_size;
  315. int i, num_units;
  316. int ret = 0; /* silence warning */
  317. int left, right, top, bottom;
  318. struct {
  319. SVGA3dCmdHeader header;
  320. SVGA3dCmdBlitSurfaceToScreen body;
  321. } *cmd;
  322. SVGASignedRect *blits;
  323. num_units = 0;
  324. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  325. head) {
  326. if (crtc->fb != &framebuffer->base)
  327. continue;
  328. units[num_units++] = vmw_crtc_to_du(crtc);
  329. }
  330. BUG_ON(!clips || !num_clips);
  331. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  332. cmd = kzalloc(fifo_size, GFP_KERNEL);
  333. if (unlikely(cmd == NULL)) {
  334. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  335. return -ENOMEM;
  336. }
  337. left = clips->x1;
  338. right = clips->x2;
  339. top = clips->y1;
  340. bottom = clips->y2;
  341. clips_ptr = clips;
  342. for (i = 1; i < num_clips; i++, clips_ptr += inc) {
  343. left = min_t(int, left, (int)clips_ptr->x1);
  344. right = max_t(int, right, (int)clips_ptr->x2);
  345. top = min_t(int, top, (int)clips_ptr->y1);
  346. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  347. }
  348. /* only need to do this once */
  349. memset(cmd, 0, fifo_size);
  350. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  351. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  352. cmd->body.srcRect.left = left;
  353. cmd->body.srcRect.right = right;
  354. cmd->body.srcRect.top = top;
  355. cmd->body.srcRect.bottom = bottom;
  356. clips_ptr = clips;
  357. blits = (SVGASignedRect *)&cmd[1];
  358. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  359. blits[i].left = clips_ptr->x1 - left;
  360. blits[i].right = clips_ptr->x2 - left;
  361. blits[i].top = clips_ptr->y1 - top;
  362. blits[i].bottom = clips_ptr->y2 - top;
  363. }
  364. /* do per unit writing, reuse fifo for each */
  365. for (i = 0; i < num_units; i++) {
  366. struct vmw_display_unit *unit = units[i];
  367. int clip_x1 = left - unit->crtc.x;
  368. int clip_y1 = top - unit->crtc.y;
  369. int clip_x2 = right - unit->crtc.x;
  370. int clip_y2 = bottom - unit->crtc.y;
  371. /* skip any crtcs that misses the clip region */
  372. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  373. clip_y1 >= unit->crtc.mode.vdisplay ||
  374. clip_x2 <= 0 || clip_y2 <= 0)
  375. continue;
  376. /* need to reset sid as it is changed by execbuf */
  377. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  378. cmd->body.destScreenId = unit->unit;
  379. /*
  380. * The blit command is a lot more resilient then the
  381. * readback command when it comes to clip rects. So its
  382. * okay to go out of bounds.
  383. */
  384. cmd->body.destRect.left = clip_x1;
  385. cmd->body.destRect.right = clip_x2;
  386. cmd->body.destRect.top = clip_y1;
  387. cmd->body.destRect.bottom = clip_y2;
  388. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  389. fifo_size, 0, NULL);
  390. if (unlikely(ret != 0))
  391. break;
  392. }
  393. kfree(cmd);
  394. return ret;
  395. }
  396. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  397. struct drm_file *file_priv,
  398. unsigned flags, unsigned color,
  399. struct drm_clip_rect *clips,
  400. unsigned num_clips)
  401. {
  402. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  403. struct vmw_master *vmaster = vmw_master(file_priv->master);
  404. struct vmw_framebuffer_surface *vfbs =
  405. vmw_framebuffer_to_vfbs(framebuffer);
  406. struct drm_clip_rect norect;
  407. int ret, inc = 1;
  408. if (unlikely(vfbs->master != file_priv->master))
  409. return -EINVAL;
  410. /* Require ScreenObject support for 3D */
  411. if (!dev_priv->sou_priv)
  412. return -EINVAL;
  413. ret = ttm_read_lock(&vmaster->lock, true);
  414. if (unlikely(ret != 0))
  415. return ret;
  416. if (!num_clips) {
  417. num_clips = 1;
  418. clips = &norect;
  419. norect.x1 = norect.y1 = 0;
  420. norect.x2 = framebuffer->width;
  421. norect.y2 = framebuffer->height;
  422. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  423. num_clips /= 2;
  424. inc = 2; /* skip source rects */
  425. }
  426. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  427. flags, color,
  428. clips, num_clips, inc);
  429. ttm_read_unlock(&vmaster->lock);
  430. return 0;
  431. }
  432. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  433. .destroy = vmw_framebuffer_surface_destroy,
  434. .dirty = vmw_framebuffer_surface_dirty,
  435. .create_handle = vmw_framebuffer_create_handle,
  436. };
  437. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  438. struct drm_file *file_priv,
  439. struct vmw_surface *surface,
  440. struct vmw_framebuffer **out,
  441. const struct drm_mode_fb_cmd
  442. *mode_cmd)
  443. {
  444. struct drm_device *dev = dev_priv->dev;
  445. struct vmw_framebuffer_surface *vfbs;
  446. enum SVGA3dSurfaceFormat format;
  447. struct vmw_master *vmaster = vmw_master(file_priv->master);
  448. int ret;
  449. /* 3D is only supported on HWv8 hosts which supports screen objects */
  450. if (!dev_priv->sou_priv)
  451. return -ENOSYS;
  452. /*
  453. * Sanity checks.
  454. */
  455. if (unlikely(surface->mip_levels[0] != 1 ||
  456. surface->num_sizes != 1 ||
  457. surface->sizes[0].width < mode_cmd->width ||
  458. surface->sizes[0].height < mode_cmd->height ||
  459. surface->sizes[0].depth != 1)) {
  460. DRM_ERROR("Incompatible surface dimensions "
  461. "for requested mode.\n");
  462. return -EINVAL;
  463. }
  464. switch (mode_cmd->depth) {
  465. case 32:
  466. format = SVGA3D_A8R8G8B8;
  467. break;
  468. case 24:
  469. format = SVGA3D_X8R8G8B8;
  470. break;
  471. case 16:
  472. format = SVGA3D_R5G6B5;
  473. break;
  474. case 15:
  475. format = SVGA3D_A1R5G5B5;
  476. break;
  477. case 8:
  478. format = SVGA3D_LUMINANCE8;
  479. break;
  480. default:
  481. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  482. return -EINVAL;
  483. }
  484. if (unlikely(format != surface->format)) {
  485. DRM_ERROR("Invalid surface format for requested mode.\n");
  486. return -EINVAL;
  487. }
  488. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  489. if (!vfbs) {
  490. ret = -ENOMEM;
  491. goto out_err1;
  492. }
  493. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  494. &vmw_framebuffer_surface_funcs);
  495. if (ret)
  496. goto out_err2;
  497. if (!vmw_surface_reference(surface)) {
  498. DRM_ERROR("failed to reference surface %p\n", surface);
  499. goto out_err3;
  500. }
  501. /* XXX get the first 3 from the surface info */
  502. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  503. vfbs->base.base.pitch = mode_cmd->pitch;
  504. vfbs->base.base.depth = mode_cmd->depth;
  505. vfbs->base.base.width = mode_cmd->width;
  506. vfbs->base.base.height = mode_cmd->height;
  507. vfbs->surface = surface;
  508. vfbs->base.user_handle = mode_cmd->handle;
  509. vfbs->master = drm_master_get(file_priv->master);
  510. mutex_lock(&vmaster->fb_surf_mutex);
  511. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  512. mutex_unlock(&vmaster->fb_surf_mutex);
  513. *out = &vfbs->base;
  514. return 0;
  515. out_err3:
  516. drm_framebuffer_cleanup(&vfbs->base.base);
  517. out_err2:
  518. kfree(vfbs);
  519. out_err1:
  520. return ret;
  521. }
  522. /*
  523. * Dmabuf framebuffer code
  524. */
  525. #define vmw_framebuffer_to_vfbd(x) \
  526. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  527. struct vmw_framebuffer_dmabuf {
  528. struct vmw_framebuffer base;
  529. struct vmw_dma_buffer *buffer;
  530. };
  531. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  532. {
  533. struct vmw_framebuffer_dmabuf *vfbd =
  534. vmw_framebuffer_to_vfbd(framebuffer);
  535. drm_framebuffer_cleanup(framebuffer);
  536. vmw_dmabuf_unreference(&vfbd->buffer);
  537. ttm_base_object_unref(&vfbd->base.user_obj);
  538. kfree(vfbd);
  539. }
  540. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  541. struct vmw_framebuffer *framebuffer,
  542. unsigned flags, unsigned color,
  543. struct drm_clip_rect *clips,
  544. unsigned num_clips, int increment)
  545. {
  546. size_t fifo_size;
  547. int i;
  548. struct {
  549. uint32_t header;
  550. SVGAFifoCmdUpdate body;
  551. } *cmd;
  552. fifo_size = sizeof(*cmd) * num_clips;
  553. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  554. if (unlikely(cmd == NULL)) {
  555. DRM_ERROR("Fifo reserve failed.\n");
  556. return -ENOMEM;
  557. }
  558. memset(cmd, 0, fifo_size);
  559. for (i = 0; i < num_clips; i++, clips += increment) {
  560. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  561. cmd[i].body.x = cpu_to_le32(clips->x1);
  562. cmd[i].body.y = cpu_to_le32(clips->y1);
  563. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  564. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  565. }
  566. vmw_fifo_commit(dev_priv, fifo_size);
  567. return 0;
  568. }
  569. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  570. struct vmw_private *dev_priv,
  571. struct vmw_framebuffer *framebuffer)
  572. {
  573. int depth = framebuffer->base.depth;
  574. size_t fifo_size;
  575. int ret;
  576. struct {
  577. uint32_t header;
  578. SVGAFifoCmdDefineGMRFB body;
  579. } *cmd;
  580. /* Emulate RGBA support, contrary to svga_reg.h this is not
  581. * supported by hosts. This is only a problem if we are reading
  582. * this value later and expecting what we uploaded back.
  583. */
  584. if (depth == 32)
  585. depth = 24;
  586. fifo_size = sizeof(*cmd);
  587. cmd = kmalloc(fifo_size, GFP_KERNEL);
  588. if (unlikely(cmd == NULL)) {
  589. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  590. return -ENOMEM;
  591. }
  592. memset(cmd, 0, fifo_size);
  593. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  594. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  595. cmd->body.format.colorDepth = depth;
  596. cmd->body.format.reserved = 0;
  597. cmd->body.bytesPerLine = framebuffer->base.pitch;
  598. cmd->body.ptr.gmrId = framebuffer->user_handle;
  599. cmd->body.ptr.offset = 0;
  600. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  601. fifo_size, 0, NULL);
  602. kfree(cmd);
  603. return ret;
  604. }
  605. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  606. struct vmw_private *dev_priv,
  607. struct vmw_framebuffer *framebuffer,
  608. unsigned flags, unsigned color,
  609. struct drm_clip_rect *clips,
  610. unsigned num_clips, int increment)
  611. {
  612. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  613. struct drm_clip_rect *clips_ptr;
  614. int i, k, num_units, ret;
  615. struct drm_crtc *crtc;
  616. size_t fifo_size;
  617. struct {
  618. uint32_t header;
  619. SVGAFifoCmdBlitGMRFBToScreen body;
  620. } *blits;
  621. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  622. if (unlikely(ret != 0))
  623. return ret; /* define_gmrfb prints warnings */
  624. fifo_size = sizeof(*blits) * num_clips;
  625. blits = kmalloc(fifo_size, GFP_KERNEL);
  626. if (unlikely(blits == NULL)) {
  627. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  628. return -ENOMEM;
  629. }
  630. num_units = 0;
  631. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  632. if (crtc->fb != &framebuffer->base)
  633. continue;
  634. units[num_units++] = vmw_crtc_to_du(crtc);
  635. }
  636. for (k = 0; k < num_units; k++) {
  637. struct vmw_display_unit *unit = units[k];
  638. int hit_num = 0;
  639. clips_ptr = clips;
  640. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  641. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  642. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  643. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  644. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  645. /* skip any crtcs that misses the clip region */
  646. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  647. clip_y1 >= unit->crtc.mode.vdisplay ||
  648. clip_x2 <= 0 || clip_y2 <= 0)
  649. continue;
  650. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  651. blits[hit_num].body.destScreenId = unit->unit;
  652. blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
  653. blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
  654. blits[hit_num].body.destRect.left = clip_x1;
  655. blits[hit_num].body.destRect.top = clip_y1;
  656. blits[hit_num].body.destRect.right = clip_x2;
  657. blits[hit_num].body.destRect.bottom = clip_y2;
  658. hit_num++;
  659. }
  660. /* no clips hit the crtc */
  661. if (hit_num == 0)
  662. continue;
  663. fifo_size = sizeof(*blits) * hit_num;
  664. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  665. fifo_size, 0, NULL);
  666. if (unlikely(ret != 0))
  667. break;
  668. }
  669. kfree(blits);
  670. return ret;
  671. }
  672. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  673. struct drm_file *file_priv,
  674. unsigned flags, unsigned color,
  675. struct drm_clip_rect *clips,
  676. unsigned num_clips)
  677. {
  678. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  679. struct vmw_master *vmaster = vmw_master(file_priv->master);
  680. struct vmw_framebuffer_dmabuf *vfbd =
  681. vmw_framebuffer_to_vfbd(framebuffer);
  682. struct drm_clip_rect norect;
  683. int ret, increment = 1;
  684. ret = ttm_read_lock(&vmaster->lock, true);
  685. if (unlikely(ret != 0))
  686. return ret;
  687. if (!num_clips) {
  688. num_clips = 1;
  689. clips = &norect;
  690. norect.x1 = norect.y1 = 0;
  691. norect.x2 = framebuffer->width;
  692. norect.y2 = framebuffer->height;
  693. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  694. num_clips /= 2;
  695. increment = 2;
  696. }
  697. if (dev_priv->ldu_priv) {
  698. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  699. flags, color,
  700. clips, num_clips, increment);
  701. } else {
  702. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  703. flags, color,
  704. clips, num_clips, increment);
  705. }
  706. ttm_read_unlock(&vmaster->lock);
  707. return ret;
  708. }
  709. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  710. .destroy = vmw_framebuffer_dmabuf_destroy,
  711. .dirty = vmw_framebuffer_dmabuf_dirty,
  712. .create_handle = vmw_framebuffer_create_handle,
  713. };
  714. /**
  715. * Pin the dmabuffer to the start of vram.
  716. */
  717. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  718. {
  719. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  720. struct vmw_framebuffer_dmabuf *vfbd =
  721. vmw_framebuffer_to_vfbd(&vfb->base);
  722. int ret;
  723. /* This code should not be used with screen objects */
  724. BUG_ON(dev_priv->sou_priv);
  725. vmw_overlay_pause_all(dev_priv);
  726. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  727. vmw_overlay_resume_all(dev_priv);
  728. WARN_ON(ret != 0);
  729. return 0;
  730. }
  731. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  732. {
  733. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  734. struct vmw_framebuffer_dmabuf *vfbd =
  735. vmw_framebuffer_to_vfbd(&vfb->base);
  736. if (!vfbd->buffer) {
  737. WARN_ON(!vfbd->buffer);
  738. return 0;
  739. }
  740. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  741. }
  742. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  743. struct vmw_dma_buffer *dmabuf,
  744. struct vmw_framebuffer **out,
  745. const struct drm_mode_fb_cmd
  746. *mode_cmd)
  747. {
  748. struct drm_device *dev = dev_priv->dev;
  749. struct vmw_framebuffer_dmabuf *vfbd;
  750. unsigned int requested_size;
  751. int ret;
  752. requested_size = mode_cmd->height * mode_cmd->pitch;
  753. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  754. DRM_ERROR("Screen buffer object size is too small "
  755. "for requested mode.\n");
  756. return -EINVAL;
  757. }
  758. /* Limited framebuffer color depth support for screen objects */
  759. if (dev_priv->sou_priv) {
  760. switch (mode_cmd->depth) {
  761. case 32:
  762. case 24:
  763. /* Only support 32 bpp for 32 and 24 depth fbs */
  764. if (mode_cmd->bpp == 32)
  765. break;
  766. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  767. mode_cmd->depth, mode_cmd->bpp);
  768. return -EINVAL;
  769. case 16:
  770. case 15:
  771. /* Only support 16 bpp for 16 and 15 depth fbs */
  772. if (mode_cmd->bpp == 16)
  773. break;
  774. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  775. mode_cmd->depth, mode_cmd->bpp);
  776. return -EINVAL;
  777. default:
  778. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  779. return -EINVAL;
  780. }
  781. }
  782. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  783. if (!vfbd) {
  784. ret = -ENOMEM;
  785. goto out_err1;
  786. }
  787. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  788. &vmw_framebuffer_dmabuf_funcs);
  789. if (ret)
  790. goto out_err2;
  791. if (!vmw_dmabuf_reference(dmabuf)) {
  792. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  793. goto out_err3;
  794. }
  795. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  796. vfbd->base.base.pitch = mode_cmd->pitch;
  797. vfbd->base.base.depth = mode_cmd->depth;
  798. vfbd->base.base.width = mode_cmd->width;
  799. vfbd->base.base.height = mode_cmd->height;
  800. if (!dev_priv->sou_priv) {
  801. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  802. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  803. }
  804. vfbd->base.dmabuf = true;
  805. vfbd->buffer = dmabuf;
  806. vfbd->base.user_handle = mode_cmd->handle;
  807. *out = &vfbd->base;
  808. return 0;
  809. out_err3:
  810. drm_framebuffer_cleanup(&vfbd->base.base);
  811. out_err2:
  812. kfree(vfbd);
  813. out_err1:
  814. return ret;
  815. }
  816. /*
  817. * Generic Kernel modesetting functions
  818. */
  819. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  820. struct drm_file *file_priv,
  821. struct drm_mode_fb_cmd *mode_cmd)
  822. {
  823. struct vmw_private *dev_priv = vmw_priv(dev);
  824. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  825. struct vmw_framebuffer *vfb = NULL;
  826. struct vmw_surface *surface = NULL;
  827. struct vmw_dma_buffer *bo = NULL;
  828. struct ttm_base_object *user_obj;
  829. u64 required_size;
  830. int ret;
  831. /**
  832. * This code should be conditioned on Screen Objects not being used.
  833. * If screen objects are used, we can allocate a GMR to hold the
  834. * requested framebuffer.
  835. */
  836. required_size = mode_cmd->pitch * mode_cmd->height;
  837. if (unlikely(required_size > (u64) dev_priv->vram_size)) {
  838. DRM_ERROR("VRAM size is too small for requested mode.\n");
  839. return ERR_PTR(-ENOMEM);
  840. }
  841. /*
  842. * Take a reference on the user object of the resource
  843. * backing the kms fb. This ensures that user-space handle
  844. * lookups on that resource will always work as long as
  845. * it's registered with a kms framebuffer. This is important,
  846. * since vmw_execbuf_process identifies resources in the
  847. * command stream using user-space handles.
  848. */
  849. user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
  850. if (unlikely(user_obj == NULL)) {
  851. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  852. return ERR_PTR(-ENOENT);
  853. }
  854. /**
  855. * End conditioned code.
  856. */
  857. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  858. mode_cmd->handle, &surface);
  859. if (ret)
  860. goto try_dmabuf;
  861. if (!surface->scanout)
  862. goto err_not_scanout;
  863. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
  864. &vfb, mode_cmd);
  865. /* vmw_user_surface_lookup takes one ref so does new_fb */
  866. vmw_surface_unreference(&surface);
  867. if (ret) {
  868. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  869. ttm_base_object_unref(&user_obj);
  870. return ERR_PTR(ret);
  871. } else
  872. vfb->user_obj = user_obj;
  873. return &vfb->base;
  874. try_dmabuf:
  875. DRM_INFO("%s: trying buffer\n", __func__);
  876. ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
  877. if (ret) {
  878. DRM_ERROR("failed to find buffer: %i\n", ret);
  879. return ERR_PTR(-ENOENT);
  880. }
  881. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  882. mode_cmd);
  883. /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
  884. vmw_dmabuf_unreference(&bo);
  885. if (ret) {
  886. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  887. ttm_base_object_unref(&user_obj);
  888. return ERR_PTR(ret);
  889. } else
  890. vfb->user_obj = user_obj;
  891. return &vfb->base;
  892. err_not_scanout:
  893. DRM_ERROR("surface not marked as scanout\n");
  894. /* vmw_user_surface_lookup takes one ref */
  895. vmw_surface_unreference(&surface);
  896. ttm_base_object_unref(&user_obj);
  897. return ERR_PTR(-EINVAL);
  898. }
  899. static struct drm_mode_config_funcs vmw_kms_funcs = {
  900. .fb_create = vmw_kms_fb_create,
  901. };
  902. int vmw_kms_present(struct vmw_private *dev_priv,
  903. struct drm_file *file_priv,
  904. struct vmw_framebuffer *vfb,
  905. struct vmw_surface *surface,
  906. uint32_t sid,
  907. int32_t destX, int32_t destY,
  908. struct drm_vmw_rect *clips,
  909. uint32_t num_clips)
  910. {
  911. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  912. struct drm_crtc *crtc;
  913. size_t fifo_size;
  914. int i, k, num_units;
  915. int ret = 0; /* silence warning */
  916. struct {
  917. SVGA3dCmdHeader header;
  918. SVGA3dCmdBlitSurfaceToScreen body;
  919. } *cmd;
  920. SVGASignedRect *blits;
  921. num_units = 0;
  922. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  923. if (crtc->fb != &vfb->base)
  924. continue;
  925. units[num_units++] = vmw_crtc_to_du(crtc);
  926. }
  927. BUG_ON(surface == NULL);
  928. BUG_ON(!clips || !num_clips);
  929. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  930. cmd = kmalloc(fifo_size, GFP_KERNEL);
  931. if (unlikely(cmd == NULL)) {
  932. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  933. return -ENOMEM;
  934. }
  935. /* only need to do this once */
  936. memset(cmd, 0, fifo_size);
  937. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  938. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  939. cmd->body.srcRect.left = 0;
  940. cmd->body.srcRect.right = surface->sizes[0].width;
  941. cmd->body.srcRect.top = 0;
  942. cmd->body.srcRect.bottom = surface->sizes[0].height;
  943. blits = (SVGASignedRect *)&cmd[1];
  944. for (i = 0; i < num_clips; i++) {
  945. blits[i].left = clips[i].x;
  946. blits[i].right = clips[i].x + clips[i].w;
  947. blits[i].top = clips[i].y;
  948. blits[i].bottom = clips[i].y + clips[i].h;
  949. }
  950. for (k = 0; k < num_units; k++) {
  951. struct vmw_display_unit *unit = units[k];
  952. int clip_x1 = destX - unit->crtc.x;
  953. int clip_y1 = destY - unit->crtc.y;
  954. int clip_x2 = clip_x1 + surface->sizes[0].width;
  955. int clip_y2 = clip_y1 + surface->sizes[0].height;
  956. /* skip any crtcs that misses the clip region */
  957. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  958. clip_y1 >= unit->crtc.mode.vdisplay ||
  959. clip_x2 <= 0 || clip_y2 <= 0)
  960. continue;
  961. /* need to reset sid as it is changed by execbuf */
  962. cmd->body.srcImage.sid = sid;
  963. cmd->body.destScreenId = unit->unit;
  964. /*
  965. * The blit command is a lot more resilient then the
  966. * readback command when it comes to clip rects. So its
  967. * okay to go out of bounds.
  968. */
  969. cmd->body.destRect.left = clip_x1;
  970. cmd->body.destRect.right = clip_x2;
  971. cmd->body.destRect.top = clip_y1;
  972. cmd->body.destRect.bottom = clip_y2;
  973. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  974. fifo_size, 0, NULL);
  975. if (unlikely(ret != 0))
  976. break;
  977. }
  978. kfree(cmd);
  979. return ret;
  980. }
  981. int vmw_kms_readback(struct vmw_private *dev_priv,
  982. struct drm_file *file_priv,
  983. struct vmw_framebuffer *vfb,
  984. struct drm_vmw_fence_rep __user *user_fence_rep,
  985. struct drm_vmw_rect *clips,
  986. uint32_t num_clips)
  987. {
  988. struct vmw_framebuffer_dmabuf *vfbd =
  989. vmw_framebuffer_to_vfbd(&vfb->base);
  990. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  991. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  992. struct drm_crtc *crtc;
  993. size_t fifo_size;
  994. int i, k, ret, num_units, blits_pos;
  995. struct {
  996. uint32_t header;
  997. SVGAFifoCmdDefineGMRFB body;
  998. } *cmd;
  999. struct {
  1000. uint32_t header;
  1001. SVGAFifoCmdBlitScreenToGMRFB body;
  1002. } *blits;
  1003. num_units = 0;
  1004. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1005. if (crtc->fb != &vfb->base)
  1006. continue;
  1007. units[num_units++] = vmw_crtc_to_du(crtc);
  1008. }
  1009. BUG_ON(dmabuf == NULL);
  1010. BUG_ON(!clips || !num_clips);
  1011. /* take a safe guess at fifo size */
  1012. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  1013. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1014. if (unlikely(cmd == NULL)) {
  1015. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1016. return -ENOMEM;
  1017. }
  1018. memset(cmd, 0, fifo_size);
  1019. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1020. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1021. cmd->body.format.colorDepth = vfb->base.depth;
  1022. cmd->body.format.reserved = 0;
  1023. cmd->body.bytesPerLine = vfb->base.pitch;
  1024. cmd->body.ptr.gmrId = vfb->user_handle;
  1025. cmd->body.ptr.offset = 0;
  1026. blits = (void *)&cmd[1];
  1027. blits_pos = 0;
  1028. for (i = 0; i < num_units; i++) {
  1029. struct drm_vmw_rect *c = clips;
  1030. for (k = 0; k < num_clips; k++, c++) {
  1031. /* transform clip coords to crtc origin based coords */
  1032. int clip_x1 = c->x - units[i]->crtc.x;
  1033. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1034. int clip_y1 = c->y - units[i]->crtc.y;
  1035. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1036. int dest_x = c->x;
  1037. int dest_y = c->y;
  1038. /* compensate for clipping, we negate
  1039. * a negative number and add that.
  1040. */
  1041. if (clip_x1 < 0)
  1042. dest_x += -clip_x1;
  1043. if (clip_y1 < 0)
  1044. dest_y += -clip_y1;
  1045. /* clip */
  1046. clip_x1 = max(clip_x1, 0);
  1047. clip_y1 = max(clip_y1, 0);
  1048. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1049. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1050. /* and cull any rects that misses the crtc */
  1051. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1052. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1053. clip_x2 <= 0 || clip_y2 <= 0)
  1054. continue;
  1055. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1056. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1057. blits[blits_pos].body.destOrigin.x = dest_x;
  1058. blits[blits_pos].body.destOrigin.y = dest_y;
  1059. blits[blits_pos].body.srcRect.left = clip_x1;
  1060. blits[blits_pos].body.srcRect.top = clip_y1;
  1061. blits[blits_pos].body.srcRect.right = clip_x2;
  1062. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1063. blits_pos++;
  1064. }
  1065. }
  1066. /* reset size here and use calculated exact size from loops */
  1067. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1068. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1069. 0, user_fence_rep);
  1070. kfree(cmd);
  1071. return ret;
  1072. }
  1073. int vmw_kms_init(struct vmw_private *dev_priv)
  1074. {
  1075. struct drm_device *dev = dev_priv->dev;
  1076. int ret;
  1077. drm_mode_config_init(dev);
  1078. dev->mode_config.funcs = &vmw_kms_funcs;
  1079. dev->mode_config.min_width = 1;
  1080. dev->mode_config.min_height = 1;
  1081. /* assumed largest fb size */
  1082. dev->mode_config.max_width = 8192;
  1083. dev->mode_config.max_height = 8192;
  1084. ret = vmw_kms_init_screen_object_display(dev_priv);
  1085. if (ret) /* Fallback */
  1086. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1087. return 0;
  1088. }
  1089. int vmw_kms_close(struct vmw_private *dev_priv)
  1090. {
  1091. /*
  1092. * Docs says we should take the lock before calling this function
  1093. * but since it destroys encoders and our destructor calls
  1094. * drm_encoder_cleanup which takes the lock we deadlock.
  1095. */
  1096. drm_mode_config_cleanup(dev_priv->dev);
  1097. vmw_kms_close_legacy_display_system(dev_priv);
  1098. return 0;
  1099. }
  1100. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1101. struct drm_file *file_priv)
  1102. {
  1103. struct drm_vmw_cursor_bypass_arg *arg = data;
  1104. struct vmw_display_unit *du;
  1105. struct drm_mode_object *obj;
  1106. struct drm_crtc *crtc;
  1107. int ret = 0;
  1108. mutex_lock(&dev->mode_config.mutex);
  1109. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1110. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1111. du = vmw_crtc_to_du(crtc);
  1112. du->hotspot_x = arg->xhot;
  1113. du->hotspot_y = arg->yhot;
  1114. }
  1115. mutex_unlock(&dev->mode_config.mutex);
  1116. return 0;
  1117. }
  1118. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1119. if (!obj) {
  1120. ret = -EINVAL;
  1121. goto out;
  1122. }
  1123. crtc = obj_to_crtc(obj);
  1124. du = vmw_crtc_to_du(crtc);
  1125. du->hotspot_x = arg->xhot;
  1126. du->hotspot_y = arg->yhot;
  1127. out:
  1128. mutex_unlock(&dev->mode_config.mutex);
  1129. return ret;
  1130. }
  1131. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1132. unsigned width, unsigned height, unsigned pitch,
  1133. unsigned bpp, unsigned depth)
  1134. {
  1135. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1136. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1137. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1138. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1139. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1140. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1141. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1142. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1143. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1144. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1145. return -EINVAL;
  1146. }
  1147. return 0;
  1148. }
  1149. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1150. {
  1151. struct vmw_vga_topology_state *save;
  1152. uint32_t i;
  1153. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1154. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1155. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1156. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1157. vmw_priv->vga_pitchlock =
  1158. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1159. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1160. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1161. SVGA_FIFO_PITCHLOCK);
  1162. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1163. return 0;
  1164. vmw_priv->num_displays = vmw_read(vmw_priv,
  1165. SVGA_REG_NUM_GUEST_DISPLAYS);
  1166. if (vmw_priv->num_displays == 0)
  1167. vmw_priv->num_displays = 1;
  1168. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1169. save = &vmw_priv->vga_save[i];
  1170. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1171. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1172. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1173. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1174. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1175. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1176. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1177. if (i == 0 && vmw_priv->num_displays == 1 &&
  1178. save->width == 0 && save->height == 0) {
  1179. /*
  1180. * It should be fairly safe to assume that these
  1181. * values are uninitialized.
  1182. */
  1183. save->width = vmw_priv->vga_width - save->pos_x;
  1184. save->height = vmw_priv->vga_height - save->pos_y;
  1185. }
  1186. }
  1187. return 0;
  1188. }
  1189. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1190. {
  1191. struct vmw_vga_topology_state *save;
  1192. uint32_t i;
  1193. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1194. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1195. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1196. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1197. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1198. vmw_priv->vga_pitchlock);
  1199. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1200. iowrite32(vmw_priv->vga_pitchlock,
  1201. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1202. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1203. return 0;
  1204. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1205. save = &vmw_priv->vga_save[i];
  1206. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1207. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1208. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1209. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1210. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1211. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1212. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1213. }
  1214. return 0;
  1215. }
  1216. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1217. uint32_t pitch,
  1218. uint32_t height)
  1219. {
  1220. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1221. }
  1222. /**
  1223. * Function called by DRM code called with vbl_lock held.
  1224. */
  1225. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1226. {
  1227. return 0;
  1228. }
  1229. /**
  1230. * Function called by DRM code called with vbl_lock held.
  1231. */
  1232. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1233. {
  1234. return -ENOSYS;
  1235. }
  1236. /**
  1237. * Function called by DRM code called with vbl_lock held.
  1238. */
  1239. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1240. {
  1241. }
  1242. /*
  1243. * Small shared kms functions.
  1244. */
  1245. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1246. struct drm_vmw_rect *rects)
  1247. {
  1248. struct drm_device *dev = dev_priv->dev;
  1249. struct vmw_display_unit *du;
  1250. struct drm_connector *con;
  1251. mutex_lock(&dev->mode_config.mutex);
  1252. #if 0
  1253. {
  1254. unsigned int i;
  1255. DRM_INFO("%s: new layout ", __func__);
  1256. for (i = 0; i < num; i++)
  1257. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1258. rects[i].w, rects[i].h);
  1259. DRM_INFO("\n");
  1260. }
  1261. #endif
  1262. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1263. du = vmw_connector_to_du(con);
  1264. if (num > du->unit) {
  1265. du->pref_width = rects[du->unit].w;
  1266. du->pref_height = rects[du->unit].h;
  1267. du->pref_active = true;
  1268. du->gui_x = rects[du->unit].x;
  1269. du->gui_y = rects[du->unit].y;
  1270. } else {
  1271. du->pref_width = 800;
  1272. du->pref_height = 600;
  1273. du->pref_active = false;
  1274. }
  1275. con->status = vmw_du_connector_detect(con, true);
  1276. }
  1277. mutex_unlock(&dev->mode_config.mutex);
  1278. return 0;
  1279. }
  1280. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1281. {
  1282. }
  1283. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1284. {
  1285. }
  1286. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1287. u16 *r, u16 *g, u16 *b,
  1288. uint32_t start, uint32_t size)
  1289. {
  1290. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1291. int i;
  1292. for (i = 0; i < size; i++) {
  1293. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1294. r[i], g[i], b[i]);
  1295. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1296. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1297. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1298. }
  1299. }
  1300. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1301. {
  1302. }
  1303. void vmw_du_connector_save(struct drm_connector *connector)
  1304. {
  1305. }
  1306. void vmw_du_connector_restore(struct drm_connector *connector)
  1307. {
  1308. }
  1309. enum drm_connector_status
  1310. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1311. {
  1312. uint32_t num_displays;
  1313. struct drm_device *dev = connector->dev;
  1314. struct vmw_private *dev_priv = vmw_priv(dev);
  1315. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1316. mutex_lock(&dev_priv->hw_mutex);
  1317. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1318. mutex_unlock(&dev_priv->hw_mutex);
  1319. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1320. du->pref_active) ?
  1321. connector_status_connected : connector_status_disconnected);
  1322. }
  1323. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1324. /* 640x480@60Hz */
  1325. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1326. 752, 800, 0, 480, 489, 492, 525, 0,
  1327. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1328. /* 800x600@60Hz */
  1329. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1330. 968, 1056, 0, 600, 601, 605, 628, 0,
  1331. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1332. /* 1024x768@60Hz */
  1333. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1334. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1335. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1336. /* 1152x864@75Hz */
  1337. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1338. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1339. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1340. /* 1280x768@60Hz */
  1341. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1342. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1343. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1344. /* 1280x800@60Hz */
  1345. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1346. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1347. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1348. /* 1280x960@60Hz */
  1349. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1350. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1351. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1352. /* 1280x1024@60Hz */
  1353. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1354. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1355. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1356. /* 1360x768@60Hz */
  1357. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1358. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1359. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1360. /* 1440x1050@60Hz */
  1361. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1362. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1363. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1364. /* 1440x900@60Hz */
  1365. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1366. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1367. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1368. /* 1600x1200@60Hz */
  1369. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1370. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1371. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1372. /* 1680x1050@60Hz */
  1373. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1374. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1375. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1376. /* 1792x1344@60Hz */
  1377. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1378. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1379. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1380. /* 1853x1392@60Hz */
  1381. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1382. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1383. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1384. /* 1920x1200@60Hz */
  1385. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1386. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1387. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1388. /* 1920x1440@60Hz */
  1389. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1390. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1391. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1392. /* 2560x1600@60Hz */
  1393. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1394. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1395. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1396. /* Terminate */
  1397. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1398. };
  1399. /**
  1400. * vmw_guess_mode_timing - Provide fake timings for a
  1401. * 60Hz vrefresh mode.
  1402. *
  1403. * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
  1404. * members filled in.
  1405. */
  1406. static void vmw_guess_mode_timing(struct drm_display_mode *mode)
  1407. {
  1408. mode->hsync_start = mode->hdisplay + 50;
  1409. mode->hsync_end = mode->hsync_start + 50;
  1410. mode->htotal = mode->hsync_end + 50;
  1411. mode->vsync_start = mode->vdisplay + 50;
  1412. mode->vsync_end = mode->vsync_start + 50;
  1413. mode->vtotal = mode->vsync_end + 50;
  1414. mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
  1415. mode->vrefresh = drm_mode_vrefresh(mode);
  1416. }
  1417. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1418. uint32_t max_width, uint32_t max_height)
  1419. {
  1420. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1421. struct drm_device *dev = connector->dev;
  1422. struct vmw_private *dev_priv = vmw_priv(dev);
  1423. struct drm_display_mode *mode = NULL;
  1424. struct drm_display_mode *bmode;
  1425. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1426. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1427. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1428. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1429. };
  1430. int i;
  1431. /* Add preferred mode */
  1432. {
  1433. mode = drm_mode_duplicate(dev, &prefmode);
  1434. if (!mode)
  1435. return 0;
  1436. mode->hdisplay = du->pref_width;
  1437. mode->vdisplay = du->pref_height;
  1438. vmw_guess_mode_timing(mode);
  1439. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1440. mode->vdisplay)) {
  1441. drm_mode_probed_add(connector, mode);
  1442. } else {
  1443. drm_mode_destroy(dev, mode);
  1444. mode = NULL;
  1445. }
  1446. if (du->pref_mode) {
  1447. list_del_init(&du->pref_mode->head);
  1448. drm_mode_destroy(dev, du->pref_mode);
  1449. }
  1450. /* mode might be null here, this is intended */
  1451. du->pref_mode = mode;
  1452. }
  1453. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1454. bmode = &vmw_kms_connector_builtin[i];
  1455. if (bmode->hdisplay > max_width ||
  1456. bmode->vdisplay > max_height)
  1457. continue;
  1458. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1459. bmode->vdisplay))
  1460. continue;
  1461. mode = drm_mode_duplicate(dev, bmode);
  1462. if (!mode)
  1463. return 0;
  1464. mode->vrefresh = drm_mode_vrefresh(mode);
  1465. drm_mode_probed_add(connector, mode);
  1466. }
  1467. /* Move the prefered mode first, help apps pick the right mode. */
  1468. if (du->pref_mode)
  1469. list_move(&du->pref_mode->head, &connector->probed_modes);
  1470. drm_mode_connector_list_update(connector);
  1471. return 1;
  1472. }
  1473. int vmw_du_connector_set_property(struct drm_connector *connector,
  1474. struct drm_property *property,
  1475. uint64_t val)
  1476. {
  1477. return 0;
  1478. }
  1479. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1480. struct drm_file *file_priv)
  1481. {
  1482. struct vmw_private *dev_priv = vmw_priv(dev);
  1483. struct drm_vmw_update_layout_arg *arg =
  1484. (struct drm_vmw_update_layout_arg *)data;
  1485. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1486. void __user *user_rects;
  1487. struct drm_vmw_rect *rects;
  1488. unsigned rects_size;
  1489. int ret;
  1490. int i;
  1491. struct drm_mode_config *mode_config = &dev->mode_config;
  1492. ret = ttm_read_lock(&vmaster->lock, true);
  1493. if (unlikely(ret != 0))
  1494. return ret;
  1495. if (!arg->num_outputs) {
  1496. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1497. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1498. goto out_unlock;
  1499. }
  1500. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1501. rects = kzalloc(rects_size, GFP_KERNEL);
  1502. if (unlikely(!rects)) {
  1503. ret = -ENOMEM;
  1504. goto out_unlock;
  1505. }
  1506. user_rects = (void __user *)(unsigned long)arg->rects;
  1507. ret = copy_from_user(rects, user_rects, rects_size);
  1508. if (unlikely(ret != 0)) {
  1509. DRM_ERROR("Failed to get rects.\n");
  1510. ret = -EFAULT;
  1511. goto out_free;
  1512. }
  1513. for (i = 0; i < arg->num_outputs; ++i) {
  1514. if (rects->x < 0 ||
  1515. rects->y < 0 ||
  1516. rects->x + rects->w > mode_config->max_width ||
  1517. rects->y + rects->h > mode_config->max_height) {
  1518. DRM_ERROR("Invalid GUI layout.\n");
  1519. ret = -EINVAL;
  1520. goto out_free;
  1521. }
  1522. }
  1523. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1524. out_free:
  1525. kfree(rects);
  1526. out_unlock:
  1527. ttm_read_unlock(&vmaster->lock);
  1528. return ret;
  1529. }