intel_sdvo.c 78 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "drm_crtc.h"
  35. #include "drm_edid.h"
  36. #include "intel_drv.h"
  37. #include "i915_drm.h"
  38. #include "i915_drv.h"
  39. #include "intel_sdvo_regs.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. int sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint8_t hotplug_active[2];
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. /**
  91. * This is set if we're going to treat the device as TV-out.
  92. *
  93. * While we have these nice friendly flags for output types that ought
  94. * to decide this for us, the S-Video output on our HDMI+S-Video card
  95. * shows up as RGB1 (VGA).
  96. */
  97. bool is_tv;
  98. /* This is for current tv format name */
  99. int tv_format_index;
  100. /**
  101. * This is set if we treat the device as HDMI, instead of DVI.
  102. */
  103. bool is_hdmi;
  104. bool has_hdmi_monitor;
  105. bool has_hdmi_audio;
  106. /**
  107. * This is set if we detect output of sdvo device as LVDS and
  108. * have a valid fixed mode to use with the panel.
  109. */
  110. bool is_lvds;
  111. /**
  112. * This is sdvo fixed pannel mode pointer
  113. */
  114. struct drm_display_mode *sdvo_lvds_fixed_mode;
  115. /* DDC bus used by this SDVO encoder */
  116. uint8_t ddc_bus;
  117. /* Input timings for adjusted_mode */
  118. struct intel_sdvo_dtd input_dtd;
  119. };
  120. struct intel_sdvo_connector {
  121. struct intel_connector base;
  122. /* Mark the type of connector */
  123. uint16_t output_flag;
  124. int force_audio;
  125. /* This contains all current supported TV format */
  126. u8 tv_format_supported[TV_FORMAT_NUM];
  127. int format_supported_num;
  128. struct drm_property *tv_format;
  129. /* add the property for the SDVO-TV */
  130. struct drm_property *left;
  131. struct drm_property *right;
  132. struct drm_property *top;
  133. struct drm_property *bottom;
  134. struct drm_property *hpos;
  135. struct drm_property *vpos;
  136. struct drm_property *contrast;
  137. struct drm_property *saturation;
  138. struct drm_property *hue;
  139. struct drm_property *sharpness;
  140. struct drm_property *flicker_filter;
  141. struct drm_property *flicker_filter_adaptive;
  142. struct drm_property *flicker_filter_2d;
  143. struct drm_property *tv_chroma_filter;
  144. struct drm_property *tv_luma_filter;
  145. struct drm_property *dot_crawl;
  146. /* add the property for the SDVO-TV/LVDS */
  147. struct drm_property *brightness;
  148. /* Add variable to record current setting for the above property */
  149. u32 left_margin, right_margin, top_margin, bottom_margin;
  150. /* this is to get the range of margin.*/
  151. u32 max_hscan, max_vscan;
  152. u32 max_hpos, cur_hpos;
  153. u32 max_vpos, cur_vpos;
  154. u32 cur_brightness, max_brightness;
  155. u32 cur_contrast, max_contrast;
  156. u32 cur_saturation, max_saturation;
  157. u32 cur_hue, max_hue;
  158. u32 cur_sharpness, max_sharpness;
  159. u32 cur_flicker_filter, max_flicker_filter;
  160. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  161. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  162. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  163. u32 cur_tv_luma_filter, max_tv_luma_filter;
  164. u32 cur_dot_crawl, max_dot_crawl;
  165. };
  166. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  167. {
  168. return container_of(encoder, struct intel_sdvo, base.base);
  169. }
  170. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  171. {
  172. return container_of(intel_attached_encoder(connector),
  173. struct intel_sdvo, base);
  174. }
  175. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  176. {
  177. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  178. }
  179. static bool
  180. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  181. static bool
  182. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  183. struct intel_sdvo_connector *intel_sdvo_connector,
  184. int type);
  185. static bool
  186. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  187. struct intel_sdvo_connector *intel_sdvo_connector);
  188. /**
  189. * Writes the SDVOB or SDVOC with the given value, but always writes both
  190. * SDVOB and SDVOC to work around apparent hardware issues (according to
  191. * comments in the BIOS).
  192. */
  193. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  194. {
  195. struct drm_device *dev = intel_sdvo->base.base.dev;
  196. struct drm_i915_private *dev_priv = dev->dev_private;
  197. u32 bval = val, cval = val;
  198. int i;
  199. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  200. I915_WRITE(intel_sdvo->sdvo_reg, val);
  201. I915_READ(intel_sdvo->sdvo_reg);
  202. return;
  203. }
  204. if (intel_sdvo->sdvo_reg == SDVOB) {
  205. cval = I915_READ(SDVOC);
  206. } else {
  207. bval = I915_READ(SDVOB);
  208. }
  209. /*
  210. * Write the registers twice for luck. Sometimes,
  211. * writing them only once doesn't appear to 'stick'.
  212. * The BIOS does this too. Yay, magic
  213. */
  214. for (i = 0; i < 2; i++)
  215. {
  216. I915_WRITE(SDVOB, bval);
  217. I915_READ(SDVOB);
  218. I915_WRITE(SDVOC, cval);
  219. I915_READ(SDVOC);
  220. }
  221. }
  222. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  223. {
  224. struct i2c_msg msgs[] = {
  225. {
  226. .addr = intel_sdvo->slave_addr,
  227. .flags = 0,
  228. .len = 1,
  229. .buf = &addr,
  230. },
  231. {
  232. .addr = intel_sdvo->slave_addr,
  233. .flags = I2C_M_RD,
  234. .len = 1,
  235. .buf = ch,
  236. }
  237. };
  238. int ret;
  239. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  240. return true;
  241. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  242. return false;
  243. }
  244. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  245. /** Mapping of command numbers to names, for debug output */
  246. static const struct _sdvo_cmd_name {
  247. u8 cmd;
  248. const char *name;
  249. } sdvo_cmd_names[] = {
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  293. /* Add the op code for SDVO enhancements */
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  338. /* HDMI op code */
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  359. };
  360. #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
  361. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  362. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  363. const void *args, int args_len)
  364. {
  365. int i;
  366. DRM_DEBUG_KMS("%s: W: %02X ",
  367. SDVO_NAME(intel_sdvo), cmd);
  368. for (i = 0; i < args_len; i++)
  369. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  370. for (; i < 8; i++)
  371. DRM_LOG_KMS(" ");
  372. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  373. if (cmd == sdvo_cmd_names[i].cmd) {
  374. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  375. break;
  376. }
  377. }
  378. if (i == ARRAY_SIZE(sdvo_cmd_names))
  379. DRM_LOG_KMS("(%02X)", cmd);
  380. DRM_LOG_KMS("\n");
  381. }
  382. static const char *cmd_status_names[] = {
  383. "Power on",
  384. "Success",
  385. "Not supported",
  386. "Invalid arg",
  387. "Pending",
  388. "Target not specified",
  389. "Scaling not supported"
  390. };
  391. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  392. const void *args, int args_len)
  393. {
  394. u8 buf[args_len*2 + 2], status;
  395. struct i2c_msg msgs[args_len + 3];
  396. int i, ret;
  397. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  398. for (i = 0; i < args_len; i++) {
  399. msgs[i].addr = intel_sdvo->slave_addr;
  400. msgs[i].flags = 0;
  401. msgs[i].len = 2;
  402. msgs[i].buf = buf + 2 *i;
  403. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  404. buf[2*i + 1] = ((u8*)args)[i];
  405. }
  406. msgs[i].addr = intel_sdvo->slave_addr;
  407. msgs[i].flags = 0;
  408. msgs[i].len = 2;
  409. msgs[i].buf = buf + 2*i;
  410. buf[2*i + 0] = SDVO_I2C_OPCODE;
  411. buf[2*i + 1] = cmd;
  412. /* the following two are to read the response */
  413. status = SDVO_I2C_CMD_STATUS;
  414. msgs[i+1].addr = intel_sdvo->slave_addr;
  415. msgs[i+1].flags = 0;
  416. msgs[i+1].len = 1;
  417. msgs[i+1].buf = &status;
  418. msgs[i+2].addr = intel_sdvo->slave_addr;
  419. msgs[i+2].flags = I2C_M_RD;
  420. msgs[i+2].len = 1;
  421. msgs[i+2].buf = &status;
  422. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  423. if (ret < 0) {
  424. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  425. return false;
  426. }
  427. if (ret != i+3) {
  428. /* failure in I2C transfer */
  429. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  430. return false;
  431. }
  432. return true;
  433. }
  434. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  435. void *response, int response_len)
  436. {
  437. u8 retry = 5;
  438. u8 status;
  439. int i;
  440. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  441. /*
  442. * The documentation states that all commands will be
  443. * processed within 15µs, and that we need only poll
  444. * the status byte a maximum of 3 times in order for the
  445. * command to be complete.
  446. *
  447. * Check 5 times in case the hardware failed to read the docs.
  448. */
  449. if (!intel_sdvo_read_byte(intel_sdvo,
  450. SDVO_I2C_CMD_STATUS,
  451. &status))
  452. goto log_fail;
  453. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  454. udelay(15);
  455. if (!intel_sdvo_read_byte(intel_sdvo,
  456. SDVO_I2C_CMD_STATUS,
  457. &status))
  458. goto log_fail;
  459. }
  460. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  461. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  462. else
  463. DRM_LOG_KMS("(??? %d)", status);
  464. if (status != SDVO_CMD_STATUS_SUCCESS)
  465. goto log_fail;
  466. /* Read the command response */
  467. for (i = 0; i < response_len; i++) {
  468. if (!intel_sdvo_read_byte(intel_sdvo,
  469. SDVO_I2C_RETURN_0 + i,
  470. &((u8 *)response)[i]))
  471. goto log_fail;
  472. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  473. }
  474. DRM_LOG_KMS("\n");
  475. return true;
  476. log_fail:
  477. DRM_LOG_KMS("... failed\n");
  478. return false;
  479. }
  480. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  481. {
  482. if (mode->clock >= 100000)
  483. return 1;
  484. else if (mode->clock >= 50000)
  485. return 2;
  486. else
  487. return 4;
  488. }
  489. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  490. u8 ddc_bus)
  491. {
  492. /* This must be the immediately preceding write before the i2c xfer */
  493. return intel_sdvo_write_cmd(intel_sdvo,
  494. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  495. &ddc_bus, 1);
  496. }
  497. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  498. {
  499. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  500. return false;
  501. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  502. }
  503. static bool
  504. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  505. {
  506. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  507. return false;
  508. return intel_sdvo_read_response(intel_sdvo, value, len);
  509. }
  510. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  511. {
  512. struct intel_sdvo_set_target_input_args targets = {0};
  513. return intel_sdvo_set_value(intel_sdvo,
  514. SDVO_CMD_SET_TARGET_INPUT,
  515. &targets, sizeof(targets));
  516. }
  517. /**
  518. * Return whether each input is trained.
  519. *
  520. * This function is making an assumption about the layout of the response,
  521. * which should be checked against the docs.
  522. */
  523. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  524. {
  525. struct intel_sdvo_get_trained_inputs_response response;
  526. BUILD_BUG_ON(sizeof(response) != 1);
  527. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  528. &response, sizeof(response)))
  529. return false;
  530. *input_1 = response.input0_trained;
  531. *input_2 = response.input1_trained;
  532. return true;
  533. }
  534. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  535. u16 outputs)
  536. {
  537. return intel_sdvo_set_value(intel_sdvo,
  538. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  539. &outputs, sizeof(outputs));
  540. }
  541. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  542. int mode)
  543. {
  544. u8 state = SDVO_ENCODER_STATE_ON;
  545. switch (mode) {
  546. case DRM_MODE_DPMS_ON:
  547. state = SDVO_ENCODER_STATE_ON;
  548. break;
  549. case DRM_MODE_DPMS_STANDBY:
  550. state = SDVO_ENCODER_STATE_STANDBY;
  551. break;
  552. case DRM_MODE_DPMS_SUSPEND:
  553. state = SDVO_ENCODER_STATE_SUSPEND;
  554. break;
  555. case DRM_MODE_DPMS_OFF:
  556. state = SDVO_ENCODER_STATE_OFF;
  557. break;
  558. }
  559. return intel_sdvo_set_value(intel_sdvo,
  560. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  561. }
  562. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  563. int *clock_min,
  564. int *clock_max)
  565. {
  566. struct intel_sdvo_pixel_clock_range clocks;
  567. BUILD_BUG_ON(sizeof(clocks) != 4);
  568. if (!intel_sdvo_get_value(intel_sdvo,
  569. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  570. &clocks, sizeof(clocks)))
  571. return false;
  572. /* Convert the values from units of 10 kHz to kHz. */
  573. *clock_min = clocks.min * 10;
  574. *clock_max = clocks.max * 10;
  575. return true;
  576. }
  577. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  578. u16 outputs)
  579. {
  580. return intel_sdvo_set_value(intel_sdvo,
  581. SDVO_CMD_SET_TARGET_OUTPUT,
  582. &outputs, sizeof(outputs));
  583. }
  584. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  585. struct intel_sdvo_dtd *dtd)
  586. {
  587. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  588. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  589. }
  590. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  591. struct intel_sdvo_dtd *dtd)
  592. {
  593. return intel_sdvo_set_timing(intel_sdvo,
  594. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  595. }
  596. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  597. struct intel_sdvo_dtd *dtd)
  598. {
  599. return intel_sdvo_set_timing(intel_sdvo,
  600. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  601. }
  602. static bool
  603. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  604. uint16_t clock,
  605. uint16_t width,
  606. uint16_t height)
  607. {
  608. struct intel_sdvo_preferred_input_timing_args args;
  609. memset(&args, 0, sizeof(args));
  610. args.clock = clock;
  611. args.width = width;
  612. args.height = height;
  613. args.interlace = 0;
  614. if (intel_sdvo->is_lvds &&
  615. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  616. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  617. args.scaled = 1;
  618. return intel_sdvo_set_value(intel_sdvo,
  619. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  620. &args, sizeof(args));
  621. }
  622. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  623. struct intel_sdvo_dtd *dtd)
  624. {
  625. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  626. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  627. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  628. &dtd->part1, sizeof(dtd->part1)) &&
  629. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  630. &dtd->part2, sizeof(dtd->part2));
  631. }
  632. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  633. {
  634. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  635. }
  636. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  637. const struct drm_display_mode *mode)
  638. {
  639. uint16_t width, height;
  640. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  641. uint16_t h_sync_offset, v_sync_offset;
  642. width = mode->crtc_hdisplay;
  643. height = mode->crtc_vdisplay;
  644. /* do some mode translations */
  645. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  646. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  647. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  648. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  649. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  650. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  651. dtd->part1.clock = mode->clock / 10;
  652. dtd->part1.h_active = width & 0xff;
  653. dtd->part1.h_blank = h_blank_len & 0xff;
  654. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  655. ((h_blank_len >> 8) & 0xf);
  656. dtd->part1.v_active = height & 0xff;
  657. dtd->part1.v_blank = v_blank_len & 0xff;
  658. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  659. ((v_blank_len >> 8) & 0xf);
  660. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  661. dtd->part2.h_sync_width = h_sync_len & 0xff;
  662. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  663. (v_sync_len & 0xf);
  664. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  665. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  666. ((v_sync_len & 0x30) >> 4);
  667. dtd->part2.dtd_flags = 0x18;
  668. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  669. dtd->part2.dtd_flags |= 0x2;
  670. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  671. dtd->part2.dtd_flags |= 0x4;
  672. dtd->part2.sdvo_flags = 0;
  673. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  674. dtd->part2.reserved = 0;
  675. }
  676. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  677. const struct intel_sdvo_dtd *dtd)
  678. {
  679. mode->hdisplay = dtd->part1.h_active;
  680. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  681. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  682. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  683. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  684. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  685. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  686. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  687. mode->vdisplay = dtd->part1.v_active;
  688. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  689. mode->vsync_start = mode->vdisplay;
  690. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  691. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  692. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  693. mode->vsync_end = mode->vsync_start +
  694. (dtd->part2.v_sync_off_width & 0xf);
  695. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  696. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  697. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  698. mode->clock = dtd->part1.clock * 10;
  699. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  700. if (dtd->part2.dtd_flags & 0x2)
  701. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  702. if (dtd->part2.dtd_flags & 0x4)
  703. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  704. }
  705. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  706. {
  707. struct intel_sdvo_encode encode;
  708. BUILD_BUG_ON(sizeof(encode) != 2);
  709. return intel_sdvo_get_value(intel_sdvo,
  710. SDVO_CMD_GET_SUPP_ENCODE,
  711. &encode, sizeof(encode));
  712. }
  713. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  714. uint8_t mode)
  715. {
  716. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  717. }
  718. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  719. uint8_t mode)
  720. {
  721. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  722. }
  723. #if 0
  724. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  725. {
  726. int i, j;
  727. uint8_t set_buf_index[2];
  728. uint8_t av_split;
  729. uint8_t buf_size;
  730. uint8_t buf[48];
  731. uint8_t *pos;
  732. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  733. for (i = 0; i <= av_split; i++) {
  734. set_buf_index[0] = i; set_buf_index[1] = 0;
  735. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  736. set_buf_index, 2);
  737. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  738. intel_sdvo_read_response(encoder, &buf_size, 1);
  739. pos = buf;
  740. for (j = 0; j <= buf_size; j += 8) {
  741. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  742. NULL, 0);
  743. intel_sdvo_read_response(encoder, pos, 8);
  744. pos += 8;
  745. }
  746. }
  747. }
  748. #endif
  749. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  750. {
  751. struct dip_infoframe avi_if = {
  752. .type = DIP_TYPE_AVI,
  753. .ver = DIP_VERSION_AVI,
  754. .len = DIP_LEN_AVI,
  755. };
  756. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  757. uint8_t set_buf_index[2] = { 1, 0 };
  758. uint64_t *data = (uint64_t *)&avi_if;
  759. unsigned i;
  760. intel_dip_infoframe_csum(&avi_if);
  761. if (!intel_sdvo_set_value(intel_sdvo,
  762. SDVO_CMD_SET_HBUF_INDEX,
  763. set_buf_index, 2))
  764. return false;
  765. for (i = 0; i < sizeof(avi_if); i += 8) {
  766. if (!intel_sdvo_set_value(intel_sdvo,
  767. SDVO_CMD_SET_HBUF_DATA,
  768. data, 8))
  769. return false;
  770. data++;
  771. }
  772. return intel_sdvo_set_value(intel_sdvo,
  773. SDVO_CMD_SET_HBUF_TXRATE,
  774. &tx_rate, 1);
  775. }
  776. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  777. {
  778. struct intel_sdvo_tv_format format;
  779. uint32_t format_map;
  780. format_map = 1 << intel_sdvo->tv_format_index;
  781. memset(&format, 0, sizeof(format));
  782. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  783. BUILD_BUG_ON(sizeof(format) != 6);
  784. return intel_sdvo_set_value(intel_sdvo,
  785. SDVO_CMD_SET_TV_FORMAT,
  786. &format, sizeof(format));
  787. }
  788. static bool
  789. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  790. struct drm_display_mode *mode)
  791. {
  792. struct intel_sdvo_dtd output_dtd;
  793. if (!intel_sdvo_set_target_output(intel_sdvo,
  794. intel_sdvo->attached_output))
  795. return false;
  796. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  797. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  798. return false;
  799. return true;
  800. }
  801. static bool
  802. intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
  803. struct drm_display_mode *mode,
  804. struct drm_display_mode *adjusted_mode)
  805. {
  806. /* Reset the input timing to the screen. Assume always input 0. */
  807. if (!intel_sdvo_set_target_input(intel_sdvo))
  808. return false;
  809. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  810. mode->clock / 10,
  811. mode->hdisplay,
  812. mode->vdisplay))
  813. return false;
  814. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  815. &intel_sdvo->input_dtd))
  816. return false;
  817. intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
  818. drm_mode_set_crtcinfo(adjusted_mode, 0);
  819. return true;
  820. }
  821. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  822. struct drm_display_mode *mode,
  823. struct drm_display_mode *adjusted_mode)
  824. {
  825. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  826. int multiplier;
  827. /* We need to construct preferred input timings based on our
  828. * output timings. To do that, we have to set the output
  829. * timings, even though this isn't really the right place in
  830. * the sequence to do it. Oh well.
  831. */
  832. if (intel_sdvo->is_tv) {
  833. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  834. return false;
  835. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  836. mode,
  837. adjusted_mode);
  838. } else if (intel_sdvo->is_lvds) {
  839. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  840. intel_sdvo->sdvo_lvds_fixed_mode))
  841. return false;
  842. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  843. mode,
  844. adjusted_mode);
  845. }
  846. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  847. * SDVO device will factor out the multiplier during mode_set.
  848. */
  849. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  850. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  851. return true;
  852. }
  853. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  854. struct drm_display_mode *mode,
  855. struct drm_display_mode *adjusted_mode)
  856. {
  857. struct drm_device *dev = encoder->dev;
  858. struct drm_i915_private *dev_priv = dev->dev_private;
  859. struct drm_crtc *crtc = encoder->crtc;
  860. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  861. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  862. u32 sdvox;
  863. struct intel_sdvo_in_out_map in_out;
  864. struct intel_sdvo_dtd input_dtd;
  865. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  866. int rate;
  867. if (!mode)
  868. return;
  869. /* First, set the input mapping for the first input to our controlled
  870. * output. This is only correct if we're a single-input device, in
  871. * which case the first input is the output from the appropriate SDVO
  872. * channel on the motherboard. In a two-input device, the first input
  873. * will be SDVOB and the second SDVOC.
  874. */
  875. in_out.in0 = intel_sdvo->attached_output;
  876. in_out.in1 = 0;
  877. intel_sdvo_set_value(intel_sdvo,
  878. SDVO_CMD_SET_IN_OUT_MAP,
  879. &in_out, sizeof(in_out));
  880. /* Set the output timings to the screen */
  881. if (!intel_sdvo_set_target_output(intel_sdvo,
  882. intel_sdvo->attached_output))
  883. return;
  884. /* We have tried to get input timing in mode_fixup, and filled into
  885. * adjusted_mode.
  886. */
  887. if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
  888. input_dtd = intel_sdvo->input_dtd;
  889. } else {
  890. /* Set the output timing to the screen */
  891. if (!intel_sdvo_set_target_output(intel_sdvo,
  892. intel_sdvo->attached_output))
  893. return;
  894. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  895. (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
  896. }
  897. /* Set the input timing to the screen. Assume always input 0. */
  898. if (!intel_sdvo_set_target_input(intel_sdvo))
  899. return;
  900. if (intel_sdvo->has_hdmi_monitor) {
  901. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  902. intel_sdvo_set_colorimetry(intel_sdvo,
  903. SDVO_COLORIMETRY_RGB256);
  904. intel_sdvo_set_avi_infoframe(intel_sdvo);
  905. } else
  906. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  907. if (intel_sdvo->is_tv &&
  908. !intel_sdvo_set_tv_format(intel_sdvo))
  909. return;
  910. (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
  911. switch (pixel_multiplier) {
  912. default:
  913. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  914. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  915. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  916. }
  917. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  918. return;
  919. /* Set the SDVO control regs. */
  920. if (INTEL_INFO(dev)->gen >= 4) {
  921. sdvox = 0;
  922. if (intel_sdvo->is_hdmi)
  923. sdvox |= intel_sdvo->color_range;
  924. if (INTEL_INFO(dev)->gen < 5)
  925. sdvox |= SDVO_BORDER_ENABLE;
  926. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  927. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  928. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  929. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  930. } else {
  931. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  932. switch (intel_sdvo->sdvo_reg) {
  933. case SDVOB:
  934. sdvox &= SDVOB_PRESERVE_MASK;
  935. break;
  936. case SDVOC:
  937. sdvox &= SDVOC_PRESERVE_MASK;
  938. break;
  939. }
  940. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  941. }
  942. if (intel_crtc->pipe == 1)
  943. sdvox |= SDVO_PIPE_B_SELECT;
  944. if (intel_sdvo->has_hdmi_audio)
  945. sdvox |= SDVO_AUDIO_ENABLE;
  946. if (INTEL_INFO(dev)->gen >= 4) {
  947. /* done in crtc_mode_set as the dpll_md reg must be written early */
  948. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  949. /* done in crtc_mode_set as it lives inside the dpll register */
  950. } else {
  951. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  952. }
  953. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  954. INTEL_INFO(dev)->gen < 5)
  955. sdvox |= SDVO_STALL_SELECT;
  956. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  957. }
  958. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  959. {
  960. struct drm_device *dev = encoder->dev;
  961. struct drm_i915_private *dev_priv = dev->dev_private;
  962. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  963. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  964. u32 temp;
  965. if (mode != DRM_MODE_DPMS_ON) {
  966. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  967. if (0)
  968. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  969. if (mode == DRM_MODE_DPMS_OFF) {
  970. temp = I915_READ(intel_sdvo->sdvo_reg);
  971. if ((temp & SDVO_ENABLE) != 0) {
  972. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  973. }
  974. }
  975. } else {
  976. bool input1, input2;
  977. int i;
  978. u8 status;
  979. temp = I915_READ(intel_sdvo->sdvo_reg);
  980. if ((temp & SDVO_ENABLE) == 0)
  981. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  982. for (i = 0; i < 2; i++)
  983. intel_wait_for_vblank(dev, intel_crtc->pipe);
  984. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  985. /* Warn if the device reported failure to sync.
  986. * A lot of SDVO devices fail to notify of sync, but it's
  987. * a given it the status is a success, we succeeded.
  988. */
  989. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  990. DRM_DEBUG_KMS("First %s output reported failure to "
  991. "sync\n", SDVO_NAME(intel_sdvo));
  992. }
  993. if (0)
  994. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  995. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  996. }
  997. return;
  998. }
  999. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1000. struct drm_display_mode *mode)
  1001. {
  1002. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1003. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1004. return MODE_NO_DBLESCAN;
  1005. if (intel_sdvo->pixel_clock_min > mode->clock)
  1006. return MODE_CLOCK_LOW;
  1007. if (intel_sdvo->pixel_clock_max < mode->clock)
  1008. return MODE_CLOCK_HIGH;
  1009. if (intel_sdvo->is_lvds) {
  1010. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1011. return MODE_PANEL;
  1012. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1013. return MODE_PANEL;
  1014. }
  1015. return MODE_OK;
  1016. }
  1017. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1018. {
  1019. BUILD_BUG_ON(sizeof(*caps) != 8);
  1020. if (!intel_sdvo_get_value(intel_sdvo,
  1021. SDVO_CMD_GET_DEVICE_CAPS,
  1022. caps, sizeof(*caps)))
  1023. return false;
  1024. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1025. " vendor_id: %d\n"
  1026. " device_id: %d\n"
  1027. " device_rev_id: %d\n"
  1028. " sdvo_version_major: %d\n"
  1029. " sdvo_version_minor: %d\n"
  1030. " sdvo_inputs_mask: %d\n"
  1031. " smooth_scaling: %d\n"
  1032. " sharp_scaling: %d\n"
  1033. " up_scaling: %d\n"
  1034. " down_scaling: %d\n"
  1035. " stall_support: %d\n"
  1036. " output_flags: %d\n",
  1037. caps->vendor_id,
  1038. caps->device_id,
  1039. caps->device_rev_id,
  1040. caps->sdvo_version_major,
  1041. caps->sdvo_version_minor,
  1042. caps->sdvo_inputs_mask,
  1043. caps->smooth_scaling,
  1044. caps->sharp_scaling,
  1045. caps->up_scaling,
  1046. caps->down_scaling,
  1047. caps->stall_support,
  1048. caps->output_flags);
  1049. return true;
  1050. }
  1051. static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
  1052. {
  1053. u8 response[2];
  1054. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1055. &response, 2) && response[0];
  1056. }
  1057. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1058. {
  1059. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1060. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
  1061. }
  1062. static bool
  1063. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1064. {
  1065. /* Is there more than one type of output? */
  1066. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1067. }
  1068. static struct edid *
  1069. intel_sdvo_get_edid(struct drm_connector *connector)
  1070. {
  1071. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1072. return drm_get_edid(connector, &sdvo->ddc);
  1073. }
  1074. /* Mac mini hack -- use the same DDC as the analog connector */
  1075. static struct edid *
  1076. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1077. {
  1078. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1079. return drm_get_edid(connector,
  1080. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1081. }
  1082. enum drm_connector_status
  1083. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1084. {
  1085. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1086. enum drm_connector_status status;
  1087. struct edid *edid;
  1088. edid = intel_sdvo_get_edid(connector);
  1089. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1090. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1091. /*
  1092. * Don't use the 1 as the argument of DDC bus switch to get
  1093. * the EDID. It is used for SDVO SPD ROM.
  1094. */
  1095. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1096. intel_sdvo->ddc_bus = ddc;
  1097. edid = intel_sdvo_get_edid(connector);
  1098. if (edid)
  1099. break;
  1100. }
  1101. /*
  1102. * If we found the EDID on the other bus,
  1103. * assume that is the correct DDC bus.
  1104. */
  1105. if (edid == NULL)
  1106. intel_sdvo->ddc_bus = saved_ddc;
  1107. }
  1108. /*
  1109. * When there is no edid and no monitor is connected with VGA
  1110. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1111. */
  1112. if (edid == NULL)
  1113. edid = intel_sdvo_get_analog_edid(connector);
  1114. status = connector_status_unknown;
  1115. if (edid != NULL) {
  1116. /* DDC bus is shared, match EDID to connector type */
  1117. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1118. status = connector_status_connected;
  1119. if (intel_sdvo->is_hdmi) {
  1120. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1121. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1122. }
  1123. } else
  1124. status = connector_status_disconnected;
  1125. connector->display_info.raw_edid = NULL;
  1126. kfree(edid);
  1127. }
  1128. if (status == connector_status_connected) {
  1129. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1130. if (intel_sdvo_connector->force_audio)
  1131. intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
  1132. }
  1133. return status;
  1134. }
  1135. static enum drm_connector_status
  1136. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1137. {
  1138. uint16_t response;
  1139. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1140. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1141. enum drm_connector_status ret;
  1142. if (!intel_sdvo_write_cmd(intel_sdvo,
  1143. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1144. return connector_status_unknown;
  1145. /* add 30ms delay when the output type might be TV */
  1146. if (intel_sdvo->caps.output_flags &
  1147. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1148. mdelay(30);
  1149. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1150. return connector_status_unknown;
  1151. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1152. response & 0xff, response >> 8,
  1153. intel_sdvo_connector->output_flag);
  1154. if (response == 0)
  1155. return connector_status_disconnected;
  1156. intel_sdvo->attached_output = response;
  1157. intel_sdvo->has_hdmi_monitor = false;
  1158. intel_sdvo->has_hdmi_audio = false;
  1159. if ((intel_sdvo_connector->output_flag & response) == 0)
  1160. ret = connector_status_disconnected;
  1161. else if (IS_TMDS(intel_sdvo_connector))
  1162. ret = intel_sdvo_tmds_sink_detect(connector);
  1163. else {
  1164. struct edid *edid;
  1165. /* if we have an edid check it matches the connection */
  1166. edid = intel_sdvo_get_edid(connector);
  1167. if (edid == NULL)
  1168. edid = intel_sdvo_get_analog_edid(connector);
  1169. if (edid != NULL) {
  1170. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1171. ret = connector_status_disconnected;
  1172. else
  1173. ret = connector_status_connected;
  1174. connector->display_info.raw_edid = NULL;
  1175. kfree(edid);
  1176. } else
  1177. ret = connector_status_connected;
  1178. }
  1179. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1180. if (ret == connector_status_connected) {
  1181. intel_sdvo->is_tv = false;
  1182. intel_sdvo->is_lvds = false;
  1183. intel_sdvo->base.needs_tv_clock = false;
  1184. if (response & SDVO_TV_MASK) {
  1185. intel_sdvo->is_tv = true;
  1186. intel_sdvo->base.needs_tv_clock = true;
  1187. }
  1188. if (response & SDVO_LVDS_MASK)
  1189. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1190. }
  1191. return ret;
  1192. }
  1193. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1194. {
  1195. struct edid *edid;
  1196. /* set the bus switch and get the modes */
  1197. edid = intel_sdvo_get_edid(connector);
  1198. /*
  1199. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1200. * link between analog and digital outputs. So, if the regular SDVO
  1201. * DDC fails, check to see if the analog output is disconnected, in
  1202. * which case we'll look there for the digital DDC data.
  1203. */
  1204. if (edid == NULL)
  1205. edid = intel_sdvo_get_analog_edid(connector);
  1206. if (edid != NULL) {
  1207. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1208. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1209. bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector);
  1210. if (connector_is_digital == monitor_is_digital) {
  1211. drm_mode_connector_update_edid_property(connector, edid);
  1212. drm_add_edid_modes(connector, edid);
  1213. }
  1214. connector->display_info.raw_edid = NULL;
  1215. kfree(edid);
  1216. }
  1217. }
  1218. /*
  1219. * Set of SDVO TV modes.
  1220. * Note! This is in reply order (see loop in get_tv_modes).
  1221. * XXX: all 60Hz refresh?
  1222. */
  1223. static const struct drm_display_mode sdvo_tv_modes[] = {
  1224. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1225. 416, 0, 200, 201, 232, 233, 0,
  1226. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1227. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1228. 416, 0, 240, 241, 272, 273, 0,
  1229. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1230. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1231. 496, 0, 300, 301, 332, 333, 0,
  1232. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1233. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1234. 736, 0, 350, 351, 382, 383, 0,
  1235. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1236. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1237. 736, 0, 400, 401, 432, 433, 0,
  1238. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1239. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1240. 736, 0, 480, 481, 512, 513, 0,
  1241. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1242. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1243. 800, 0, 480, 481, 512, 513, 0,
  1244. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1245. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1246. 800, 0, 576, 577, 608, 609, 0,
  1247. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1248. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1249. 816, 0, 350, 351, 382, 383, 0,
  1250. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1251. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1252. 816, 0, 400, 401, 432, 433, 0,
  1253. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1254. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1255. 816, 0, 480, 481, 512, 513, 0,
  1256. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1257. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1258. 816, 0, 540, 541, 572, 573, 0,
  1259. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1260. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1261. 816, 0, 576, 577, 608, 609, 0,
  1262. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1263. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1264. 864, 0, 576, 577, 608, 609, 0,
  1265. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1266. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1267. 896, 0, 600, 601, 632, 633, 0,
  1268. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1269. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1270. 928, 0, 624, 625, 656, 657, 0,
  1271. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1272. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1273. 1016, 0, 766, 767, 798, 799, 0,
  1274. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1275. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1276. 1120, 0, 768, 769, 800, 801, 0,
  1277. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1278. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1279. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1280. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1281. };
  1282. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1283. {
  1284. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1285. struct intel_sdvo_sdtv_resolution_request tv_res;
  1286. uint32_t reply = 0, format_map = 0;
  1287. int i;
  1288. /* Read the list of supported input resolutions for the selected TV
  1289. * format.
  1290. */
  1291. format_map = 1 << intel_sdvo->tv_format_index;
  1292. memcpy(&tv_res, &format_map,
  1293. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1294. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1295. return;
  1296. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1297. if (!intel_sdvo_write_cmd(intel_sdvo,
  1298. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1299. &tv_res, sizeof(tv_res)))
  1300. return;
  1301. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1302. return;
  1303. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1304. if (reply & (1 << i)) {
  1305. struct drm_display_mode *nmode;
  1306. nmode = drm_mode_duplicate(connector->dev,
  1307. &sdvo_tv_modes[i]);
  1308. if (nmode)
  1309. drm_mode_probed_add(connector, nmode);
  1310. }
  1311. }
  1312. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1313. {
  1314. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1315. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1316. struct drm_display_mode *newmode;
  1317. /*
  1318. * Attempt to get the mode list from DDC.
  1319. * Assume that the preferred modes are
  1320. * arranged in priority order.
  1321. */
  1322. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1323. if (list_empty(&connector->probed_modes) == false)
  1324. goto end;
  1325. /* Fetch modes from VBT */
  1326. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1327. newmode = drm_mode_duplicate(connector->dev,
  1328. dev_priv->sdvo_lvds_vbt_mode);
  1329. if (newmode != NULL) {
  1330. /* Guarantee the mode is preferred */
  1331. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1332. DRM_MODE_TYPE_DRIVER);
  1333. drm_mode_probed_add(connector, newmode);
  1334. }
  1335. }
  1336. end:
  1337. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1338. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1339. intel_sdvo->sdvo_lvds_fixed_mode =
  1340. drm_mode_duplicate(connector->dev, newmode);
  1341. drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
  1342. 0);
  1343. intel_sdvo->is_lvds = true;
  1344. break;
  1345. }
  1346. }
  1347. }
  1348. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1349. {
  1350. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1351. if (IS_TV(intel_sdvo_connector))
  1352. intel_sdvo_get_tv_modes(connector);
  1353. else if (IS_LVDS(intel_sdvo_connector))
  1354. intel_sdvo_get_lvds_modes(connector);
  1355. else
  1356. intel_sdvo_get_ddc_modes(connector);
  1357. return !list_empty(&connector->probed_modes);
  1358. }
  1359. static void
  1360. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1361. {
  1362. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1363. struct drm_device *dev = connector->dev;
  1364. if (intel_sdvo_connector->left)
  1365. drm_property_destroy(dev, intel_sdvo_connector->left);
  1366. if (intel_sdvo_connector->right)
  1367. drm_property_destroy(dev, intel_sdvo_connector->right);
  1368. if (intel_sdvo_connector->top)
  1369. drm_property_destroy(dev, intel_sdvo_connector->top);
  1370. if (intel_sdvo_connector->bottom)
  1371. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1372. if (intel_sdvo_connector->hpos)
  1373. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1374. if (intel_sdvo_connector->vpos)
  1375. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1376. if (intel_sdvo_connector->saturation)
  1377. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1378. if (intel_sdvo_connector->contrast)
  1379. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1380. if (intel_sdvo_connector->hue)
  1381. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1382. if (intel_sdvo_connector->sharpness)
  1383. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1384. if (intel_sdvo_connector->flicker_filter)
  1385. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1386. if (intel_sdvo_connector->flicker_filter_2d)
  1387. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1388. if (intel_sdvo_connector->flicker_filter_adaptive)
  1389. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1390. if (intel_sdvo_connector->tv_luma_filter)
  1391. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1392. if (intel_sdvo_connector->tv_chroma_filter)
  1393. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1394. if (intel_sdvo_connector->dot_crawl)
  1395. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1396. if (intel_sdvo_connector->brightness)
  1397. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1398. }
  1399. static void intel_sdvo_destroy(struct drm_connector *connector)
  1400. {
  1401. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1402. if (intel_sdvo_connector->tv_format)
  1403. drm_property_destroy(connector->dev,
  1404. intel_sdvo_connector->tv_format);
  1405. intel_sdvo_destroy_enhance_property(connector);
  1406. drm_sysfs_connector_remove(connector);
  1407. drm_connector_cleanup(connector);
  1408. kfree(connector);
  1409. }
  1410. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1411. {
  1412. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1413. struct edid *edid;
  1414. bool has_audio = false;
  1415. if (!intel_sdvo->is_hdmi)
  1416. return false;
  1417. edid = intel_sdvo_get_edid(connector);
  1418. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1419. has_audio = drm_detect_monitor_audio(edid);
  1420. return has_audio;
  1421. }
  1422. static int
  1423. intel_sdvo_set_property(struct drm_connector *connector,
  1424. struct drm_property *property,
  1425. uint64_t val)
  1426. {
  1427. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1428. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1429. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1430. uint16_t temp_value;
  1431. uint8_t cmd;
  1432. int ret;
  1433. ret = drm_connector_property_set_value(connector, property, val);
  1434. if (ret)
  1435. return ret;
  1436. if (property == dev_priv->force_audio_property) {
  1437. int i = val;
  1438. bool has_audio;
  1439. if (i == intel_sdvo_connector->force_audio)
  1440. return 0;
  1441. intel_sdvo_connector->force_audio = i;
  1442. if (i == 0)
  1443. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1444. else
  1445. has_audio = i > 0;
  1446. if (has_audio == intel_sdvo->has_hdmi_audio)
  1447. return 0;
  1448. intel_sdvo->has_hdmi_audio = has_audio;
  1449. goto done;
  1450. }
  1451. if (property == dev_priv->broadcast_rgb_property) {
  1452. if (val == !!intel_sdvo->color_range)
  1453. return 0;
  1454. intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1455. goto done;
  1456. }
  1457. #define CHECK_PROPERTY(name, NAME) \
  1458. if (intel_sdvo_connector->name == property) { \
  1459. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1460. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1461. cmd = SDVO_CMD_SET_##NAME; \
  1462. intel_sdvo_connector->cur_##name = temp_value; \
  1463. goto set_value; \
  1464. }
  1465. if (property == intel_sdvo_connector->tv_format) {
  1466. if (val >= TV_FORMAT_NUM)
  1467. return -EINVAL;
  1468. if (intel_sdvo->tv_format_index ==
  1469. intel_sdvo_connector->tv_format_supported[val])
  1470. return 0;
  1471. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1472. goto done;
  1473. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1474. temp_value = val;
  1475. if (intel_sdvo_connector->left == property) {
  1476. drm_connector_property_set_value(connector,
  1477. intel_sdvo_connector->right, val);
  1478. if (intel_sdvo_connector->left_margin == temp_value)
  1479. return 0;
  1480. intel_sdvo_connector->left_margin = temp_value;
  1481. intel_sdvo_connector->right_margin = temp_value;
  1482. temp_value = intel_sdvo_connector->max_hscan -
  1483. intel_sdvo_connector->left_margin;
  1484. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1485. goto set_value;
  1486. } else if (intel_sdvo_connector->right == property) {
  1487. drm_connector_property_set_value(connector,
  1488. intel_sdvo_connector->left, val);
  1489. if (intel_sdvo_connector->right_margin == temp_value)
  1490. return 0;
  1491. intel_sdvo_connector->left_margin = temp_value;
  1492. intel_sdvo_connector->right_margin = temp_value;
  1493. temp_value = intel_sdvo_connector->max_hscan -
  1494. intel_sdvo_connector->left_margin;
  1495. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1496. goto set_value;
  1497. } else if (intel_sdvo_connector->top == property) {
  1498. drm_connector_property_set_value(connector,
  1499. intel_sdvo_connector->bottom, val);
  1500. if (intel_sdvo_connector->top_margin == temp_value)
  1501. return 0;
  1502. intel_sdvo_connector->top_margin = temp_value;
  1503. intel_sdvo_connector->bottom_margin = temp_value;
  1504. temp_value = intel_sdvo_connector->max_vscan -
  1505. intel_sdvo_connector->top_margin;
  1506. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1507. goto set_value;
  1508. } else if (intel_sdvo_connector->bottom == property) {
  1509. drm_connector_property_set_value(connector,
  1510. intel_sdvo_connector->top, val);
  1511. if (intel_sdvo_connector->bottom_margin == temp_value)
  1512. return 0;
  1513. intel_sdvo_connector->top_margin = temp_value;
  1514. intel_sdvo_connector->bottom_margin = temp_value;
  1515. temp_value = intel_sdvo_connector->max_vscan -
  1516. intel_sdvo_connector->top_margin;
  1517. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1518. goto set_value;
  1519. }
  1520. CHECK_PROPERTY(hpos, HPOS)
  1521. CHECK_PROPERTY(vpos, VPOS)
  1522. CHECK_PROPERTY(saturation, SATURATION)
  1523. CHECK_PROPERTY(contrast, CONTRAST)
  1524. CHECK_PROPERTY(hue, HUE)
  1525. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1526. CHECK_PROPERTY(sharpness, SHARPNESS)
  1527. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1528. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1529. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1530. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1531. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1532. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1533. }
  1534. return -EINVAL; /* unknown property */
  1535. set_value:
  1536. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1537. return -EIO;
  1538. done:
  1539. if (intel_sdvo->base.base.crtc) {
  1540. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  1541. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1542. crtc->y, crtc->fb);
  1543. }
  1544. return 0;
  1545. #undef CHECK_PROPERTY
  1546. }
  1547. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1548. .dpms = intel_sdvo_dpms,
  1549. .mode_fixup = intel_sdvo_mode_fixup,
  1550. .prepare = intel_encoder_prepare,
  1551. .mode_set = intel_sdvo_mode_set,
  1552. .commit = intel_encoder_commit,
  1553. };
  1554. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1555. .dpms = drm_helper_connector_dpms,
  1556. .detect = intel_sdvo_detect,
  1557. .fill_modes = drm_helper_probe_single_connector_modes,
  1558. .set_property = intel_sdvo_set_property,
  1559. .destroy = intel_sdvo_destroy,
  1560. };
  1561. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1562. .get_modes = intel_sdvo_get_modes,
  1563. .mode_valid = intel_sdvo_mode_valid,
  1564. .best_encoder = intel_best_encoder,
  1565. };
  1566. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1567. {
  1568. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1569. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1570. drm_mode_destroy(encoder->dev,
  1571. intel_sdvo->sdvo_lvds_fixed_mode);
  1572. i2c_del_adapter(&intel_sdvo->ddc);
  1573. intel_encoder_destroy(encoder);
  1574. }
  1575. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1576. .destroy = intel_sdvo_enc_destroy,
  1577. };
  1578. static void
  1579. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1580. {
  1581. uint16_t mask = 0;
  1582. unsigned int num_bits;
  1583. /* Make a mask of outputs less than or equal to our own priority in the
  1584. * list.
  1585. */
  1586. switch (sdvo->controlled_output) {
  1587. case SDVO_OUTPUT_LVDS1:
  1588. mask |= SDVO_OUTPUT_LVDS1;
  1589. case SDVO_OUTPUT_LVDS0:
  1590. mask |= SDVO_OUTPUT_LVDS0;
  1591. case SDVO_OUTPUT_TMDS1:
  1592. mask |= SDVO_OUTPUT_TMDS1;
  1593. case SDVO_OUTPUT_TMDS0:
  1594. mask |= SDVO_OUTPUT_TMDS0;
  1595. case SDVO_OUTPUT_RGB1:
  1596. mask |= SDVO_OUTPUT_RGB1;
  1597. case SDVO_OUTPUT_RGB0:
  1598. mask |= SDVO_OUTPUT_RGB0;
  1599. break;
  1600. }
  1601. /* Count bits to find what number we are in the priority list. */
  1602. mask &= sdvo->caps.output_flags;
  1603. num_bits = hweight16(mask);
  1604. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1605. if (num_bits > 3)
  1606. num_bits = 3;
  1607. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1608. sdvo->ddc_bus = 1 << num_bits;
  1609. }
  1610. /**
  1611. * Choose the appropriate DDC bus for control bus switch command for this
  1612. * SDVO output based on the controlled output.
  1613. *
  1614. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1615. * outputs, then LVDS outputs.
  1616. */
  1617. static void
  1618. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1619. struct intel_sdvo *sdvo, u32 reg)
  1620. {
  1621. struct sdvo_device_mapping *mapping;
  1622. if (IS_SDVOB(reg))
  1623. mapping = &(dev_priv->sdvo_mappings[0]);
  1624. else
  1625. mapping = &(dev_priv->sdvo_mappings[1]);
  1626. if (mapping->initialized)
  1627. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1628. else
  1629. intel_sdvo_guess_ddc_bus(sdvo);
  1630. }
  1631. static void
  1632. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1633. struct intel_sdvo *sdvo, u32 reg)
  1634. {
  1635. struct sdvo_device_mapping *mapping;
  1636. u8 pin;
  1637. if (IS_SDVOB(reg))
  1638. mapping = &dev_priv->sdvo_mappings[0];
  1639. else
  1640. mapping = &dev_priv->sdvo_mappings[1];
  1641. pin = GMBUS_PORT_DPB;
  1642. if (mapping->initialized)
  1643. pin = mapping->i2c_pin;
  1644. if (pin < GMBUS_NUM_PORTS) {
  1645. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1646. intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
  1647. intel_gmbus_force_bit(sdvo->i2c, true);
  1648. } else {
  1649. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1650. }
  1651. }
  1652. static bool
  1653. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1654. {
  1655. return intel_sdvo_check_supp_encode(intel_sdvo);
  1656. }
  1657. static u8
  1658. intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1659. {
  1660. struct drm_i915_private *dev_priv = dev->dev_private;
  1661. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1662. if (IS_SDVOB(sdvo_reg)) {
  1663. my_mapping = &dev_priv->sdvo_mappings[0];
  1664. other_mapping = &dev_priv->sdvo_mappings[1];
  1665. } else {
  1666. my_mapping = &dev_priv->sdvo_mappings[1];
  1667. other_mapping = &dev_priv->sdvo_mappings[0];
  1668. }
  1669. /* If the BIOS described our SDVO device, take advantage of it. */
  1670. if (my_mapping->slave_addr)
  1671. return my_mapping->slave_addr;
  1672. /* If the BIOS only described a different SDVO device, use the
  1673. * address that it isn't using.
  1674. */
  1675. if (other_mapping->slave_addr) {
  1676. if (other_mapping->slave_addr == 0x70)
  1677. return 0x72;
  1678. else
  1679. return 0x70;
  1680. }
  1681. /* No SDVO device info is found for another DVO port,
  1682. * so use mapping assumption we had before BIOS parsing.
  1683. */
  1684. if (IS_SDVOB(sdvo_reg))
  1685. return 0x70;
  1686. else
  1687. return 0x72;
  1688. }
  1689. static void
  1690. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1691. struct intel_sdvo *encoder)
  1692. {
  1693. drm_connector_init(encoder->base.base.dev,
  1694. &connector->base.base,
  1695. &intel_sdvo_connector_funcs,
  1696. connector->base.base.connector_type);
  1697. drm_connector_helper_add(&connector->base.base,
  1698. &intel_sdvo_connector_helper_funcs);
  1699. connector->base.base.interlace_allowed = 0;
  1700. connector->base.base.doublescan_allowed = 0;
  1701. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1702. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1703. drm_sysfs_connector_add(&connector->base.base);
  1704. }
  1705. static void
  1706. intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
  1707. {
  1708. struct drm_device *dev = connector->base.base.dev;
  1709. intel_attach_force_audio_property(&connector->base.base);
  1710. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
  1711. intel_attach_broadcast_rgb_property(&connector->base.base);
  1712. }
  1713. static bool
  1714. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1715. {
  1716. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1717. struct drm_connector *connector;
  1718. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1719. struct intel_connector *intel_connector;
  1720. struct intel_sdvo_connector *intel_sdvo_connector;
  1721. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1722. if (!intel_sdvo_connector)
  1723. return false;
  1724. if (device == 0) {
  1725. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1726. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1727. } else if (device == 1) {
  1728. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1729. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1730. }
  1731. intel_connector = &intel_sdvo_connector->base;
  1732. connector = &intel_connector->base;
  1733. if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
  1734. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1735. intel_sdvo->hotplug_active[0] |= 1 << device;
  1736. /* Some SDVO devices have one-shot hotplug interrupts.
  1737. * Ensure that they get re-enabled when an interrupt happens.
  1738. */
  1739. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1740. intel_sdvo_enable_hotplug(intel_encoder);
  1741. }
  1742. else
  1743. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1744. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1745. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1746. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1747. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1748. intel_sdvo->is_hdmi = true;
  1749. }
  1750. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1751. (1 << INTEL_ANALOG_CLONE_BIT));
  1752. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1753. if (intel_sdvo->is_hdmi)
  1754. intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
  1755. return true;
  1756. }
  1757. static bool
  1758. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1759. {
  1760. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1761. struct drm_connector *connector;
  1762. struct intel_connector *intel_connector;
  1763. struct intel_sdvo_connector *intel_sdvo_connector;
  1764. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1765. if (!intel_sdvo_connector)
  1766. return false;
  1767. intel_connector = &intel_sdvo_connector->base;
  1768. connector = &intel_connector->base;
  1769. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1770. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1771. intel_sdvo->controlled_output |= type;
  1772. intel_sdvo_connector->output_flag = type;
  1773. intel_sdvo->is_tv = true;
  1774. intel_sdvo->base.needs_tv_clock = true;
  1775. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1776. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1777. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1778. goto err;
  1779. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1780. goto err;
  1781. return true;
  1782. err:
  1783. intel_sdvo_destroy(connector);
  1784. return false;
  1785. }
  1786. static bool
  1787. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1788. {
  1789. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1790. struct drm_connector *connector;
  1791. struct intel_connector *intel_connector;
  1792. struct intel_sdvo_connector *intel_sdvo_connector;
  1793. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1794. if (!intel_sdvo_connector)
  1795. return false;
  1796. intel_connector = &intel_sdvo_connector->base;
  1797. connector = &intel_connector->base;
  1798. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1799. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1800. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1801. if (device == 0) {
  1802. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1803. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1804. } else if (device == 1) {
  1805. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1806. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1807. }
  1808. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1809. (1 << INTEL_ANALOG_CLONE_BIT));
  1810. intel_sdvo_connector_init(intel_sdvo_connector,
  1811. intel_sdvo);
  1812. return true;
  1813. }
  1814. static bool
  1815. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1816. {
  1817. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1818. struct drm_connector *connector;
  1819. struct intel_connector *intel_connector;
  1820. struct intel_sdvo_connector *intel_sdvo_connector;
  1821. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1822. if (!intel_sdvo_connector)
  1823. return false;
  1824. intel_connector = &intel_sdvo_connector->base;
  1825. connector = &intel_connector->base;
  1826. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1827. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1828. if (device == 0) {
  1829. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1830. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1831. } else if (device == 1) {
  1832. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1833. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1834. }
  1835. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1836. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1837. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1838. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1839. goto err;
  1840. return true;
  1841. err:
  1842. intel_sdvo_destroy(connector);
  1843. return false;
  1844. }
  1845. static bool
  1846. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1847. {
  1848. intel_sdvo->is_tv = false;
  1849. intel_sdvo->base.needs_tv_clock = false;
  1850. intel_sdvo->is_lvds = false;
  1851. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1852. if (flags & SDVO_OUTPUT_TMDS0)
  1853. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1854. return false;
  1855. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1856. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1857. return false;
  1858. /* TV has no XXX1 function block */
  1859. if (flags & SDVO_OUTPUT_SVID0)
  1860. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1861. return false;
  1862. if (flags & SDVO_OUTPUT_CVBS0)
  1863. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1864. return false;
  1865. if (flags & SDVO_OUTPUT_RGB0)
  1866. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1867. return false;
  1868. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1869. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1870. return false;
  1871. if (flags & SDVO_OUTPUT_LVDS0)
  1872. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1873. return false;
  1874. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1875. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1876. return false;
  1877. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1878. unsigned char bytes[2];
  1879. intel_sdvo->controlled_output = 0;
  1880. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1881. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1882. SDVO_NAME(intel_sdvo),
  1883. bytes[0], bytes[1]);
  1884. return false;
  1885. }
  1886. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1887. return true;
  1888. }
  1889. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1890. struct intel_sdvo_connector *intel_sdvo_connector,
  1891. int type)
  1892. {
  1893. struct drm_device *dev = intel_sdvo->base.base.dev;
  1894. struct intel_sdvo_tv_format format;
  1895. uint32_t format_map, i;
  1896. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1897. return false;
  1898. BUILD_BUG_ON(sizeof(format) != 6);
  1899. if (!intel_sdvo_get_value(intel_sdvo,
  1900. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1901. &format, sizeof(format)))
  1902. return false;
  1903. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1904. if (format_map == 0)
  1905. return false;
  1906. intel_sdvo_connector->format_supported_num = 0;
  1907. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1908. if (format_map & (1 << i))
  1909. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1910. intel_sdvo_connector->tv_format =
  1911. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1912. "mode", intel_sdvo_connector->format_supported_num);
  1913. if (!intel_sdvo_connector->tv_format)
  1914. return false;
  1915. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1916. drm_property_add_enum(
  1917. intel_sdvo_connector->tv_format, i,
  1918. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1919. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1920. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1921. intel_sdvo_connector->tv_format, 0);
  1922. return true;
  1923. }
  1924. #define ENHANCEMENT(name, NAME) do { \
  1925. if (enhancements.name) { \
  1926. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1927. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1928. return false; \
  1929. intel_sdvo_connector->max_##name = data_value[0]; \
  1930. intel_sdvo_connector->cur_##name = response; \
  1931. intel_sdvo_connector->name = \
  1932. drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
  1933. if (!intel_sdvo_connector->name) return false; \
  1934. intel_sdvo_connector->name->values[0] = 0; \
  1935. intel_sdvo_connector->name->values[1] = data_value[0]; \
  1936. drm_connector_attach_property(connector, \
  1937. intel_sdvo_connector->name, \
  1938. intel_sdvo_connector->cur_##name); \
  1939. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1940. data_value[0], data_value[1], response); \
  1941. } \
  1942. } while (0)
  1943. static bool
  1944. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1945. struct intel_sdvo_connector *intel_sdvo_connector,
  1946. struct intel_sdvo_enhancements_reply enhancements)
  1947. {
  1948. struct drm_device *dev = intel_sdvo->base.base.dev;
  1949. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  1950. uint16_t response, data_value[2];
  1951. /* when horizontal overscan is supported, Add the left/right property */
  1952. if (enhancements.overscan_h) {
  1953. if (!intel_sdvo_get_value(intel_sdvo,
  1954. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1955. &data_value, 4))
  1956. return false;
  1957. if (!intel_sdvo_get_value(intel_sdvo,
  1958. SDVO_CMD_GET_OVERSCAN_H,
  1959. &response, 2))
  1960. return false;
  1961. intel_sdvo_connector->max_hscan = data_value[0];
  1962. intel_sdvo_connector->left_margin = data_value[0] - response;
  1963. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  1964. intel_sdvo_connector->left =
  1965. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  1966. "left_margin", 2);
  1967. if (!intel_sdvo_connector->left)
  1968. return false;
  1969. intel_sdvo_connector->left->values[0] = 0;
  1970. intel_sdvo_connector->left->values[1] = data_value[0];
  1971. drm_connector_attach_property(connector,
  1972. intel_sdvo_connector->left,
  1973. intel_sdvo_connector->left_margin);
  1974. intel_sdvo_connector->right =
  1975. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  1976. "right_margin", 2);
  1977. if (!intel_sdvo_connector->right)
  1978. return false;
  1979. intel_sdvo_connector->right->values[0] = 0;
  1980. intel_sdvo_connector->right->values[1] = data_value[0];
  1981. drm_connector_attach_property(connector,
  1982. intel_sdvo_connector->right,
  1983. intel_sdvo_connector->right_margin);
  1984. DRM_DEBUG_KMS("h_overscan: max %d, "
  1985. "default %d, current %d\n",
  1986. data_value[0], data_value[1], response);
  1987. }
  1988. if (enhancements.overscan_v) {
  1989. if (!intel_sdvo_get_value(intel_sdvo,
  1990. SDVO_CMD_GET_MAX_OVERSCAN_V,
  1991. &data_value, 4))
  1992. return false;
  1993. if (!intel_sdvo_get_value(intel_sdvo,
  1994. SDVO_CMD_GET_OVERSCAN_V,
  1995. &response, 2))
  1996. return false;
  1997. intel_sdvo_connector->max_vscan = data_value[0];
  1998. intel_sdvo_connector->top_margin = data_value[0] - response;
  1999. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2000. intel_sdvo_connector->top =
  2001. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2002. "top_margin", 2);
  2003. if (!intel_sdvo_connector->top)
  2004. return false;
  2005. intel_sdvo_connector->top->values[0] = 0;
  2006. intel_sdvo_connector->top->values[1] = data_value[0];
  2007. drm_connector_attach_property(connector,
  2008. intel_sdvo_connector->top,
  2009. intel_sdvo_connector->top_margin);
  2010. intel_sdvo_connector->bottom =
  2011. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2012. "bottom_margin", 2);
  2013. if (!intel_sdvo_connector->bottom)
  2014. return false;
  2015. intel_sdvo_connector->bottom->values[0] = 0;
  2016. intel_sdvo_connector->bottom->values[1] = data_value[0];
  2017. drm_connector_attach_property(connector,
  2018. intel_sdvo_connector->bottom,
  2019. intel_sdvo_connector->bottom_margin);
  2020. DRM_DEBUG_KMS("v_overscan: max %d, "
  2021. "default %d, current %d\n",
  2022. data_value[0], data_value[1], response);
  2023. }
  2024. ENHANCEMENT(hpos, HPOS);
  2025. ENHANCEMENT(vpos, VPOS);
  2026. ENHANCEMENT(saturation, SATURATION);
  2027. ENHANCEMENT(contrast, CONTRAST);
  2028. ENHANCEMENT(hue, HUE);
  2029. ENHANCEMENT(sharpness, SHARPNESS);
  2030. ENHANCEMENT(brightness, BRIGHTNESS);
  2031. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2032. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2033. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2034. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2035. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2036. if (enhancements.dot_crawl) {
  2037. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2038. return false;
  2039. intel_sdvo_connector->max_dot_crawl = 1;
  2040. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2041. intel_sdvo_connector->dot_crawl =
  2042. drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
  2043. if (!intel_sdvo_connector->dot_crawl)
  2044. return false;
  2045. intel_sdvo_connector->dot_crawl->values[0] = 0;
  2046. intel_sdvo_connector->dot_crawl->values[1] = 1;
  2047. drm_connector_attach_property(connector,
  2048. intel_sdvo_connector->dot_crawl,
  2049. intel_sdvo_connector->cur_dot_crawl);
  2050. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2051. }
  2052. return true;
  2053. }
  2054. static bool
  2055. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2056. struct intel_sdvo_connector *intel_sdvo_connector,
  2057. struct intel_sdvo_enhancements_reply enhancements)
  2058. {
  2059. struct drm_device *dev = intel_sdvo->base.base.dev;
  2060. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2061. uint16_t response, data_value[2];
  2062. ENHANCEMENT(brightness, BRIGHTNESS);
  2063. return true;
  2064. }
  2065. #undef ENHANCEMENT
  2066. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2067. struct intel_sdvo_connector *intel_sdvo_connector)
  2068. {
  2069. union {
  2070. struct intel_sdvo_enhancements_reply reply;
  2071. uint16_t response;
  2072. } enhancements;
  2073. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2074. enhancements.response = 0;
  2075. intel_sdvo_get_value(intel_sdvo,
  2076. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2077. &enhancements, sizeof(enhancements));
  2078. if (enhancements.response == 0) {
  2079. DRM_DEBUG_KMS("No enhancement is supported\n");
  2080. return true;
  2081. }
  2082. if (IS_TV(intel_sdvo_connector))
  2083. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2084. else if (IS_LVDS(intel_sdvo_connector))
  2085. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2086. else
  2087. return true;
  2088. }
  2089. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2090. struct i2c_msg *msgs,
  2091. int num)
  2092. {
  2093. struct intel_sdvo *sdvo = adapter->algo_data;
  2094. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2095. return -EIO;
  2096. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2097. }
  2098. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2099. {
  2100. struct intel_sdvo *sdvo = adapter->algo_data;
  2101. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2102. }
  2103. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2104. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2105. .functionality = intel_sdvo_ddc_proxy_func
  2106. };
  2107. static bool
  2108. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2109. struct drm_device *dev)
  2110. {
  2111. sdvo->ddc.owner = THIS_MODULE;
  2112. sdvo->ddc.class = I2C_CLASS_DDC;
  2113. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2114. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2115. sdvo->ddc.algo_data = sdvo;
  2116. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2117. return i2c_add_adapter(&sdvo->ddc) == 0;
  2118. }
  2119. bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2120. {
  2121. struct drm_i915_private *dev_priv = dev->dev_private;
  2122. struct intel_encoder *intel_encoder;
  2123. struct intel_sdvo *intel_sdvo;
  2124. int i;
  2125. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2126. if (!intel_sdvo)
  2127. return false;
  2128. intel_sdvo->sdvo_reg = sdvo_reg;
  2129. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2130. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2131. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
  2132. kfree(intel_sdvo);
  2133. return false;
  2134. }
  2135. /* encoder type will be decided later */
  2136. intel_encoder = &intel_sdvo->base;
  2137. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2138. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2139. /* Read the regs to test if we can talk to the device */
  2140. for (i = 0; i < 0x40; i++) {
  2141. u8 byte;
  2142. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2143. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2144. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2145. goto err;
  2146. }
  2147. }
  2148. if (IS_SDVOB(sdvo_reg))
  2149. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2150. else
  2151. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2152. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2153. /* In default case sdvo lvds is false */
  2154. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2155. goto err;
  2156. /* Set up hotplug command - note paranoia about contents of reply.
  2157. * We assume that the hardware is in a sane state, and only touch
  2158. * the bits we think we understand.
  2159. */
  2160. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
  2161. &intel_sdvo->hotplug_active, 2);
  2162. intel_sdvo->hotplug_active[0] &= ~0x3;
  2163. if (intel_sdvo_output_setup(intel_sdvo,
  2164. intel_sdvo->caps.output_flags) != true) {
  2165. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2166. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2167. goto err;
  2168. }
  2169. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2170. /* Set the input timing to the screen. Assume always input 0. */
  2171. if (!intel_sdvo_set_target_input(intel_sdvo))
  2172. goto err;
  2173. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2174. &intel_sdvo->pixel_clock_min,
  2175. &intel_sdvo->pixel_clock_max))
  2176. goto err;
  2177. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2178. "clock range %dMHz - %dMHz, "
  2179. "input 1: %c, input 2: %c, "
  2180. "output 1: %c, output 2: %c\n",
  2181. SDVO_NAME(intel_sdvo),
  2182. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2183. intel_sdvo->caps.device_rev_id,
  2184. intel_sdvo->pixel_clock_min / 1000,
  2185. intel_sdvo->pixel_clock_max / 1000,
  2186. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2187. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2188. /* check currently supported outputs */
  2189. intel_sdvo->caps.output_flags &
  2190. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2191. intel_sdvo->caps.output_flags &
  2192. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2193. return true;
  2194. err:
  2195. drm_encoder_cleanup(&intel_encoder->base);
  2196. i2c_del_adapter(&intel_sdvo->ddc);
  2197. kfree(intel_sdvo);
  2198. return false;
  2199. }