i915_debugfs.c 46 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "intel_drv.h"
  35. #include "intel_ringbuffer.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #define DRM_I915_RING_DEBUG 1
  39. #if defined(CONFIG_DEBUG_FS)
  40. enum {
  41. ACTIVE_LIST,
  42. FLUSHING_LIST,
  43. INACTIVE_LIST,
  44. PINNED_LIST,
  45. DEFERRED_FREE_LIST,
  46. };
  47. static const char *yesno(int v)
  48. {
  49. return v ? "yes" : "no";
  50. }
  51. static int i915_capabilities(struct seq_file *m, void *data)
  52. {
  53. struct drm_info_node *node = (struct drm_info_node *) m->private;
  54. struct drm_device *dev = node->minor->dev;
  55. const struct intel_device_info *info = INTEL_INFO(dev);
  56. seq_printf(m, "gen: %d\n", info->gen);
  57. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  58. B(is_mobile);
  59. B(is_i85x);
  60. B(is_i915g);
  61. B(is_i945gm);
  62. B(is_g33);
  63. B(need_gfx_hws);
  64. B(is_g4x);
  65. B(is_pineview);
  66. B(is_broadwater);
  67. B(is_crestline);
  68. B(has_fbc);
  69. B(has_pipe_cxsr);
  70. B(has_hotplug);
  71. B(cursor_needs_physical);
  72. B(has_overlay);
  73. B(overlay_needs_physical);
  74. B(supports_tv);
  75. B(has_bsd_ring);
  76. B(has_blt_ring);
  77. #undef B
  78. return 0;
  79. }
  80. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  81. {
  82. if (obj->user_pin_count > 0)
  83. return "P";
  84. else if (obj->pin_count > 0)
  85. return "p";
  86. else
  87. return " ";
  88. }
  89. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  90. {
  91. switch (obj->tiling_mode) {
  92. default:
  93. case I915_TILING_NONE: return " ";
  94. case I915_TILING_X: return "X";
  95. case I915_TILING_Y: return "Y";
  96. }
  97. }
  98. static const char *cache_level_str(int type)
  99. {
  100. switch (type) {
  101. case I915_CACHE_NONE: return " uncached";
  102. case I915_CACHE_LLC: return " snooped (LLC)";
  103. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  104. default: return "";
  105. }
  106. }
  107. static void
  108. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  109. {
  110. seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
  111. &obj->base,
  112. get_pin_flag(obj),
  113. get_tiling_flag(obj),
  114. obj->base.size,
  115. obj->base.read_domains,
  116. obj->base.write_domain,
  117. obj->last_rendering_seqno,
  118. obj->last_fenced_seqno,
  119. cache_level_str(obj->cache_level),
  120. obj->dirty ? " dirty" : "",
  121. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  122. if (obj->base.name)
  123. seq_printf(m, " (name: %d)", obj->base.name);
  124. if (obj->fence_reg != I915_FENCE_REG_NONE)
  125. seq_printf(m, " (fence: %d)", obj->fence_reg);
  126. if (obj->gtt_space != NULL)
  127. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  128. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  129. if (obj->pin_mappable || obj->fault_mappable) {
  130. char s[3], *t = s;
  131. if (obj->pin_mappable)
  132. *t++ = 'p';
  133. if (obj->fault_mappable)
  134. *t++ = 'f';
  135. *t = '\0';
  136. seq_printf(m, " (%s mappable)", s);
  137. }
  138. if (obj->ring != NULL)
  139. seq_printf(m, " (%s)", obj->ring->name);
  140. }
  141. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  142. {
  143. struct drm_info_node *node = (struct drm_info_node *) m->private;
  144. uintptr_t list = (uintptr_t) node->info_ent->data;
  145. struct list_head *head;
  146. struct drm_device *dev = node->minor->dev;
  147. drm_i915_private_t *dev_priv = dev->dev_private;
  148. struct drm_i915_gem_object *obj;
  149. size_t total_obj_size, total_gtt_size;
  150. int count, ret;
  151. ret = mutex_lock_interruptible(&dev->struct_mutex);
  152. if (ret)
  153. return ret;
  154. switch (list) {
  155. case ACTIVE_LIST:
  156. seq_printf(m, "Active:\n");
  157. head = &dev_priv->mm.active_list;
  158. break;
  159. case INACTIVE_LIST:
  160. seq_printf(m, "Inactive:\n");
  161. head = &dev_priv->mm.inactive_list;
  162. break;
  163. case PINNED_LIST:
  164. seq_printf(m, "Pinned:\n");
  165. head = &dev_priv->mm.pinned_list;
  166. break;
  167. case FLUSHING_LIST:
  168. seq_printf(m, "Flushing:\n");
  169. head = &dev_priv->mm.flushing_list;
  170. break;
  171. case DEFERRED_FREE_LIST:
  172. seq_printf(m, "Deferred free:\n");
  173. head = &dev_priv->mm.deferred_free_list;
  174. break;
  175. default:
  176. mutex_unlock(&dev->struct_mutex);
  177. return -EINVAL;
  178. }
  179. total_obj_size = total_gtt_size = count = 0;
  180. list_for_each_entry(obj, head, mm_list) {
  181. seq_printf(m, " ");
  182. describe_obj(m, obj);
  183. seq_printf(m, "\n");
  184. total_obj_size += obj->base.size;
  185. total_gtt_size += obj->gtt_space->size;
  186. count++;
  187. }
  188. mutex_unlock(&dev->struct_mutex);
  189. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  190. count, total_obj_size, total_gtt_size);
  191. return 0;
  192. }
  193. #define count_objects(list, member) do { \
  194. list_for_each_entry(obj, list, member) { \
  195. size += obj->gtt_space->size; \
  196. ++count; \
  197. if (obj->map_and_fenceable) { \
  198. mappable_size += obj->gtt_space->size; \
  199. ++mappable_count; \
  200. } \
  201. } \
  202. } while (0)
  203. static int i915_gem_object_info(struct seq_file *m, void* data)
  204. {
  205. struct drm_info_node *node = (struct drm_info_node *) m->private;
  206. struct drm_device *dev = node->minor->dev;
  207. struct drm_i915_private *dev_priv = dev->dev_private;
  208. u32 count, mappable_count;
  209. size_t size, mappable_size;
  210. struct drm_i915_gem_object *obj;
  211. int ret;
  212. ret = mutex_lock_interruptible(&dev->struct_mutex);
  213. if (ret)
  214. return ret;
  215. seq_printf(m, "%u objects, %zu bytes\n",
  216. dev_priv->mm.object_count,
  217. dev_priv->mm.object_memory);
  218. size = count = mappable_size = mappable_count = 0;
  219. count_objects(&dev_priv->mm.gtt_list, gtt_list);
  220. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  221. count, mappable_count, size, mappable_size);
  222. size = count = mappable_size = mappable_count = 0;
  223. count_objects(&dev_priv->mm.active_list, mm_list);
  224. count_objects(&dev_priv->mm.flushing_list, mm_list);
  225. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  226. count, mappable_count, size, mappable_size);
  227. size = count = mappable_size = mappable_count = 0;
  228. count_objects(&dev_priv->mm.pinned_list, mm_list);
  229. seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
  230. count, mappable_count, size, mappable_size);
  231. size = count = mappable_size = mappable_count = 0;
  232. count_objects(&dev_priv->mm.inactive_list, mm_list);
  233. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  234. count, mappable_count, size, mappable_size);
  235. size = count = mappable_size = mappable_count = 0;
  236. count_objects(&dev_priv->mm.deferred_free_list, mm_list);
  237. seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
  238. count, mappable_count, size, mappable_size);
  239. size = count = mappable_size = mappable_count = 0;
  240. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  241. if (obj->fault_mappable) {
  242. size += obj->gtt_space->size;
  243. ++count;
  244. }
  245. if (obj->pin_mappable) {
  246. mappable_size += obj->gtt_space->size;
  247. ++mappable_count;
  248. }
  249. }
  250. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  251. mappable_count, mappable_size);
  252. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  253. count, size);
  254. seq_printf(m, "%zu [%zu] gtt total\n",
  255. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  256. mutex_unlock(&dev->struct_mutex);
  257. return 0;
  258. }
  259. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  260. {
  261. struct drm_info_node *node = (struct drm_info_node *) m->private;
  262. struct drm_device *dev = node->minor->dev;
  263. struct drm_i915_private *dev_priv = dev->dev_private;
  264. struct drm_i915_gem_object *obj;
  265. size_t total_obj_size, total_gtt_size;
  266. int count, ret;
  267. ret = mutex_lock_interruptible(&dev->struct_mutex);
  268. if (ret)
  269. return ret;
  270. total_obj_size = total_gtt_size = count = 0;
  271. list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
  272. seq_printf(m, " ");
  273. describe_obj(m, obj);
  274. seq_printf(m, "\n");
  275. total_obj_size += obj->base.size;
  276. total_gtt_size += obj->gtt_space->size;
  277. count++;
  278. }
  279. mutex_unlock(&dev->struct_mutex);
  280. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  281. count, total_obj_size, total_gtt_size);
  282. return 0;
  283. }
  284. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  285. {
  286. struct drm_info_node *node = (struct drm_info_node *) m->private;
  287. struct drm_device *dev = node->minor->dev;
  288. unsigned long flags;
  289. struct intel_crtc *crtc;
  290. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  291. const char pipe = pipe_name(crtc->pipe);
  292. const char plane = plane_name(crtc->plane);
  293. struct intel_unpin_work *work;
  294. spin_lock_irqsave(&dev->event_lock, flags);
  295. work = crtc->unpin_work;
  296. if (work == NULL) {
  297. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  298. pipe, plane);
  299. } else {
  300. if (!work->pending) {
  301. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  302. pipe, plane);
  303. } else {
  304. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  305. pipe, plane);
  306. }
  307. if (work->enable_stall_check)
  308. seq_printf(m, "Stall check enabled, ");
  309. else
  310. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  311. seq_printf(m, "%d prepares\n", work->pending);
  312. if (work->old_fb_obj) {
  313. struct drm_i915_gem_object *obj = work->old_fb_obj;
  314. if (obj)
  315. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  316. }
  317. if (work->pending_flip_obj) {
  318. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  319. if (obj)
  320. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  321. }
  322. }
  323. spin_unlock_irqrestore(&dev->event_lock, flags);
  324. }
  325. return 0;
  326. }
  327. static int i915_gem_request_info(struct seq_file *m, void *data)
  328. {
  329. struct drm_info_node *node = (struct drm_info_node *) m->private;
  330. struct drm_device *dev = node->minor->dev;
  331. drm_i915_private_t *dev_priv = dev->dev_private;
  332. struct drm_i915_gem_request *gem_request;
  333. int ret, count;
  334. ret = mutex_lock_interruptible(&dev->struct_mutex);
  335. if (ret)
  336. return ret;
  337. count = 0;
  338. if (!list_empty(&dev_priv->ring[RCS].request_list)) {
  339. seq_printf(m, "Render requests:\n");
  340. list_for_each_entry(gem_request,
  341. &dev_priv->ring[RCS].request_list,
  342. list) {
  343. seq_printf(m, " %d @ %d\n",
  344. gem_request->seqno,
  345. (int) (jiffies - gem_request->emitted_jiffies));
  346. }
  347. count++;
  348. }
  349. if (!list_empty(&dev_priv->ring[VCS].request_list)) {
  350. seq_printf(m, "BSD requests:\n");
  351. list_for_each_entry(gem_request,
  352. &dev_priv->ring[VCS].request_list,
  353. list) {
  354. seq_printf(m, " %d @ %d\n",
  355. gem_request->seqno,
  356. (int) (jiffies - gem_request->emitted_jiffies));
  357. }
  358. count++;
  359. }
  360. if (!list_empty(&dev_priv->ring[BCS].request_list)) {
  361. seq_printf(m, "BLT requests:\n");
  362. list_for_each_entry(gem_request,
  363. &dev_priv->ring[BCS].request_list,
  364. list) {
  365. seq_printf(m, " %d @ %d\n",
  366. gem_request->seqno,
  367. (int) (jiffies - gem_request->emitted_jiffies));
  368. }
  369. count++;
  370. }
  371. mutex_unlock(&dev->struct_mutex);
  372. if (count == 0)
  373. seq_printf(m, "No requests\n");
  374. return 0;
  375. }
  376. static void i915_ring_seqno_info(struct seq_file *m,
  377. struct intel_ring_buffer *ring)
  378. {
  379. if (ring->get_seqno) {
  380. seq_printf(m, "Current sequence (%s): %d\n",
  381. ring->name, ring->get_seqno(ring));
  382. seq_printf(m, "Waiter sequence (%s): %d\n",
  383. ring->name, ring->waiting_seqno);
  384. seq_printf(m, "IRQ sequence (%s): %d\n",
  385. ring->name, ring->irq_seqno);
  386. }
  387. }
  388. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  389. {
  390. struct drm_info_node *node = (struct drm_info_node *) m->private;
  391. struct drm_device *dev = node->minor->dev;
  392. drm_i915_private_t *dev_priv = dev->dev_private;
  393. int ret, i;
  394. ret = mutex_lock_interruptible(&dev->struct_mutex);
  395. if (ret)
  396. return ret;
  397. for (i = 0; i < I915_NUM_RINGS; i++)
  398. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  399. mutex_unlock(&dev->struct_mutex);
  400. return 0;
  401. }
  402. static int i915_interrupt_info(struct seq_file *m, void *data)
  403. {
  404. struct drm_info_node *node = (struct drm_info_node *) m->private;
  405. struct drm_device *dev = node->minor->dev;
  406. drm_i915_private_t *dev_priv = dev->dev_private;
  407. int ret, i, pipe;
  408. ret = mutex_lock_interruptible(&dev->struct_mutex);
  409. if (ret)
  410. return ret;
  411. if (!HAS_PCH_SPLIT(dev)) {
  412. seq_printf(m, "Interrupt enable: %08x\n",
  413. I915_READ(IER));
  414. seq_printf(m, "Interrupt identity: %08x\n",
  415. I915_READ(IIR));
  416. seq_printf(m, "Interrupt mask: %08x\n",
  417. I915_READ(IMR));
  418. for_each_pipe(pipe)
  419. seq_printf(m, "Pipe %c stat: %08x\n",
  420. pipe_name(pipe),
  421. I915_READ(PIPESTAT(pipe)));
  422. } else {
  423. seq_printf(m, "North Display Interrupt enable: %08x\n",
  424. I915_READ(DEIER));
  425. seq_printf(m, "North Display Interrupt identity: %08x\n",
  426. I915_READ(DEIIR));
  427. seq_printf(m, "North Display Interrupt mask: %08x\n",
  428. I915_READ(DEIMR));
  429. seq_printf(m, "South Display Interrupt enable: %08x\n",
  430. I915_READ(SDEIER));
  431. seq_printf(m, "South Display Interrupt identity: %08x\n",
  432. I915_READ(SDEIIR));
  433. seq_printf(m, "South Display Interrupt mask: %08x\n",
  434. I915_READ(SDEIMR));
  435. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  436. I915_READ(GTIER));
  437. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  438. I915_READ(GTIIR));
  439. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  440. I915_READ(GTIMR));
  441. }
  442. seq_printf(m, "Interrupts received: %d\n",
  443. atomic_read(&dev_priv->irq_received));
  444. for (i = 0; i < I915_NUM_RINGS; i++) {
  445. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  446. seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
  447. dev_priv->ring[i].name,
  448. I915_READ_IMR(&dev_priv->ring[i]));
  449. }
  450. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  451. }
  452. mutex_unlock(&dev->struct_mutex);
  453. return 0;
  454. }
  455. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  456. {
  457. struct drm_info_node *node = (struct drm_info_node *) m->private;
  458. struct drm_device *dev = node->minor->dev;
  459. drm_i915_private_t *dev_priv = dev->dev_private;
  460. int i, ret;
  461. ret = mutex_lock_interruptible(&dev->struct_mutex);
  462. if (ret)
  463. return ret;
  464. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  465. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  466. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  467. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  468. seq_printf(m, "Fenced object[%2d] = ", i);
  469. if (obj == NULL)
  470. seq_printf(m, "unused");
  471. else
  472. describe_obj(m, obj);
  473. seq_printf(m, "\n");
  474. }
  475. mutex_unlock(&dev->struct_mutex);
  476. return 0;
  477. }
  478. static int i915_hws_info(struct seq_file *m, void *data)
  479. {
  480. struct drm_info_node *node = (struct drm_info_node *) m->private;
  481. struct drm_device *dev = node->minor->dev;
  482. drm_i915_private_t *dev_priv = dev->dev_private;
  483. struct intel_ring_buffer *ring;
  484. const volatile u32 __iomem *hws;
  485. int i;
  486. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  487. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  488. if (hws == NULL)
  489. return 0;
  490. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  491. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  492. i * 4,
  493. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  494. }
  495. return 0;
  496. }
  497. static void i915_dump_object(struct seq_file *m,
  498. struct io_mapping *mapping,
  499. struct drm_i915_gem_object *obj)
  500. {
  501. int page, page_count, i;
  502. page_count = obj->base.size / PAGE_SIZE;
  503. for (page = 0; page < page_count; page++) {
  504. u32 *mem = io_mapping_map_wc(mapping,
  505. obj->gtt_offset + page * PAGE_SIZE);
  506. for (i = 0; i < PAGE_SIZE; i += 4)
  507. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  508. io_mapping_unmap(mem);
  509. }
  510. }
  511. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  512. {
  513. struct drm_info_node *node = (struct drm_info_node *) m->private;
  514. struct drm_device *dev = node->minor->dev;
  515. drm_i915_private_t *dev_priv = dev->dev_private;
  516. struct drm_i915_gem_object *obj;
  517. int ret;
  518. ret = mutex_lock_interruptible(&dev->struct_mutex);
  519. if (ret)
  520. return ret;
  521. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  522. if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
  523. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  524. i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
  525. }
  526. }
  527. mutex_unlock(&dev->struct_mutex);
  528. return 0;
  529. }
  530. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  531. {
  532. struct drm_info_node *node = (struct drm_info_node *) m->private;
  533. struct drm_device *dev = node->minor->dev;
  534. drm_i915_private_t *dev_priv = dev->dev_private;
  535. struct intel_ring_buffer *ring;
  536. int ret;
  537. ret = mutex_lock_interruptible(&dev->struct_mutex);
  538. if (ret)
  539. return ret;
  540. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  541. if (!ring->obj) {
  542. seq_printf(m, "No ringbuffer setup\n");
  543. } else {
  544. const u8 __iomem *virt = ring->virtual_start;
  545. uint32_t off;
  546. for (off = 0; off < ring->size; off += 4) {
  547. uint32_t *ptr = (uint32_t *)(virt + off);
  548. seq_printf(m, "%08x : %08x\n", off, *ptr);
  549. }
  550. }
  551. mutex_unlock(&dev->struct_mutex);
  552. return 0;
  553. }
  554. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  555. {
  556. struct drm_info_node *node = (struct drm_info_node *) m->private;
  557. struct drm_device *dev = node->minor->dev;
  558. drm_i915_private_t *dev_priv = dev->dev_private;
  559. struct intel_ring_buffer *ring;
  560. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  561. if (ring->size == 0)
  562. return 0;
  563. seq_printf(m, "Ring %s:\n", ring->name);
  564. seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
  565. seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
  566. seq_printf(m, " Size : %08x\n", ring->size);
  567. seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
  568. seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
  569. if (IS_GEN6(dev)) {
  570. seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
  571. seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
  572. }
  573. seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
  574. seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
  575. return 0;
  576. }
  577. static const char *ring_str(int ring)
  578. {
  579. switch (ring) {
  580. case RING_RENDER: return " render";
  581. case RING_BSD: return " bsd";
  582. case RING_BLT: return " blt";
  583. default: return "";
  584. }
  585. }
  586. static const char *pin_flag(int pinned)
  587. {
  588. if (pinned > 0)
  589. return " P";
  590. else if (pinned < 0)
  591. return " p";
  592. else
  593. return "";
  594. }
  595. static const char *tiling_flag(int tiling)
  596. {
  597. switch (tiling) {
  598. default:
  599. case I915_TILING_NONE: return "";
  600. case I915_TILING_X: return " X";
  601. case I915_TILING_Y: return " Y";
  602. }
  603. }
  604. static const char *dirty_flag(int dirty)
  605. {
  606. return dirty ? " dirty" : "";
  607. }
  608. static const char *purgeable_flag(int purgeable)
  609. {
  610. return purgeable ? " purgeable" : "";
  611. }
  612. static void print_error_buffers(struct seq_file *m,
  613. const char *name,
  614. struct drm_i915_error_buffer *err,
  615. int count)
  616. {
  617. seq_printf(m, "%s [%d]:\n", name, count);
  618. while (count--) {
  619. seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",
  620. err->gtt_offset,
  621. err->size,
  622. err->read_domains,
  623. err->write_domain,
  624. err->seqno,
  625. pin_flag(err->pinned),
  626. tiling_flag(err->tiling),
  627. dirty_flag(err->dirty),
  628. purgeable_flag(err->purgeable),
  629. ring_str(err->ring),
  630. cache_level_str(err->cache_level));
  631. if (err->name)
  632. seq_printf(m, " (name: %d)", err->name);
  633. if (err->fence_reg != I915_FENCE_REG_NONE)
  634. seq_printf(m, " (fence: %d)", err->fence_reg);
  635. seq_printf(m, "\n");
  636. err++;
  637. }
  638. }
  639. static int i915_error_state(struct seq_file *m, void *unused)
  640. {
  641. struct drm_info_node *node = (struct drm_info_node *) m->private;
  642. struct drm_device *dev = node->minor->dev;
  643. drm_i915_private_t *dev_priv = dev->dev_private;
  644. struct drm_i915_error_state *error;
  645. unsigned long flags;
  646. int i, page, offset, elt;
  647. spin_lock_irqsave(&dev_priv->error_lock, flags);
  648. if (!dev_priv->first_error) {
  649. seq_printf(m, "no error state collected\n");
  650. goto out;
  651. }
  652. error = dev_priv->first_error;
  653. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  654. error->time.tv_usec);
  655. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  656. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  657. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  658. if (INTEL_INFO(dev)->gen >= 6) {
  659. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  660. seq_printf(m, "Blitter command stream:\n");
  661. seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
  662. seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
  663. seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
  664. seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
  665. seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
  666. seq_printf(m, "Video (BSD) command stream:\n");
  667. seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
  668. seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
  669. seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
  670. seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
  671. seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
  672. }
  673. seq_printf(m, "Render command stream:\n");
  674. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  675. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  676. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  677. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  678. if (INTEL_INFO(dev)->gen >= 4) {
  679. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  680. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  681. }
  682. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  683. seq_printf(m, " seqno: 0x%08x\n", error->seqno);
  684. for (i = 0; i < dev_priv->num_fence_regs; i++)
  685. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  686. if (error->active_bo)
  687. print_error_buffers(m, "Active",
  688. error->active_bo,
  689. error->active_bo_count);
  690. if (error->pinned_bo)
  691. print_error_buffers(m, "Pinned",
  692. error->pinned_bo,
  693. error->pinned_bo_count);
  694. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  695. if (error->batchbuffer[i]) {
  696. struct drm_i915_error_object *obj = error->batchbuffer[i];
  697. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  698. dev_priv->ring[i].name,
  699. obj->gtt_offset);
  700. offset = 0;
  701. for (page = 0; page < obj->page_count; page++) {
  702. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  703. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  704. offset += 4;
  705. }
  706. }
  707. }
  708. }
  709. for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
  710. if (error->ringbuffer[i]) {
  711. struct drm_i915_error_object *obj = error->ringbuffer[i];
  712. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  713. dev_priv->ring[i].name,
  714. obj->gtt_offset);
  715. offset = 0;
  716. for (page = 0; page < obj->page_count; page++) {
  717. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  718. seq_printf(m, "%08x : %08x\n",
  719. offset,
  720. obj->pages[page][elt]);
  721. offset += 4;
  722. }
  723. }
  724. }
  725. }
  726. if (error->overlay)
  727. intel_overlay_print_error_state(m, error->overlay);
  728. if (error->display)
  729. intel_display_print_error_state(m, dev, error->display);
  730. out:
  731. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  732. return 0;
  733. }
  734. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  735. {
  736. struct drm_info_node *node = (struct drm_info_node *) m->private;
  737. struct drm_device *dev = node->minor->dev;
  738. drm_i915_private_t *dev_priv = dev->dev_private;
  739. u16 crstanddelay = I915_READ16(CRSTANDVID);
  740. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  741. return 0;
  742. }
  743. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  744. {
  745. struct drm_info_node *node = (struct drm_info_node *) m->private;
  746. struct drm_device *dev = node->minor->dev;
  747. drm_i915_private_t *dev_priv = dev->dev_private;
  748. int ret;
  749. if (IS_GEN5(dev)) {
  750. u16 rgvswctl = I915_READ16(MEMSWCTL);
  751. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  752. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  753. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  754. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  755. MEMSTAT_VID_SHIFT);
  756. seq_printf(m, "Current P-state: %d\n",
  757. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  758. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  759. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  760. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  761. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  762. u32 rpstat;
  763. u32 rpupei, rpcurup, rpprevup;
  764. u32 rpdownei, rpcurdown, rpprevdown;
  765. int max_freq;
  766. /* RPSTAT1 is in the GT power well */
  767. ret = mutex_lock_interruptible(&dev->struct_mutex);
  768. if (ret)
  769. return ret;
  770. gen6_gt_force_wake_get(dev_priv);
  771. rpstat = I915_READ(GEN6_RPSTAT1);
  772. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  773. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  774. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  775. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  776. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  777. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  778. gen6_gt_force_wake_put(dev_priv);
  779. mutex_unlock(&dev->struct_mutex);
  780. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  781. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  782. seq_printf(m, "Render p-state ratio: %d\n",
  783. (gt_perf_status & 0xff00) >> 8);
  784. seq_printf(m, "Render p-state VID: %d\n",
  785. gt_perf_status & 0xff);
  786. seq_printf(m, "Render p-state limit: %d\n",
  787. rp_state_limits & 0xff);
  788. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  789. GEN6_CAGF_SHIFT) * 50);
  790. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  791. GEN6_CURICONT_MASK);
  792. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  793. GEN6_CURBSYTAVG_MASK);
  794. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  795. GEN6_CURBSYTAVG_MASK);
  796. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  797. GEN6_CURIAVG_MASK);
  798. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  799. GEN6_CURBSYTAVG_MASK);
  800. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  801. GEN6_CURBSYTAVG_MASK);
  802. max_freq = (rp_state_cap & 0xff0000) >> 16;
  803. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  804. max_freq * 50);
  805. max_freq = (rp_state_cap & 0xff00) >> 8;
  806. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  807. max_freq * 50);
  808. max_freq = rp_state_cap & 0xff;
  809. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  810. max_freq * 50);
  811. } else {
  812. seq_printf(m, "no P-state info available\n");
  813. }
  814. return 0;
  815. }
  816. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  817. {
  818. struct drm_info_node *node = (struct drm_info_node *) m->private;
  819. struct drm_device *dev = node->minor->dev;
  820. drm_i915_private_t *dev_priv = dev->dev_private;
  821. u32 delayfreq;
  822. int i;
  823. for (i = 0; i < 16; i++) {
  824. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  825. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  826. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  827. }
  828. return 0;
  829. }
  830. static inline int MAP_TO_MV(int map)
  831. {
  832. return 1250 - (map * 25);
  833. }
  834. static int i915_inttoext_table(struct seq_file *m, void *unused)
  835. {
  836. struct drm_info_node *node = (struct drm_info_node *) m->private;
  837. struct drm_device *dev = node->minor->dev;
  838. drm_i915_private_t *dev_priv = dev->dev_private;
  839. u32 inttoext;
  840. int i;
  841. for (i = 1; i <= 32; i++) {
  842. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  843. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  844. }
  845. return 0;
  846. }
  847. static int i915_drpc_info(struct seq_file *m, void *unused)
  848. {
  849. struct drm_info_node *node = (struct drm_info_node *) m->private;
  850. struct drm_device *dev = node->minor->dev;
  851. drm_i915_private_t *dev_priv = dev->dev_private;
  852. u32 rgvmodectl = I915_READ(MEMMODECTL);
  853. u32 rstdbyctl = I915_READ(RSTDBYCTL);
  854. u16 crstandvid = I915_READ16(CRSTANDVID);
  855. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  856. "yes" : "no");
  857. seq_printf(m, "Boost freq: %d\n",
  858. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  859. MEMMODE_BOOST_FREQ_SHIFT);
  860. seq_printf(m, "HW control enabled: %s\n",
  861. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  862. seq_printf(m, "SW control enabled: %s\n",
  863. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  864. seq_printf(m, "Gated voltage change: %s\n",
  865. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  866. seq_printf(m, "Starting frequency: P%d\n",
  867. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  868. seq_printf(m, "Max P-state: P%d\n",
  869. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  870. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  871. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  872. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  873. seq_printf(m, "Render standby enabled: %s\n",
  874. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  875. seq_printf(m, "Current RS state: ");
  876. switch (rstdbyctl & RSX_STATUS_MASK) {
  877. case RSX_STATUS_ON:
  878. seq_printf(m, "on\n");
  879. break;
  880. case RSX_STATUS_RC1:
  881. seq_printf(m, "RC1\n");
  882. break;
  883. case RSX_STATUS_RC1E:
  884. seq_printf(m, "RC1E\n");
  885. break;
  886. case RSX_STATUS_RS1:
  887. seq_printf(m, "RS1\n");
  888. break;
  889. case RSX_STATUS_RS2:
  890. seq_printf(m, "RS2 (RC6)\n");
  891. break;
  892. case RSX_STATUS_RS3:
  893. seq_printf(m, "RC3 (RC6+)\n");
  894. break;
  895. default:
  896. seq_printf(m, "unknown\n");
  897. break;
  898. }
  899. return 0;
  900. }
  901. static int i915_fbc_status(struct seq_file *m, void *unused)
  902. {
  903. struct drm_info_node *node = (struct drm_info_node *) m->private;
  904. struct drm_device *dev = node->minor->dev;
  905. drm_i915_private_t *dev_priv = dev->dev_private;
  906. if (!I915_HAS_FBC(dev)) {
  907. seq_printf(m, "FBC unsupported on this chipset\n");
  908. return 0;
  909. }
  910. if (intel_fbc_enabled(dev)) {
  911. seq_printf(m, "FBC enabled\n");
  912. } else {
  913. seq_printf(m, "FBC disabled: ");
  914. switch (dev_priv->no_fbc_reason) {
  915. case FBC_NO_OUTPUT:
  916. seq_printf(m, "no outputs");
  917. break;
  918. case FBC_STOLEN_TOO_SMALL:
  919. seq_printf(m, "not enough stolen memory");
  920. break;
  921. case FBC_UNSUPPORTED_MODE:
  922. seq_printf(m, "mode not supported");
  923. break;
  924. case FBC_MODE_TOO_LARGE:
  925. seq_printf(m, "mode too large");
  926. break;
  927. case FBC_BAD_PLANE:
  928. seq_printf(m, "FBC unsupported on plane");
  929. break;
  930. case FBC_NOT_TILED:
  931. seq_printf(m, "scanout buffer not tiled");
  932. break;
  933. case FBC_MULTIPLE_PIPES:
  934. seq_printf(m, "multiple pipes are enabled");
  935. break;
  936. case FBC_MODULE_PARAM:
  937. seq_printf(m, "disabled per module param (default off)");
  938. break;
  939. default:
  940. seq_printf(m, "unknown reason");
  941. }
  942. seq_printf(m, "\n");
  943. }
  944. return 0;
  945. }
  946. static int i915_sr_status(struct seq_file *m, void *unused)
  947. {
  948. struct drm_info_node *node = (struct drm_info_node *) m->private;
  949. struct drm_device *dev = node->minor->dev;
  950. drm_i915_private_t *dev_priv = dev->dev_private;
  951. bool sr_enabled = false;
  952. if (HAS_PCH_SPLIT(dev))
  953. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  954. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  955. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  956. else if (IS_I915GM(dev))
  957. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  958. else if (IS_PINEVIEW(dev))
  959. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  960. seq_printf(m, "self-refresh: %s\n",
  961. sr_enabled ? "enabled" : "disabled");
  962. return 0;
  963. }
  964. static int i915_emon_status(struct seq_file *m, void *unused)
  965. {
  966. struct drm_info_node *node = (struct drm_info_node *) m->private;
  967. struct drm_device *dev = node->minor->dev;
  968. drm_i915_private_t *dev_priv = dev->dev_private;
  969. unsigned long temp, chipset, gfx;
  970. int ret;
  971. ret = mutex_lock_interruptible(&dev->struct_mutex);
  972. if (ret)
  973. return ret;
  974. temp = i915_mch_val(dev_priv);
  975. chipset = i915_chipset_val(dev_priv);
  976. gfx = i915_gfx_val(dev_priv);
  977. mutex_unlock(&dev->struct_mutex);
  978. seq_printf(m, "GMCH temp: %ld\n", temp);
  979. seq_printf(m, "Chipset power: %ld\n", chipset);
  980. seq_printf(m, "GFX power: %ld\n", gfx);
  981. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  982. return 0;
  983. }
  984. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  985. {
  986. struct drm_info_node *node = (struct drm_info_node *) m->private;
  987. struct drm_device *dev = node->minor->dev;
  988. drm_i915_private_t *dev_priv = dev->dev_private;
  989. int ret;
  990. int gpu_freq, ia_freq;
  991. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  992. seq_printf(m, "unsupported on this chipset\n");
  993. return 0;
  994. }
  995. ret = mutex_lock_interruptible(&dev->struct_mutex);
  996. if (ret)
  997. return ret;
  998. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  999. for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
  1000. gpu_freq++) {
  1001. I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
  1002. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  1003. GEN6_PCODE_READ_MIN_FREQ_TABLE);
  1004. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  1005. GEN6_PCODE_READY) == 0, 10)) {
  1006. DRM_ERROR("pcode read of freq table timed out\n");
  1007. continue;
  1008. }
  1009. ia_freq = I915_READ(GEN6_PCODE_DATA);
  1010. seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
  1011. }
  1012. mutex_unlock(&dev->struct_mutex);
  1013. return 0;
  1014. }
  1015. static int i915_gfxec(struct seq_file *m, void *unused)
  1016. {
  1017. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1018. struct drm_device *dev = node->minor->dev;
  1019. drm_i915_private_t *dev_priv = dev->dev_private;
  1020. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1021. return 0;
  1022. }
  1023. static int i915_opregion(struct seq_file *m, void *unused)
  1024. {
  1025. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1026. struct drm_device *dev = node->minor->dev;
  1027. drm_i915_private_t *dev_priv = dev->dev_private;
  1028. struct intel_opregion *opregion = &dev_priv->opregion;
  1029. int ret;
  1030. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1031. if (ret)
  1032. return ret;
  1033. if (opregion->header)
  1034. seq_write(m, opregion->header, OPREGION_SIZE);
  1035. mutex_unlock(&dev->struct_mutex);
  1036. return 0;
  1037. }
  1038. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1039. {
  1040. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1041. struct drm_device *dev = node->minor->dev;
  1042. drm_i915_private_t *dev_priv = dev->dev_private;
  1043. struct intel_fbdev *ifbdev;
  1044. struct intel_framebuffer *fb;
  1045. int ret;
  1046. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1047. if (ret)
  1048. return ret;
  1049. ifbdev = dev_priv->fbdev;
  1050. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1051. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1052. fb->base.width,
  1053. fb->base.height,
  1054. fb->base.depth,
  1055. fb->base.bits_per_pixel);
  1056. describe_obj(m, fb->obj);
  1057. seq_printf(m, "\n");
  1058. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1059. if (&fb->base == ifbdev->helper.fb)
  1060. continue;
  1061. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1062. fb->base.width,
  1063. fb->base.height,
  1064. fb->base.depth,
  1065. fb->base.bits_per_pixel);
  1066. describe_obj(m, fb->obj);
  1067. seq_printf(m, "\n");
  1068. }
  1069. mutex_unlock(&dev->mode_config.mutex);
  1070. return 0;
  1071. }
  1072. static int i915_context_status(struct seq_file *m, void *unused)
  1073. {
  1074. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1075. struct drm_device *dev = node->minor->dev;
  1076. drm_i915_private_t *dev_priv = dev->dev_private;
  1077. int ret;
  1078. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1079. if (ret)
  1080. return ret;
  1081. if (dev_priv->pwrctx) {
  1082. seq_printf(m, "power context ");
  1083. describe_obj(m, dev_priv->pwrctx);
  1084. seq_printf(m, "\n");
  1085. }
  1086. if (dev_priv->renderctx) {
  1087. seq_printf(m, "render context ");
  1088. describe_obj(m, dev_priv->renderctx);
  1089. seq_printf(m, "\n");
  1090. }
  1091. mutex_unlock(&dev->mode_config.mutex);
  1092. return 0;
  1093. }
  1094. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1095. {
  1096. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1097. struct drm_device *dev = node->minor->dev;
  1098. struct drm_i915_private *dev_priv = dev->dev_private;
  1099. seq_printf(m, "forcewake count = %d\n",
  1100. atomic_read(&dev_priv->forcewake_count));
  1101. return 0;
  1102. }
  1103. static int
  1104. i915_wedged_open(struct inode *inode,
  1105. struct file *filp)
  1106. {
  1107. filp->private_data = inode->i_private;
  1108. return 0;
  1109. }
  1110. static ssize_t
  1111. i915_wedged_read(struct file *filp,
  1112. char __user *ubuf,
  1113. size_t max,
  1114. loff_t *ppos)
  1115. {
  1116. struct drm_device *dev = filp->private_data;
  1117. drm_i915_private_t *dev_priv = dev->dev_private;
  1118. char buf[80];
  1119. int len;
  1120. len = snprintf(buf, sizeof(buf),
  1121. "wedged : %d\n",
  1122. atomic_read(&dev_priv->mm.wedged));
  1123. if (len > sizeof(buf))
  1124. len = sizeof(buf);
  1125. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1126. }
  1127. static ssize_t
  1128. i915_wedged_write(struct file *filp,
  1129. const char __user *ubuf,
  1130. size_t cnt,
  1131. loff_t *ppos)
  1132. {
  1133. struct drm_device *dev = filp->private_data;
  1134. char buf[20];
  1135. int val = 1;
  1136. if (cnt > 0) {
  1137. if (cnt > sizeof(buf) - 1)
  1138. return -EINVAL;
  1139. if (copy_from_user(buf, ubuf, cnt))
  1140. return -EFAULT;
  1141. buf[cnt] = 0;
  1142. val = simple_strtoul(buf, NULL, 0);
  1143. }
  1144. DRM_INFO("Manually setting wedged to %d\n", val);
  1145. i915_handle_error(dev, val);
  1146. return cnt;
  1147. }
  1148. static const struct file_operations i915_wedged_fops = {
  1149. .owner = THIS_MODULE,
  1150. .open = i915_wedged_open,
  1151. .read = i915_wedged_read,
  1152. .write = i915_wedged_write,
  1153. .llseek = default_llseek,
  1154. };
  1155. static int
  1156. i915_max_freq_open(struct inode *inode,
  1157. struct file *filp)
  1158. {
  1159. filp->private_data = inode->i_private;
  1160. return 0;
  1161. }
  1162. static ssize_t
  1163. i915_max_freq_read(struct file *filp,
  1164. char __user *ubuf,
  1165. size_t max,
  1166. loff_t *ppos)
  1167. {
  1168. struct drm_device *dev = filp->private_data;
  1169. drm_i915_private_t *dev_priv = dev->dev_private;
  1170. char buf[80];
  1171. int len;
  1172. len = snprintf(buf, sizeof(buf),
  1173. "max freq: %d\n", dev_priv->max_delay * 50);
  1174. if (len > sizeof(buf))
  1175. len = sizeof(buf);
  1176. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1177. }
  1178. static ssize_t
  1179. i915_max_freq_write(struct file *filp,
  1180. const char __user *ubuf,
  1181. size_t cnt,
  1182. loff_t *ppos)
  1183. {
  1184. struct drm_device *dev = filp->private_data;
  1185. struct drm_i915_private *dev_priv = dev->dev_private;
  1186. char buf[20];
  1187. int val = 1;
  1188. if (cnt > 0) {
  1189. if (cnt > sizeof(buf) - 1)
  1190. return -EINVAL;
  1191. if (copy_from_user(buf, ubuf, cnt))
  1192. return -EFAULT;
  1193. buf[cnt] = 0;
  1194. val = simple_strtoul(buf, NULL, 0);
  1195. }
  1196. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1197. /*
  1198. * Turbo will still be enabled, but won't go above the set value.
  1199. */
  1200. dev_priv->max_delay = val / 50;
  1201. gen6_set_rps(dev, val / 50);
  1202. return cnt;
  1203. }
  1204. static const struct file_operations i915_max_freq_fops = {
  1205. .owner = THIS_MODULE,
  1206. .open = i915_max_freq_open,
  1207. .read = i915_max_freq_read,
  1208. .write = i915_max_freq_write,
  1209. .llseek = default_llseek,
  1210. };
  1211. static int
  1212. i915_cache_sharing_open(struct inode *inode,
  1213. struct file *filp)
  1214. {
  1215. filp->private_data = inode->i_private;
  1216. return 0;
  1217. }
  1218. static ssize_t
  1219. i915_cache_sharing_read(struct file *filp,
  1220. char __user *ubuf,
  1221. size_t max,
  1222. loff_t *ppos)
  1223. {
  1224. struct drm_device *dev = filp->private_data;
  1225. drm_i915_private_t *dev_priv = dev->dev_private;
  1226. char buf[80];
  1227. u32 snpcr;
  1228. int len;
  1229. mutex_lock(&dev_priv->dev->struct_mutex);
  1230. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1231. mutex_unlock(&dev_priv->dev->struct_mutex);
  1232. len = snprintf(buf, sizeof(buf),
  1233. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1234. GEN6_MBC_SNPCR_SHIFT);
  1235. if (len > sizeof(buf))
  1236. len = sizeof(buf);
  1237. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1238. }
  1239. static ssize_t
  1240. i915_cache_sharing_write(struct file *filp,
  1241. const char __user *ubuf,
  1242. size_t cnt,
  1243. loff_t *ppos)
  1244. {
  1245. struct drm_device *dev = filp->private_data;
  1246. struct drm_i915_private *dev_priv = dev->dev_private;
  1247. char buf[20];
  1248. u32 snpcr;
  1249. int val = 1;
  1250. if (cnt > 0) {
  1251. if (cnt > sizeof(buf) - 1)
  1252. return -EINVAL;
  1253. if (copy_from_user(buf, ubuf, cnt))
  1254. return -EFAULT;
  1255. buf[cnt] = 0;
  1256. val = simple_strtoul(buf, NULL, 0);
  1257. }
  1258. if (val < 0 || val > 3)
  1259. return -EINVAL;
  1260. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1261. /* Update the cache sharing policy here as well */
  1262. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1263. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1264. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1265. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1266. return cnt;
  1267. }
  1268. static const struct file_operations i915_cache_sharing_fops = {
  1269. .owner = THIS_MODULE,
  1270. .open = i915_cache_sharing_open,
  1271. .read = i915_cache_sharing_read,
  1272. .write = i915_cache_sharing_write,
  1273. .llseek = default_llseek,
  1274. };
  1275. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1276. * allocated we need to hook into the minor for release. */
  1277. static int
  1278. drm_add_fake_info_node(struct drm_minor *minor,
  1279. struct dentry *ent,
  1280. const void *key)
  1281. {
  1282. struct drm_info_node *node;
  1283. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1284. if (node == NULL) {
  1285. debugfs_remove(ent);
  1286. return -ENOMEM;
  1287. }
  1288. node->minor = minor;
  1289. node->dent = ent;
  1290. node->info_ent = (void *) key;
  1291. list_add(&node->list, &minor->debugfs_nodes.list);
  1292. return 0;
  1293. }
  1294. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  1295. {
  1296. struct drm_device *dev = minor->dev;
  1297. struct dentry *ent;
  1298. ent = debugfs_create_file("i915_wedged",
  1299. S_IRUGO | S_IWUSR,
  1300. root, dev,
  1301. &i915_wedged_fops);
  1302. if (IS_ERR(ent))
  1303. return PTR_ERR(ent);
  1304. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  1305. }
  1306. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1307. {
  1308. struct drm_device *dev = inode->i_private;
  1309. struct drm_i915_private *dev_priv = dev->dev_private;
  1310. int ret;
  1311. if (!IS_GEN6(dev))
  1312. return 0;
  1313. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1314. if (ret)
  1315. return ret;
  1316. gen6_gt_force_wake_get(dev_priv);
  1317. mutex_unlock(&dev->struct_mutex);
  1318. return 0;
  1319. }
  1320. int i915_forcewake_release(struct inode *inode, struct file *file)
  1321. {
  1322. struct drm_device *dev = inode->i_private;
  1323. struct drm_i915_private *dev_priv = dev->dev_private;
  1324. if (!IS_GEN6(dev))
  1325. return 0;
  1326. /*
  1327. * It's bad that we can potentially hang userspace if struct_mutex gets
  1328. * forever stuck. However, if we cannot acquire this lock it means that
  1329. * almost certainly the driver has hung, is not unload-able. Therefore
  1330. * hanging here is probably a minor inconvenience not to be seen my
  1331. * almost every user.
  1332. */
  1333. mutex_lock(&dev->struct_mutex);
  1334. gen6_gt_force_wake_put(dev_priv);
  1335. mutex_unlock(&dev->struct_mutex);
  1336. return 0;
  1337. }
  1338. static const struct file_operations i915_forcewake_fops = {
  1339. .owner = THIS_MODULE,
  1340. .open = i915_forcewake_open,
  1341. .release = i915_forcewake_release,
  1342. };
  1343. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1344. {
  1345. struct drm_device *dev = minor->dev;
  1346. struct dentry *ent;
  1347. ent = debugfs_create_file("i915_forcewake_user",
  1348. S_IRUSR,
  1349. root, dev,
  1350. &i915_forcewake_fops);
  1351. if (IS_ERR(ent))
  1352. return PTR_ERR(ent);
  1353. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1354. }
  1355. static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor)
  1356. {
  1357. struct drm_device *dev = minor->dev;
  1358. struct dentry *ent;
  1359. ent = debugfs_create_file("i915_max_freq",
  1360. S_IRUGO | S_IWUSR,
  1361. root, dev,
  1362. &i915_max_freq_fops);
  1363. if (IS_ERR(ent))
  1364. return PTR_ERR(ent);
  1365. return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops);
  1366. }
  1367. static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor)
  1368. {
  1369. struct drm_device *dev = minor->dev;
  1370. struct dentry *ent;
  1371. ent = debugfs_create_file("i915_cache_sharing",
  1372. S_IRUGO | S_IWUSR,
  1373. root, dev,
  1374. &i915_cache_sharing_fops);
  1375. if (IS_ERR(ent))
  1376. return PTR_ERR(ent);
  1377. return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops);
  1378. }
  1379. static struct drm_info_list i915_debugfs_list[] = {
  1380. {"i915_capabilities", i915_capabilities, 0},
  1381. {"i915_gem_objects", i915_gem_object_info, 0},
  1382. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1383. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1384. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  1385. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1386. {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
  1387. {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
  1388. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1389. {"i915_gem_request", i915_gem_request_info, 0},
  1390. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1391. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1392. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1393. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1394. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1395. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1396. {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
  1397. {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
  1398. {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
  1399. {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
  1400. {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
  1401. {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
  1402. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  1403. {"i915_error_state", i915_error_state, 0},
  1404. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1405. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1406. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1407. {"i915_inttoext_table", i915_inttoext_table, 0},
  1408. {"i915_drpc_info", i915_drpc_info, 0},
  1409. {"i915_emon_status", i915_emon_status, 0},
  1410. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1411. {"i915_gfxec", i915_gfxec, 0},
  1412. {"i915_fbc_status", i915_fbc_status, 0},
  1413. {"i915_sr_status", i915_sr_status, 0},
  1414. {"i915_opregion", i915_opregion, 0},
  1415. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1416. {"i915_context_status", i915_context_status, 0},
  1417. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1418. };
  1419. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1420. int i915_debugfs_init(struct drm_minor *minor)
  1421. {
  1422. int ret;
  1423. ret = i915_wedged_create(minor->debugfs_root, minor);
  1424. if (ret)
  1425. return ret;
  1426. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1427. if (ret)
  1428. return ret;
  1429. ret = i915_max_freq_create(minor->debugfs_root, minor);
  1430. if (ret)
  1431. return ret;
  1432. ret = i915_cache_sharing_create(minor->debugfs_root, minor);
  1433. if (ret)
  1434. return ret;
  1435. return drm_debugfs_create_files(i915_debugfs_list,
  1436. I915_DEBUGFS_ENTRIES,
  1437. minor->debugfs_root, minor);
  1438. }
  1439. void i915_debugfs_cleanup(struct drm_minor *minor)
  1440. {
  1441. drm_debugfs_remove_files(i915_debugfs_list,
  1442. I915_DEBUGFS_ENTRIES, minor);
  1443. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1444. 1, minor);
  1445. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1446. 1, minor);
  1447. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1448. 1, minor);
  1449. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1450. 1, minor);
  1451. }
  1452. #endif /* CONFIG_DEBUG_FS */