dmatest.c 17 KB

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  1. /*
  2. * DMA Engine test module
  3. *
  4. * Copyright (C) 2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/freezer.h>
  14. #include <linux/init.h>
  15. #include <linux/kthread.h>
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/random.h>
  19. #include <linux/slab.h>
  20. #include <linux/wait.h>
  21. static unsigned int test_buf_size = 16384;
  22. module_param(test_buf_size, uint, S_IRUGO);
  23. MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
  24. static char test_channel[20];
  25. module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
  26. MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
  27. static char test_device[20];
  28. module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
  29. MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
  30. static unsigned int threads_per_chan = 1;
  31. module_param(threads_per_chan, uint, S_IRUGO);
  32. MODULE_PARM_DESC(threads_per_chan,
  33. "Number of threads to start per channel (default: 1)");
  34. static unsigned int max_channels;
  35. module_param(max_channels, uint, S_IRUGO);
  36. MODULE_PARM_DESC(max_channels,
  37. "Maximum number of channels to use (default: all)");
  38. static unsigned int iterations;
  39. module_param(iterations, uint, S_IRUGO);
  40. MODULE_PARM_DESC(iterations,
  41. "Iterations before stopping test (default: infinite)");
  42. static unsigned int xor_sources = 3;
  43. module_param(xor_sources, uint, S_IRUGO);
  44. MODULE_PARM_DESC(xor_sources,
  45. "Number of xor source buffers (default: 3)");
  46. static unsigned int pq_sources = 3;
  47. module_param(pq_sources, uint, S_IRUGO);
  48. MODULE_PARM_DESC(pq_sources,
  49. "Number of p+q source buffers (default: 3)");
  50. static int timeout = 3000;
  51. module_param(timeout, uint, S_IRUGO);
  52. MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
  53. "Pass -1 for infinite timeout");
  54. /*
  55. * Initialization patterns. All bytes in the source buffer has bit 7
  56. * set, all bytes in the destination buffer has bit 7 cleared.
  57. *
  58. * Bit 6 is set for all bytes which are to be copied by the DMA
  59. * engine. Bit 5 is set for all bytes which are to be overwritten by
  60. * the DMA engine.
  61. *
  62. * The remaining bits are the inverse of a counter which increments by
  63. * one for each byte address.
  64. */
  65. #define PATTERN_SRC 0x80
  66. #define PATTERN_DST 0x00
  67. #define PATTERN_COPY 0x40
  68. #define PATTERN_OVERWRITE 0x20
  69. #define PATTERN_COUNT_MASK 0x1f
  70. struct dmatest_thread {
  71. struct list_head node;
  72. struct task_struct *task;
  73. struct dma_chan *chan;
  74. u8 **srcs;
  75. u8 **dsts;
  76. enum dma_transaction_type type;
  77. };
  78. struct dmatest_chan {
  79. struct list_head node;
  80. struct dma_chan *chan;
  81. struct list_head threads;
  82. };
  83. /*
  84. * These are protected by dma_list_mutex since they're only used by
  85. * the DMA filter function callback
  86. */
  87. static LIST_HEAD(dmatest_channels);
  88. static unsigned int nr_channels;
  89. static bool dmatest_match_channel(struct dma_chan *chan)
  90. {
  91. if (test_channel[0] == '\0')
  92. return true;
  93. return strcmp(dma_chan_name(chan), test_channel) == 0;
  94. }
  95. static bool dmatest_match_device(struct dma_device *device)
  96. {
  97. if (test_device[0] == '\0')
  98. return true;
  99. return strcmp(dev_name(device->dev), test_device) == 0;
  100. }
  101. static unsigned long dmatest_random(void)
  102. {
  103. unsigned long buf;
  104. get_random_bytes(&buf, sizeof(buf));
  105. return buf;
  106. }
  107. static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len)
  108. {
  109. unsigned int i;
  110. u8 *buf;
  111. for (; (buf = *bufs); bufs++) {
  112. for (i = 0; i < start; i++)
  113. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  114. for ( ; i < start + len; i++)
  115. buf[i] = PATTERN_SRC | PATTERN_COPY
  116. | (~i & PATTERN_COUNT_MASK);
  117. for ( ; i < test_buf_size; i++)
  118. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  119. buf++;
  120. }
  121. }
  122. static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len)
  123. {
  124. unsigned int i;
  125. u8 *buf;
  126. for (; (buf = *bufs); bufs++) {
  127. for (i = 0; i < start; i++)
  128. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  129. for ( ; i < start + len; i++)
  130. buf[i] = PATTERN_DST | PATTERN_OVERWRITE
  131. | (~i & PATTERN_COUNT_MASK);
  132. for ( ; i < test_buf_size; i++)
  133. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  134. }
  135. }
  136. static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
  137. unsigned int counter, bool is_srcbuf)
  138. {
  139. u8 diff = actual ^ pattern;
  140. u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
  141. const char *thread_name = current->comm;
  142. if (is_srcbuf)
  143. pr_warning("%s: srcbuf[0x%x] overwritten!"
  144. " Expected %02x, got %02x\n",
  145. thread_name, index, expected, actual);
  146. else if ((pattern & PATTERN_COPY)
  147. && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
  148. pr_warning("%s: dstbuf[0x%x] not copied!"
  149. " Expected %02x, got %02x\n",
  150. thread_name, index, expected, actual);
  151. else if (diff & PATTERN_SRC)
  152. pr_warning("%s: dstbuf[0x%x] was copied!"
  153. " Expected %02x, got %02x\n",
  154. thread_name, index, expected, actual);
  155. else
  156. pr_warning("%s: dstbuf[0x%x] mismatch!"
  157. " Expected %02x, got %02x\n",
  158. thread_name, index, expected, actual);
  159. }
  160. static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
  161. unsigned int end, unsigned int counter, u8 pattern,
  162. bool is_srcbuf)
  163. {
  164. unsigned int i;
  165. unsigned int error_count = 0;
  166. u8 actual;
  167. u8 expected;
  168. u8 *buf;
  169. unsigned int counter_orig = counter;
  170. for (; (buf = *bufs); bufs++) {
  171. counter = counter_orig;
  172. for (i = start; i < end; i++) {
  173. actual = buf[i];
  174. expected = pattern | (~counter & PATTERN_COUNT_MASK);
  175. if (actual != expected) {
  176. if (error_count < 32)
  177. dmatest_mismatch(actual, pattern, i,
  178. counter, is_srcbuf);
  179. error_count++;
  180. }
  181. counter++;
  182. }
  183. }
  184. if (error_count > 32)
  185. pr_warning("%s: %u errors suppressed\n",
  186. current->comm, error_count - 32);
  187. return error_count;
  188. }
  189. static void dmatest_callback(void *completion)
  190. {
  191. complete(completion);
  192. }
  193. /*
  194. * This function repeatedly tests DMA transfers of various lengths and
  195. * offsets for a given operation type until it is told to exit by
  196. * kthread_stop(). There may be multiple threads running this function
  197. * in parallel for a single channel, and there may be multiple channels
  198. * being tested in parallel.
  199. *
  200. * Before each test, the source and destination buffer is initialized
  201. * with a known pattern. This pattern is different depending on
  202. * whether it's in an area which is supposed to be copied or
  203. * overwritten, and different in the source and destination buffers.
  204. * So if the DMA engine doesn't copy exactly what we tell it to copy,
  205. * we'll notice.
  206. */
  207. static int dmatest_func(void *data)
  208. {
  209. struct dmatest_thread *thread = data;
  210. struct dma_chan *chan;
  211. const char *thread_name;
  212. unsigned int src_off, dst_off, len;
  213. unsigned int error_count;
  214. unsigned int failed_tests = 0;
  215. unsigned int total_tests = 0;
  216. dma_cookie_t cookie;
  217. enum dma_status status;
  218. enum dma_ctrl_flags flags;
  219. u8 pq_coefs[pq_sources + 1];
  220. int ret;
  221. int src_cnt;
  222. int dst_cnt;
  223. int i;
  224. thread_name = current->comm;
  225. set_freezable_with_signal();
  226. ret = -ENOMEM;
  227. smp_rmb();
  228. chan = thread->chan;
  229. if (thread->type == DMA_MEMCPY)
  230. src_cnt = dst_cnt = 1;
  231. else if (thread->type == DMA_XOR) {
  232. src_cnt = xor_sources | 1; /* force odd to ensure dst = src */
  233. dst_cnt = 1;
  234. } else if (thread->type == DMA_PQ) {
  235. src_cnt = pq_sources | 1; /* force odd to ensure dst = src */
  236. dst_cnt = 2;
  237. for (i = 0; i < src_cnt; i++)
  238. pq_coefs[i] = 1;
  239. } else
  240. goto err_srcs;
  241. thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
  242. if (!thread->srcs)
  243. goto err_srcs;
  244. for (i = 0; i < src_cnt; i++) {
  245. thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL);
  246. if (!thread->srcs[i])
  247. goto err_srcbuf;
  248. }
  249. thread->srcs[i] = NULL;
  250. thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
  251. if (!thread->dsts)
  252. goto err_dsts;
  253. for (i = 0; i < dst_cnt; i++) {
  254. thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL);
  255. if (!thread->dsts[i])
  256. goto err_dstbuf;
  257. }
  258. thread->dsts[i] = NULL;
  259. set_user_nice(current, 10);
  260. /*
  261. * src buffers are freed by the DMAEngine code with dma_unmap_single()
  262. * dst buffers are freed by ourselves below
  263. */
  264. flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT
  265. | DMA_COMPL_SKIP_DEST_UNMAP | DMA_COMPL_SRC_UNMAP_SINGLE;
  266. while (!kthread_should_stop()
  267. && !(iterations && total_tests >= iterations)) {
  268. struct dma_device *dev = chan->device;
  269. struct dma_async_tx_descriptor *tx = NULL;
  270. dma_addr_t dma_srcs[src_cnt];
  271. dma_addr_t dma_dsts[dst_cnt];
  272. struct completion cmp;
  273. unsigned long start, tmo, end = 0 /* compiler... */;
  274. bool reload = true;
  275. u8 align = 0;
  276. total_tests++;
  277. /* honor alignment restrictions */
  278. if (thread->type == DMA_MEMCPY)
  279. align = dev->copy_align;
  280. else if (thread->type == DMA_XOR)
  281. align = dev->xor_align;
  282. else if (thread->type == DMA_PQ)
  283. align = dev->pq_align;
  284. if (1 << align > test_buf_size) {
  285. pr_err("%u-byte buffer too small for %d-byte alignment\n",
  286. test_buf_size, 1 << align);
  287. break;
  288. }
  289. len = dmatest_random() % test_buf_size + 1;
  290. len = (len >> align) << align;
  291. if (!len)
  292. len = 1 << align;
  293. src_off = dmatest_random() % (test_buf_size - len + 1);
  294. dst_off = dmatest_random() % (test_buf_size - len + 1);
  295. src_off = (src_off >> align) << align;
  296. dst_off = (dst_off >> align) << align;
  297. dmatest_init_srcs(thread->srcs, src_off, len);
  298. dmatest_init_dsts(thread->dsts, dst_off, len);
  299. for (i = 0; i < src_cnt; i++) {
  300. u8 *buf = thread->srcs[i] + src_off;
  301. dma_srcs[i] = dma_map_single(dev->dev, buf, len,
  302. DMA_TO_DEVICE);
  303. }
  304. /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
  305. for (i = 0; i < dst_cnt; i++) {
  306. dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
  307. test_buf_size,
  308. DMA_BIDIRECTIONAL);
  309. }
  310. if (thread->type == DMA_MEMCPY)
  311. tx = dev->device_prep_dma_memcpy(chan,
  312. dma_dsts[0] + dst_off,
  313. dma_srcs[0], len,
  314. flags);
  315. else if (thread->type == DMA_XOR)
  316. tx = dev->device_prep_dma_xor(chan,
  317. dma_dsts[0] + dst_off,
  318. dma_srcs, src_cnt,
  319. len, flags);
  320. else if (thread->type == DMA_PQ) {
  321. dma_addr_t dma_pq[dst_cnt];
  322. for (i = 0; i < dst_cnt; i++)
  323. dma_pq[i] = dma_dsts[i] + dst_off;
  324. tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
  325. src_cnt, pq_coefs,
  326. len, flags);
  327. }
  328. if (!tx) {
  329. for (i = 0; i < src_cnt; i++)
  330. dma_unmap_single(dev->dev, dma_srcs[i], len,
  331. DMA_TO_DEVICE);
  332. for (i = 0; i < dst_cnt; i++)
  333. dma_unmap_single(dev->dev, dma_dsts[i],
  334. test_buf_size,
  335. DMA_BIDIRECTIONAL);
  336. pr_warning("%s: #%u: prep error with src_off=0x%x "
  337. "dst_off=0x%x len=0x%x\n",
  338. thread_name, total_tests - 1,
  339. src_off, dst_off, len);
  340. msleep(100);
  341. failed_tests++;
  342. continue;
  343. }
  344. init_completion(&cmp);
  345. tx->callback = dmatest_callback;
  346. tx->callback_param = &cmp;
  347. cookie = tx->tx_submit(tx);
  348. if (dma_submit_error(cookie)) {
  349. pr_warning("%s: #%u: submit error %d with src_off=0x%x "
  350. "dst_off=0x%x len=0x%x\n",
  351. thread_name, total_tests - 1, cookie,
  352. src_off, dst_off, len);
  353. msleep(100);
  354. failed_tests++;
  355. continue;
  356. }
  357. dma_async_issue_pending(chan);
  358. do {
  359. start = jiffies;
  360. if (reload)
  361. end = start + msecs_to_jiffies(timeout);
  362. else if (end <= start)
  363. end = start + 1;
  364. tmo = wait_for_completion_interruptible_timeout(&cmp,
  365. end - start);
  366. reload = try_to_freeze();
  367. } while (tmo == -ERESTARTSYS);
  368. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  369. if (tmo == 0) {
  370. pr_warning("%s: #%u: test timed out\n",
  371. thread_name, total_tests - 1);
  372. failed_tests++;
  373. continue;
  374. } else if (status != DMA_SUCCESS) {
  375. pr_warning("%s: #%u: got completion callback,"
  376. " but status is \'%s\'\n",
  377. thread_name, total_tests - 1,
  378. status == DMA_ERROR ? "error" : "in progress");
  379. failed_tests++;
  380. continue;
  381. }
  382. /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
  383. for (i = 0; i < dst_cnt; i++)
  384. dma_unmap_single(dev->dev, dma_dsts[i], test_buf_size,
  385. DMA_BIDIRECTIONAL);
  386. error_count = 0;
  387. pr_debug("%s: verifying source buffer...\n", thread_name);
  388. error_count += dmatest_verify(thread->srcs, 0, src_off,
  389. 0, PATTERN_SRC, true);
  390. error_count += dmatest_verify(thread->srcs, src_off,
  391. src_off + len, src_off,
  392. PATTERN_SRC | PATTERN_COPY, true);
  393. error_count += dmatest_verify(thread->srcs, src_off + len,
  394. test_buf_size, src_off + len,
  395. PATTERN_SRC, true);
  396. pr_debug("%s: verifying dest buffer...\n",
  397. thread->task->comm);
  398. error_count += dmatest_verify(thread->dsts, 0, dst_off,
  399. 0, PATTERN_DST, false);
  400. error_count += dmatest_verify(thread->dsts, dst_off,
  401. dst_off + len, src_off,
  402. PATTERN_SRC | PATTERN_COPY, false);
  403. error_count += dmatest_verify(thread->dsts, dst_off + len,
  404. test_buf_size, dst_off + len,
  405. PATTERN_DST, false);
  406. if (error_count) {
  407. pr_warning("%s: #%u: %u errors with "
  408. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  409. thread_name, total_tests - 1, error_count,
  410. src_off, dst_off, len);
  411. failed_tests++;
  412. } else {
  413. pr_debug("%s: #%u: No errors with "
  414. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  415. thread_name, total_tests - 1,
  416. src_off, dst_off, len);
  417. }
  418. }
  419. ret = 0;
  420. for (i = 0; thread->dsts[i]; i++)
  421. kfree(thread->dsts[i]);
  422. err_dstbuf:
  423. kfree(thread->dsts);
  424. err_dsts:
  425. for (i = 0; thread->srcs[i]; i++)
  426. kfree(thread->srcs[i]);
  427. err_srcbuf:
  428. kfree(thread->srcs);
  429. err_srcs:
  430. pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
  431. thread_name, total_tests, failed_tests, ret);
  432. /* terminate all transfers on specified channels */
  433. chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
  434. if (iterations > 0)
  435. while (!kthread_should_stop()) {
  436. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
  437. interruptible_sleep_on(&wait_dmatest_exit);
  438. }
  439. return ret;
  440. }
  441. static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
  442. {
  443. struct dmatest_thread *thread;
  444. struct dmatest_thread *_thread;
  445. int ret;
  446. list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
  447. ret = kthread_stop(thread->task);
  448. pr_debug("dmatest: thread %s exited with status %d\n",
  449. thread->task->comm, ret);
  450. list_del(&thread->node);
  451. kfree(thread);
  452. }
  453. /* terminate all transfers on specified channels */
  454. dtc->chan->device->device_control(dtc->chan, DMA_TERMINATE_ALL, 0);
  455. kfree(dtc);
  456. }
  457. static int dmatest_add_threads(struct dmatest_chan *dtc, enum dma_transaction_type type)
  458. {
  459. struct dmatest_thread *thread;
  460. struct dma_chan *chan = dtc->chan;
  461. char *op;
  462. unsigned int i;
  463. if (type == DMA_MEMCPY)
  464. op = "copy";
  465. else if (type == DMA_XOR)
  466. op = "xor";
  467. else if (type == DMA_PQ)
  468. op = "pq";
  469. else
  470. return -EINVAL;
  471. for (i = 0; i < threads_per_chan; i++) {
  472. thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
  473. if (!thread) {
  474. pr_warning("dmatest: No memory for %s-%s%u\n",
  475. dma_chan_name(chan), op, i);
  476. break;
  477. }
  478. thread->chan = dtc->chan;
  479. thread->type = type;
  480. smp_wmb();
  481. thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
  482. dma_chan_name(chan), op, i);
  483. if (IS_ERR(thread->task)) {
  484. pr_warning("dmatest: Failed to run thread %s-%s%u\n",
  485. dma_chan_name(chan), op, i);
  486. kfree(thread);
  487. break;
  488. }
  489. /* srcbuf and dstbuf are allocated by the thread itself */
  490. list_add_tail(&thread->node, &dtc->threads);
  491. }
  492. return i;
  493. }
  494. static int dmatest_add_channel(struct dma_chan *chan)
  495. {
  496. struct dmatest_chan *dtc;
  497. struct dma_device *dma_dev = chan->device;
  498. unsigned int thread_count = 0;
  499. int cnt;
  500. dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
  501. if (!dtc) {
  502. pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
  503. return -ENOMEM;
  504. }
  505. dtc->chan = chan;
  506. INIT_LIST_HEAD(&dtc->threads);
  507. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
  508. cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
  509. thread_count += cnt > 0 ? cnt : 0;
  510. }
  511. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  512. cnt = dmatest_add_threads(dtc, DMA_XOR);
  513. thread_count += cnt > 0 ? cnt : 0;
  514. }
  515. if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
  516. cnt = dmatest_add_threads(dtc, DMA_PQ);
  517. thread_count += cnt > 0 ?: 0;
  518. }
  519. pr_info("dmatest: Started %u threads using %s\n",
  520. thread_count, dma_chan_name(chan));
  521. list_add_tail(&dtc->node, &dmatest_channels);
  522. nr_channels++;
  523. return 0;
  524. }
  525. static bool filter(struct dma_chan *chan, void *param)
  526. {
  527. if (!dmatest_match_channel(chan) || !dmatest_match_device(chan->device))
  528. return false;
  529. else
  530. return true;
  531. }
  532. static int __init dmatest_init(void)
  533. {
  534. dma_cap_mask_t mask;
  535. struct dma_chan *chan;
  536. int err = 0;
  537. dma_cap_zero(mask);
  538. dma_cap_set(DMA_MEMCPY, mask);
  539. for (;;) {
  540. chan = dma_request_channel(mask, filter, NULL);
  541. if (chan) {
  542. err = dmatest_add_channel(chan);
  543. if (err) {
  544. dma_release_channel(chan);
  545. break; /* add_channel failed, punt */
  546. }
  547. } else
  548. break; /* no more channels available */
  549. if (max_channels && nr_channels >= max_channels)
  550. break; /* we have all we need */
  551. }
  552. return err;
  553. }
  554. /* when compiled-in wait for drivers to load first */
  555. late_initcall(dmatest_init);
  556. static void __exit dmatest_exit(void)
  557. {
  558. struct dmatest_chan *dtc, *_dtc;
  559. struct dma_chan *chan;
  560. list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) {
  561. list_del(&dtc->node);
  562. chan = dtc->chan;
  563. dmatest_cleanup_channel(dtc);
  564. pr_debug("dmatest: dropped channel %s\n",
  565. dma_chan_name(chan));
  566. dma_release_channel(chan);
  567. }
  568. }
  569. module_exit(dmatest_exit);
  570. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  571. MODULE_LICENSE("GPL v2");