ctrl.c 7.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271
  1. /*
  2. * CAAM control-plane driver backend
  3. * Controller-level driver, kernel property detection, initialization
  4. *
  5. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  6. */
  7. #include "compat.h"
  8. #include "regs.h"
  9. #include "intern.h"
  10. #include "jr.h"
  11. static int caam_remove(struct platform_device *pdev)
  12. {
  13. struct device *ctrldev;
  14. struct caam_drv_private *ctrlpriv;
  15. struct caam_drv_private_jr *jrpriv;
  16. struct caam_full __iomem *topregs;
  17. int ring, ret = 0;
  18. ctrldev = &pdev->dev;
  19. ctrlpriv = dev_get_drvdata(ctrldev);
  20. topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
  21. /* shut down JobRs */
  22. for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
  23. ret |= caam_jr_shutdown(ctrlpriv->jrdev[ring]);
  24. jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]);
  25. irq_dispose_mapping(jrpriv->irq);
  26. }
  27. /* Shut down debug views */
  28. #ifdef CONFIG_DEBUG_FS
  29. debugfs_remove_recursive(ctrlpriv->dfs_root);
  30. #endif
  31. /* Unmap controller region */
  32. iounmap(&topregs->ctrl);
  33. kfree(ctrlpriv->jrdev);
  34. kfree(ctrlpriv);
  35. return ret;
  36. }
  37. /* Probe routine for CAAM top (controller) level */
  38. static int caam_probe(struct platform_device *pdev)
  39. {
  40. int d, ring, rspec;
  41. struct device *dev;
  42. struct device_node *nprop, *np;
  43. struct caam_ctrl __iomem *ctrl;
  44. struct caam_full __iomem *topregs;
  45. struct caam_drv_private *ctrlpriv;
  46. struct caam_deco **deco;
  47. u32 deconum;
  48. #ifdef CONFIG_DEBUG_FS
  49. struct caam_perfmon *perfmon;
  50. #endif
  51. ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
  52. if (!ctrlpriv)
  53. return -ENOMEM;
  54. dev = &pdev->dev;
  55. dev_set_drvdata(dev, ctrlpriv);
  56. ctrlpriv->pdev = pdev;
  57. nprop = pdev->dev.of_node;
  58. /* Get configuration properties from device tree */
  59. /* First, get register page */
  60. ctrl = of_iomap(nprop, 0);
  61. if (ctrl == NULL) {
  62. dev_err(dev, "caam: of_iomap() failed\n");
  63. return -ENOMEM;
  64. }
  65. ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
  66. /* topregs used to derive pointers to CAAM sub-blocks only */
  67. topregs = (struct caam_full __iomem *)ctrl;
  68. /* Get the IRQ of the controller (for security violations only) */
  69. ctrlpriv->secvio_irq = of_irq_to_resource(nprop, 0, NULL);
  70. /*
  71. * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
  72. * 36-bit pointers in master configuration register
  73. */
  74. setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
  75. (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
  76. if (sizeof(dma_addr_t) == sizeof(u64))
  77. dma_set_mask(dev, DMA_BIT_MASK(36));
  78. /* Find out how many DECOs are present */
  79. deconum = (rd_reg64(&topregs->ctrl.perfmon.cha_num) &
  80. CHA_NUM_DECONUM_MASK) >> CHA_NUM_DECONUM_SHIFT;
  81. ctrlpriv->deco = kmalloc(deconum * sizeof(struct caam_deco *),
  82. GFP_KERNEL);
  83. deco = (struct caam_deco __force **)&topregs->deco;
  84. for (d = 0; d < deconum; d++)
  85. ctrlpriv->deco[d] = deco[d];
  86. /*
  87. * Detect and enable JobRs
  88. * First, find out how many ring spec'ed, allocate references
  89. * for all, then go probe each one.
  90. */
  91. rspec = 0;
  92. for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring")
  93. rspec++;
  94. ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL);
  95. if (ctrlpriv->jrdev == NULL) {
  96. iounmap(&topregs->ctrl);
  97. return -ENOMEM;
  98. }
  99. ring = 0;
  100. ctrlpriv->total_jobrs = 0;
  101. for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") {
  102. caam_jr_probe(pdev, np, ring);
  103. ctrlpriv->total_jobrs++;
  104. ring++;
  105. }
  106. /* Check to see if QI present. If so, enable */
  107. ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
  108. CTPR_QI_MASK);
  109. if (ctrlpriv->qi_present) {
  110. ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi;
  111. /* This is all that's required to physically enable QI */
  112. wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN);
  113. }
  114. /* If no QI and no rings specified, quit and go home */
  115. if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
  116. dev_err(dev, "no queues configured, terminating\n");
  117. caam_remove(pdev);
  118. return -ENOMEM;
  119. }
  120. /* NOTE: RTIC detection ought to go here, around Si time */
  121. /* Initialize queue allocator lock */
  122. spin_lock_init(&ctrlpriv->jr_alloc_lock);
  123. /* Report "alive" for developer to see */
  124. dev_info(dev, "device ID = 0x%016llx\n",
  125. rd_reg64(&topregs->ctrl.perfmon.caam_id));
  126. dev_info(dev, "job rings = %d, qi = %d\n",
  127. ctrlpriv->total_jobrs, ctrlpriv->qi_present);
  128. #ifdef CONFIG_DEBUG_FS
  129. /*
  130. * FIXME: needs better naming distinction, as some amalgamation of
  131. * "caam" and nprop->full_name. The OF name isn't distinctive,
  132. * but does separate instances
  133. */
  134. perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
  135. ctrlpriv->dfs_root = debugfs_create_dir("caam", NULL);
  136. ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
  137. /* Controller-level - performance monitor counters */
  138. ctrlpriv->ctl_rq_dequeued =
  139. debugfs_create_u64("rq_dequeued",
  140. S_IRUSR | S_IRGRP | S_IROTH,
  141. ctrlpriv->ctl, &perfmon->req_dequeued);
  142. ctrlpriv->ctl_ob_enc_req =
  143. debugfs_create_u64("ob_rq_encrypted",
  144. S_IRUSR | S_IRGRP | S_IROTH,
  145. ctrlpriv->ctl, &perfmon->ob_enc_req);
  146. ctrlpriv->ctl_ib_dec_req =
  147. debugfs_create_u64("ib_rq_decrypted",
  148. S_IRUSR | S_IRGRP | S_IROTH,
  149. ctrlpriv->ctl, &perfmon->ib_dec_req);
  150. ctrlpriv->ctl_ob_enc_bytes =
  151. debugfs_create_u64("ob_bytes_encrypted",
  152. S_IRUSR | S_IRGRP | S_IROTH,
  153. ctrlpriv->ctl, &perfmon->ob_enc_bytes);
  154. ctrlpriv->ctl_ob_prot_bytes =
  155. debugfs_create_u64("ob_bytes_protected",
  156. S_IRUSR | S_IRGRP | S_IROTH,
  157. ctrlpriv->ctl, &perfmon->ob_prot_bytes);
  158. ctrlpriv->ctl_ib_dec_bytes =
  159. debugfs_create_u64("ib_bytes_decrypted",
  160. S_IRUSR | S_IRGRP | S_IROTH,
  161. ctrlpriv->ctl, &perfmon->ib_dec_bytes);
  162. ctrlpriv->ctl_ib_valid_bytes =
  163. debugfs_create_u64("ib_bytes_validated",
  164. S_IRUSR | S_IRGRP | S_IROTH,
  165. ctrlpriv->ctl, &perfmon->ib_valid_bytes);
  166. /* Controller level - global status values */
  167. ctrlpriv->ctl_faultaddr =
  168. debugfs_create_u64("fault_addr",
  169. S_IRUSR | S_IRGRP | S_IROTH,
  170. ctrlpriv->ctl, &perfmon->faultaddr);
  171. ctrlpriv->ctl_faultdetail =
  172. debugfs_create_u32("fault_detail",
  173. S_IRUSR | S_IRGRP | S_IROTH,
  174. ctrlpriv->ctl, &perfmon->faultdetail);
  175. ctrlpriv->ctl_faultstatus =
  176. debugfs_create_u32("fault_status",
  177. S_IRUSR | S_IRGRP | S_IROTH,
  178. ctrlpriv->ctl, &perfmon->status);
  179. /* Internal covering keys (useful in non-secure mode only) */
  180. ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
  181. ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
  182. ctrlpriv->ctl_kek = debugfs_create_blob("kek",
  183. S_IRUSR |
  184. S_IRGRP | S_IROTH,
  185. ctrlpriv->ctl,
  186. &ctrlpriv->ctl_kek_wrap);
  187. ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
  188. ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
  189. ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
  190. S_IRUSR |
  191. S_IRGRP | S_IROTH,
  192. ctrlpriv->ctl,
  193. &ctrlpriv->ctl_tkek_wrap);
  194. ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
  195. ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
  196. ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
  197. S_IRUSR |
  198. S_IRGRP | S_IROTH,
  199. ctrlpriv->ctl,
  200. &ctrlpriv->ctl_tdsk_wrap);
  201. #endif
  202. return 0;
  203. }
  204. static struct of_device_id caam_match[] = {
  205. {
  206. .compatible = "fsl,sec-v4.0",
  207. },
  208. {},
  209. };
  210. MODULE_DEVICE_TABLE(of, caam_match);
  211. static struct platform_driver caam_driver = {
  212. .driver = {
  213. .name = "caam",
  214. .owner = THIS_MODULE,
  215. .of_match_table = caam_match,
  216. },
  217. .probe = caam_probe,
  218. .remove = __devexit_p(caam_remove),
  219. };
  220. static int __init caam_base_init(void)
  221. {
  222. return platform_driver_register(&caam_driver);
  223. }
  224. static void __exit caam_base_exit(void)
  225. {
  226. return platform_driver_unregister(&caam_driver);
  227. }
  228. module_init(caam_base_init);
  229. module_exit(caam_base_exit);
  230. MODULE_LICENSE("GPL");
  231. MODULE_DESCRIPTION("FSL CAAM request backend");
  232. MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");