amd_nb.h 1.4 KB

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  1. #ifndef _ASM_X86_AMD_NB_H
  2. #define _ASM_X86_AMD_NB_H
  3. #include <linux/pci.h>
  4. struct amd_nb_bus_dev_range {
  5. u8 bus;
  6. u8 dev_base;
  7. u8 dev_limit;
  8. };
  9. extern const struct pci_device_id amd_nb_misc_ids[];
  10. extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
  11. extern bool early_is_amd_nb(u32 value);
  12. extern int amd_cache_northbridges(void);
  13. extern void amd_flush_garts(void);
  14. extern int amd_numa_init(void);
  15. extern int amd_get_subcaches(int);
  16. extern int amd_set_subcaches(int, int);
  17. struct amd_l3_cache {
  18. unsigned indices;
  19. u8 subcaches[4];
  20. };
  21. struct amd_northbridge {
  22. struct pci_dev *misc;
  23. struct pci_dev *link;
  24. struct amd_l3_cache l3_cache;
  25. };
  26. struct amd_northbridge_info {
  27. u16 num;
  28. u64 flags;
  29. struct amd_northbridge *nb;
  30. };
  31. extern struct amd_northbridge_info amd_northbridges;
  32. #define AMD_NB_GART BIT(0)
  33. #define AMD_NB_L3_INDEX_DISABLE BIT(1)
  34. #define AMD_NB_L3_PARTITIONING BIT(2)
  35. #ifdef CONFIG_AMD_NB
  36. static inline u16 amd_nb_num(void)
  37. {
  38. return amd_northbridges.num;
  39. }
  40. static inline bool amd_nb_has_feature(unsigned feature)
  41. {
  42. return ((amd_northbridges.flags & feature) == feature);
  43. }
  44. static inline struct amd_northbridge *node_to_amd_nb(int node)
  45. {
  46. return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
  47. }
  48. #else
  49. #define amd_nb_num(x) 0
  50. #define amd_nb_has_feature(x) false
  51. #define node_to_amd_nb(x) NULL
  52. #endif
  53. #endif /* _ASM_X86_AMD_NB_H */