p2020ds.dts 8.1 KB

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  1. /*
  2. * P2020 DS Device Tree Source
  3. *
  4. * Copyright 2009-2011 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /include/ "p2020si.dtsi"
  12. / {
  13. model = "fsl,P2020DS";
  14. compatible = "fsl,P2020DS";
  15. aliases {
  16. ethernet0 = &enet0;
  17. ethernet1 = &enet1;
  18. ethernet2 = &enet2;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. pci1 = &pci1;
  23. pci2 = &pci2;
  24. };
  25. memory {
  26. device_type = "memory";
  27. };
  28. localbus@ffe05000 {
  29. compatible = "fsl,elbc", "simple-bus";
  30. ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
  31. 0x1 0x0 0x0 0xe0000000 0x08000000
  32. 0x2 0x0 0x0 0xffa00000 0x00040000
  33. 0x3 0x0 0x0 0xffdf0000 0x00008000
  34. 0x4 0x0 0x0 0xffa40000 0x00040000
  35. 0x5 0x0 0x0 0xffa80000 0x00040000
  36. 0x6 0x0 0x0 0xffac0000 0x00040000>;
  37. nor@0,0 {
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. compatible = "cfi-flash";
  41. reg = <0x0 0x0 0x8000000>;
  42. bank-width = <2>;
  43. device-width = <1>;
  44. ramdisk@0 {
  45. reg = <0x0 0x03000000>;
  46. read-only;
  47. };
  48. diagnostic@3000000 {
  49. reg = <0x03000000 0x00e00000>;
  50. read-only;
  51. };
  52. dink@3e00000 {
  53. reg = <0x03e00000 0x00200000>;
  54. read-only;
  55. };
  56. kernel@4000000 {
  57. reg = <0x04000000 0x00400000>;
  58. read-only;
  59. };
  60. jffs2@4400000 {
  61. reg = <0x04400000 0x03b00000>;
  62. };
  63. dtb@7f00000 {
  64. reg = <0x07f00000 0x00080000>;
  65. read-only;
  66. };
  67. u-boot@7f80000 {
  68. reg = <0x07f80000 0x00080000>;
  69. read-only;
  70. };
  71. };
  72. nand@2,0 {
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. compatible = "fsl,elbc-fcm-nand";
  76. reg = <0x2 0x0 0x40000>;
  77. u-boot@0 {
  78. reg = <0x0 0x02000000>;
  79. read-only;
  80. };
  81. jffs2@2000000 {
  82. reg = <0x02000000 0x10000000>;
  83. };
  84. ramdisk@12000000 {
  85. reg = <0x12000000 0x08000000>;
  86. read-only;
  87. };
  88. kernel@1a000000 {
  89. reg = <0x1a000000 0x04000000>;
  90. };
  91. dtb@1e000000 {
  92. reg = <0x1e000000 0x01000000>;
  93. read-only;
  94. };
  95. empty@1f000000 {
  96. reg = <0x1f000000 0x21000000>;
  97. };
  98. };
  99. board-control@3,0 {
  100. compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
  101. reg = <0x3 0x0 0x30>;
  102. };
  103. nand@4,0 {
  104. compatible = "fsl,elbc-fcm-nand";
  105. reg = <0x4 0x0 0x40000>;
  106. };
  107. nand@5,0 {
  108. compatible = "fsl,elbc-fcm-nand";
  109. reg = <0x5 0x0 0x40000>;
  110. };
  111. nand@6,0 {
  112. compatible = "fsl,elbc-fcm-nand";
  113. reg = <0x6 0x0 0x40000>;
  114. };
  115. };
  116. soc@ffe00000 {
  117. usb@22000 {
  118. phy_type = "ulpi";
  119. };
  120. mdio@24520 {
  121. phy0: ethernet-phy@0 {
  122. interrupt-parent = <&mpic>;
  123. interrupts = <3 1>;
  124. reg = <0x0>;
  125. };
  126. phy1: ethernet-phy@1 {
  127. interrupt-parent = <&mpic>;
  128. interrupts = <3 1>;
  129. reg = <0x1>;
  130. };
  131. phy2: ethernet-phy@2 {
  132. interrupt-parent = <&mpic>;
  133. interrupts = <3 1>;
  134. reg = <0x2>;
  135. };
  136. tbi0: tbi-phy@11 {
  137. reg = <0x11>;
  138. device_type = "tbi-phy";
  139. };
  140. };
  141. mdio@25520 {
  142. tbi1: tbi-phy@11 {
  143. reg = <0x11>;
  144. device_type = "tbi-phy";
  145. };
  146. };
  147. mdio@26520 {
  148. tbi2: tbi-phy@11 {
  149. reg = <0x11>;
  150. device_type = "tbi-phy";
  151. };
  152. };
  153. ptp_clock@24E00 {
  154. compatible = "fsl,etsec-ptp";
  155. reg = <0x24E00 0xB0>;
  156. interrupts = <68 2 69 2 70 2>;
  157. interrupt-parent = < &mpic >;
  158. fsl,tclk-period = <5>;
  159. fsl,tmr-prsc = <200>;
  160. fsl,tmr-add = <0xCCCCCCCD>;
  161. fsl,tmr-fiper1 = <0x3B9AC9FB>;
  162. fsl,tmr-fiper2 = <0x0001869B>;
  163. fsl,max-adj = <249999999>;
  164. };
  165. enet0: ethernet@24000 {
  166. tbi-handle = <&tbi0>;
  167. phy-handle = <&phy0>;
  168. phy-connection-type = "rgmii-id";
  169. };
  170. enet1: ethernet@25000 {
  171. tbi-handle = <&tbi1>;
  172. phy-handle = <&phy1>;
  173. phy-connection-type = "rgmii-id";
  174. };
  175. enet2: ethernet@26000 {
  176. tbi-handle = <&tbi2>;
  177. phy-handle = <&phy2>;
  178. phy-connection-type = "rgmii-id";
  179. };
  180. msi@41600 {
  181. compatible = "fsl,mpic-msi";
  182. };
  183. };
  184. pci0: pcie@ffe08000 {
  185. ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
  186. 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
  187. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  188. interrupt-map = <
  189. /* IDSEL 0x0 */
  190. 0000 0x0 0x0 0x1 &mpic 0x8 0x1
  191. 0000 0x0 0x0 0x2 &mpic 0x9 0x1
  192. 0000 0x0 0x0 0x3 &mpic 0xa 0x1
  193. 0000 0x0 0x0 0x4 &mpic 0xb 0x1
  194. >;
  195. pcie@0 {
  196. reg = <0x0 0x0 0x0 0x0 0x0>;
  197. #size-cells = <2>;
  198. #address-cells = <3>;
  199. device_type = "pci";
  200. ranges = <0x2000000 0x0 0x80000000
  201. 0x2000000 0x0 0x80000000
  202. 0x0 0x20000000
  203. 0x1000000 0x0 0x0
  204. 0x1000000 0x0 0x0
  205. 0x0 0x10000>;
  206. };
  207. };
  208. pci1: pcie@ffe09000 {
  209. ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
  210. 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
  211. interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
  212. interrupt-map = <
  213. // IDSEL 0x11 func 0 - PCI slot 1
  214. 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
  215. 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
  216. // IDSEL 0x11 func 1 - PCI slot 1
  217. 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
  218. 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
  219. // IDSEL 0x11 func 2 - PCI slot 1
  220. 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
  221. 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
  222. // IDSEL 0x11 func 3 - PCI slot 1
  223. 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
  224. 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
  225. // IDSEL 0x11 func 4 - PCI slot 1
  226. 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
  227. 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
  228. // IDSEL 0x11 func 5 - PCI slot 1
  229. 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
  230. 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
  231. // IDSEL 0x11 func 6 - PCI slot 1
  232. 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
  233. 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
  234. // IDSEL 0x11 func 7 - PCI slot 1
  235. 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
  236. 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
  237. // IDSEL 0x1d Audio
  238. 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
  239. // IDSEL 0x1e Legacy
  240. 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
  241. 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
  242. // IDSEL 0x1f IDE/SATA
  243. 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
  244. 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
  245. >;
  246. pcie@0 {
  247. reg = <0x0 0x0 0x0 0x0 0x0>;
  248. #size-cells = <2>;
  249. #address-cells = <3>;
  250. device_type = "pci";
  251. ranges = <0x2000000 0x0 0xa0000000
  252. 0x2000000 0x0 0xa0000000
  253. 0x0 0x20000000
  254. 0x1000000 0x0 0x0
  255. 0x1000000 0x0 0x0
  256. 0x0 0x10000>;
  257. uli1575@0 {
  258. reg = <0x0 0x0 0x0 0x0 0x0>;
  259. #size-cells = <2>;
  260. #address-cells = <3>;
  261. ranges = <0x2000000 0x0 0xa0000000
  262. 0x2000000 0x0 0xa0000000
  263. 0x0 0x20000000
  264. 0x1000000 0x0 0x0
  265. 0x1000000 0x0 0x0
  266. 0x0 0x10000>;
  267. isa@1e {
  268. device_type = "isa";
  269. #interrupt-cells = <2>;
  270. #size-cells = <1>;
  271. #address-cells = <2>;
  272. reg = <0xf000 0x0 0x0 0x0 0x0>;
  273. ranges = <0x1 0x0 0x1000000 0x0 0x0
  274. 0x1000>;
  275. interrupt-parent = <&i8259>;
  276. i8259: interrupt-controller@20 {
  277. reg = <0x1 0x20 0x2
  278. 0x1 0xa0 0x2
  279. 0x1 0x4d0 0x2>;
  280. interrupt-controller;
  281. device_type = "interrupt-controller";
  282. #address-cells = <0>;
  283. #interrupt-cells = <2>;
  284. compatible = "chrp,iic";
  285. interrupts = <4 1>;
  286. interrupt-parent = <&mpic>;
  287. };
  288. i8042@60 {
  289. #size-cells = <0>;
  290. #address-cells = <1>;
  291. reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
  292. interrupts = <1 3 12 3>;
  293. interrupt-parent =
  294. <&i8259>;
  295. keyboard@0 {
  296. reg = <0x0>;
  297. compatible = "pnpPNP,303";
  298. };
  299. mouse@1 {
  300. reg = <0x1>;
  301. compatible = "pnpPNP,f03";
  302. };
  303. };
  304. rtc@70 {
  305. compatible = "pnpPNP,b00";
  306. reg = <0x1 0x70 0x2>;
  307. };
  308. gpio@400 {
  309. reg = <0x1 0x400 0x80>;
  310. };
  311. };
  312. };
  313. };
  314. };
  315. pci2: pcie@ffe0a000 {
  316. ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
  317. 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
  318. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  319. interrupt-map = <
  320. /* IDSEL 0x0 */
  321. 0000 0x0 0x0 0x1 &mpic 0x0 0x1
  322. 0000 0x0 0x0 0x2 &mpic 0x1 0x1
  323. 0000 0x0 0x0 0x3 &mpic 0x2 0x1
  324. 0000 0x0 0x0 0x4 &mpic 0x3 0x1
  325. >;
  326. pcie@0 {
  327. reg = <0x0 0x0 0x0 0x0 0x0>;
  328. #size-cells = <2>;
  329. #address-cells = <3>;
  330. device_type = "pci";
  331. ranges = <0x2000000 0x0 0xc0000000
  332. 0x2000000 0x0 0xc0000000
  333. 0x0 0x20000000
  334. 0x1000000 0x0 0x0
  335. 0x1000000 0x0 0x0
  336. 0x0 0x10000>;
  337. };
  338. };
  339. };