platform.c 8.4 KB

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  1. /*
  2. * DBAu1xxx board platform device registration
  3. *
  4. * Copyright (C) 2009 Manuel Lauss
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/platform_device.h>
  24. #include <asm/mach-au1x00/au1000.h>
  25. #include <asm/mach-au1x00/au1000_dma.h>
  26. #include <asm/mach-db1x00/bcsr.h>
  27. #include "../platform.h"
  28. struct pci_dev;
  29. /* DB1xxx PCMCIA interrupt sources:
  30. * CD0/1 GPIO0/3
  31. * STSCHG0/1 GPIO1/4
  32. * CARD0/1 GPIO2/5
  33. * Db1550: 0/1, 21/22, 3/5
  34. */
  35. #define DB1XXX_HAS_PCMCIA
  36. #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
  37. #if defined(CONFIG_MIPS_DB1000)
  38. #define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
  39. #define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
  40. #define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
  41. #define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
  42. #define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
  43. #define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
  44. #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
  45. #define BOARD_FLASH_WIDTH 4 /* 32-bits */
  46. #elif defined(CONFIG_MIPS_DB1100)
  47. #define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
  48. #define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
  49. #define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
  50. #define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
  51. #define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
  52. #define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
  53. #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
  54. #define BOARD_FLASH_WIDTH 4 /* 32-bits */
  55. #elif defined(CONFIG_MIPS_DB1500)
  56. #define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
  57. #define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
  58. #define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
  59. #define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
  60. #define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
  61. #define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
  62. #define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
  63. #define BOARD_FLASH_WIDTH 4 /* 32-bits */
  64. #elif defined(CONFIG_MIPS_DB1550)
  65. #define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
  66. #define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
  67. #define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
  68. #define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
  69. #define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
  70. #define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
  71. #define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
  72. #define BOARD_FLASH_WIDTH 4 /* 32-bits */
  73. #else
  74. /* other board: no PCMCIA */
  75. #undef DB1XXX_HAS_PCMCIA
  76. #undef F_SWAPPED
  77. #define F_SWAPPED 0
  78. #if defined(CONFIG_MIPS_BOSPORUS)
  79. #define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
  80. #define BOARD_FLASH_WIDTH 2 /* 16-bits */
  81. #elif defined(CONFIG_MIPS_MIRAGE)
  82. #define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
  83. #define BOARD_FLASH_WIDTH 4 /* 32-bits */
  84. #endif
  85. #endif
  86. #ifdef CONFIG_PCI
  87. #ifdef CONFIG_MIPS_DB1500
  88. static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  89. {
  90. if ((slot < 12) || (slot > 13) || pin == 0)
  91. return -1;
  92. if (slot == 12)
  93. return (pin == 1) ? AU1500_PCI_INTA : 0xff;
  94. if (slot == 13) {
  95. switch (pin) {
  96. case 1: return AU1500_PCI_INTA;
  97. case 2: return AU1500_PCI_INTB;
  98. case 3: return AU1500_PCI_INTC;
  99. case 4: return AU1500_PCI_INTD;
  100. }
  101. }
  102. return -1;
  103. }
  104. #endif
  105. #ifdef CONFIG_MIPS_DB1550
  106. static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  107. {
  108. if ((slot < 11) || (slot > 13) || pin == 0)
  109. return -1;
  110. if (slot == 11)
  111. return (pin == 1) ? AU1550_PCI_INTC : 0xff;
  112. if (slot == 12) {
  113. switch (pin) {
  114. case 1: return AU1550_PCI_INTB;
  115. case 2: return AU1550_PCI_INTC;
  116. case 3: return AU1550_PCI_INTD;
  117. case 4: return AU1550_PCI_INTA;
  118. }
  119. }
  120. if (slot == 13) {
  121. switch (pin) {
  122. case 1: return AU1550_PCI_INTA;
  123. case 2: return AU1550_PCI_INTB;
  124. case 3: return AU1550_PCI_INTC;
  125. case 4: return AU1550_PCI_INTD;
  126. }
  127. }
  128. return -1;
  129. }
  130. #endif
  131. #ifdef CONFIG_MIPS_BOSPORUS
  132. static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  133. {
  134. if ((slot < 11) || (slot > 13) || pin == 0)
  135. return -1;
  136. if (slot == 12)
  137. return (pin == 1) ? AU1500_PCI_INTA : 0xff;
  138. if (slot == 11) {
  139. switch (pin) {
  140. case 1: return AU1500_PCI_INTA;
  141. case 2: return AU1500_PCI_INTB;
  142. default: return 0xff;
  143. }
  144. }
  145. if (slot == 13) {
  146. switch (pin) {
  147. case 1: return AU1500_PCI_INTA;
  148. case 2: return AU1500_PCI_INTB;
  149. case 3: return AU1500_PCI_INTC;
  150. case 4: return AU1500_PCI_INTD;
  151. }
  152. }
  153. return -1;
  154. }
  155. #endif
  156. #ifdef CONFIG_MIPS_MIRAGE
  157. static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  158. {
  159. if ((slot < 11) || (slot > 13) || pin == 0)
  160. return -1;
  161. if (slot == 11)
  162. return (pin == 1) ? AU1500_PCI_INTD : 0xff;
  163. if (slot == 12)
  164. return (pin == 3) ? AU1500_PCI_INTC : 0xff;
  165. if (slot == 13) {
  166. switch (pin) {
  167. case 1: return AU1500_PCI_INTA;
  168. case 2: return AU1500_PCI_INTB;
  169. default: return 0xff;
  170. }
  171. }
  172. return -1;
  173. }
  174. #endif
  175. static struct resource alchemy_pci_host_res[] = {
  176. [0] = {
  177. .start = AU1500_PCI_PHYS_ADDR,
  178. .end = AU1500_PCI_PHYS_ADDR + 0xfff,
  179. .flags = IORESOURCE_MEM,
  180. },
  181. };
  182. static struct alchemy_pci_platdata db1xxx_pci_pd = {
  183. .board_map_irq = db1xxx_map_pci_irq,
  184. };
  185. static struct platform_device db1xxx_pci_host_dev = {
  186. .dev.platform_data = &db1xxx_pci_pd,
  187. .name = "alchemy-pci",
  188. .id = 0,
  189. .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
  190. .resource = alchemy_pci_host_res,
  191. };
  192. static int __init db15x0_pci_init(void)
  193. {
  194. return platform_device_register(&db1xxx_pci_host_dev);
  195. }
  196. /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
  197. arch_initcall(db15x0_pci_init);
  198. #endif
  199. #ifdef CONFIG_MIPS_DB1100
  200. static struct resource au1100_lcd_resources[] = {
  201. [0] = {
  202. .start = AU1100_LCD_PHYS_ADDR,
  203. .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
  204. .flags = IORESOURCE_MEM,
  205. },
  206. [1] = {
  207. .start = AU1100_LCD_INT,
  208. .end = AU1100_LCD_INT,
  209. .flags = IORESOURCE_IRQ,
  210. }
  211. };
  212. static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
  213. static struct platform_device au1100_lcd_device = {
  214. .name = "au1100-lcd",
  215. .id = 0,
  216. .dev = {
  217. .dma_mask = &au1100_lcd_dmamask,
  218. .coherent_dma_mask = DMA_BIT_MASK(32),
  219. },
  220. .num_resources = ARRAY_SIZE(au1100_lcd_resources),
  221. .resource = au1100_lcd_resources,
  222. };
  223. #endif
  224. static struct resource alchemy_ac97c_res[] = {
  225. [0] = {
  226. .start = AU1000_AC97_PHYS_ADDR,
  227. .end = AU1000_AC97_PHYS_ADDR + 0xfff,
  228. .flags = IORESOURCE_MEM,
  229. },
  230. [1] = {
  231. .start = DMA_ID_AC97C_TX,
  232. .end = DMA_ID_AC97C_TX,
  233. .flags = IORESOURCE_DMA,
  234. },
  235. [2] = {
  236. .start = DMA_ID_AC97C_RX,
  237. .end = DMA_ID_AC97C_RX,
  238. .flags = IORESOURCE_DMA,
  239. },
  240. };
  241. static struct platform_device alchemy_ac97c_dev = {
  242. .name = "alchemy-ac97c",
  243. .id = -1,
  244. .resource = alchemy_ac97c_res,
  245. .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
  246. };
  247. static struct platform_device alchemy_ac97c_dma_dev = {
  248. .name = "alchemy-pcm-dma",
  249. .id = 0,
  250. };
  251. static struct platform_device db1x00_codec_dev = {
  252. .name = "ac97-codec",
  253. .id = -1,
  254. };
  255. static struct platform_device db1x00_audio_dev = {
  256. .name = "db1000-audio",
  257. };
  258. static int __init db1xxx_dev_init(void)
  259. {
  260. #ifdef DB1XXX_HAS_PCMCIA
  261. db1x_register_pcmcia_socket(
  262. AU1000_PCMCIA_ATTR_PHYS_ADDR,
  263. AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
  264. AU1000_PCMCIA_MEM_PHYS_ADDR,
  265. AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
  266. AU1000_PCMCIA_IO_PHYS_ADDR,
  267. AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
  268. DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
  269. /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
  270. db1x_register_pcmcia_socket(
  271. AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
  272. AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
  273. AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
  274. AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
  275. AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
  276. AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
  277. DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
  278. /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
  279. #endif
  280. #ifdef CONFIG_MIPS_DB1100
  281. platform_device_register(&au1100_lcd_device);
  282. #endif
  283. db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
  284. platform_device_register(&db1x00_codec_dev);
  285. platform_device_register(&alchemy_ac97c_dma_dev);
  286. platform_device_register(&alchemy_ac97c_dev);
  287. platform_device_register(&db1x00_audio_dev);
  288. return 0;
  289. }
  290. device_initcall(db1xxx_dev_init);