ezkit.c 22 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2
  7. */
  8. #include <linux/device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/mtd/mtd.h>
  11. #include <linux/mtd/physmap.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #include <linux/irq.h>
  16. #include <linux/interrupt.h>
  17. #include <asm/bfin5xx_spi.h>
  18. #include <asm/dma.h>
  19. #include <asm/gpio.h>
  20. #include <asm/nand.h>
  21. #include <asm/portmux.h>
  22. #include <asm/dpmc.h>
  23. #include <linux/input.h>
  24. /*
  25. * Name the Board for the /proc/cpuinfo
  26. */
  27. const char bfin_board_name[] = "ADI BF538-EZKIT";
  28. /*
  29. * Driver needs to know address, irq and flag pin.
  30. */
  31. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  32. static struct platform_device rtc_device = {
  33. .name = "rtc-bfin",
  34. .id = -1,
  35. };
  36. #endif
  37. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  38. #ifdef CONFIG_SERIAL_BFIN_UART0
  39. static struct resource bfin_uart0_resources[] = {
  40. {
  41. .start = UART0_THR,
  42. .end = UART0_GCTL+2,
  43. .flags = IORESOURCE_MEM,
  44. },
  45. {
  46. .start = IRQ_UART0_RX,
  47. .end = IRQ_UART0_RX+1,
  48. .flags = IORESOURCE_IRQ,
  49. },
  50. {
  51. .start = IRQ_UART0_ERROR,
  52. .end = IRQ_UART0_ERROR,
  53. .flags = IORESOURCE_IRQ,
  54. },
  55. {
  56. .start = CH_UART0_TX,
  57. .end = CH_UART0_TX,
  58. .flags = IORESOURCE_DMA,
  59. },
  60. {
  61. .start = CH_UART0_RX,
  62. .end = CH_UART0_RX,
  63. .flags = IORESOURCE_DMA,
  64. },
  65. #ifdef CONFIG_BFIN_UART0_CTSRTS
  66. { /* CTS pin */
  67. .start = GPIO_PG7,
  68. .end = GPIO_PG7,
  69. .flags = IORESOURCE_IO,
  70. },
  71. { /* RTS pin */
  72. .start = GPIO_PG6,
  73. .end = GPIO_PG6,
  74. .flags = IORESOURCE_IO,
  75. },
  76. #endif
  77. };
  78. static unsigned short bfin_uart0_peripherals[] = {
  79. P_UART0_TX, P_UART0_RX, 0
  80. };
  81. static struct platform_device bfin_uart0_device = {
  82. .name = "bfin-uart",
  83. .id = 0,
  84. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  85. .resource = bfin_uart0_resources,
  86. .dev = {
  87. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  88. },
  89. };
  90. #endif
  91. #ifdef CONFIG_SERIAL_BFIN_UART1
  92. static struct resource bfin_uart1_resources[] = {
  93. {
  94. .start = UART1_THR,
  95. .end = UART1_GCTL+2,
  96. .flags = IORESOURCE_MEM,
  97. },
  98. {
  99. .start = IRQ_UART1_RX,
  100. .end = IRQ_UART1_RX+1,
  101. .flags = IORESOURCE_IRQ,
  102. },
  103. {
  104. .start = IRQ_UART1_ERROR,
  105. .end = IRQ_UART1_ERROR,
  106. .flags = IORESOURCE_IRQ,
  107. },
  108. {
  109. .start = CH_UART1_TX,
  110. .end = CH_UART1_TX,
  111. .flags = IORESOURCE_DMA,
  112. },
  113. {
  114. .start = CH_UART1_RX,
  115. .end = CH_UART1_RX,
  116. .flags = IORESOURCE_DMA,
  117. },
  118. };
  119. static unsigned short bfin_uart1_peripherals[] = {
  120. P_UART1_TX, P_UART1_RX, 0
  121. };
  122. static struct platform_device bfin_uart1_device = {
  123. .name = "bfin-uart",
  124. .id = 1,
  125. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  126. .resource = bfin_uart1_resources,
  127. .dev = {
  128. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  129. },
  130. };
  131. #endif
  132. #ifdef CONFIG_SERIAL_BFIN_UART2
  133. static struct resource bfin_uart2_resources[] = {
  134. {
  135. .start = UART2_THR,
  136. .end = UART2_GCTL+2,
  137. .flags = IORESOURCE_MEM,
  138. },
  139. {
  140. .start = IRQ_UART2_RX,
  141. .end = IRQ_UART2_RX+1,
  142. .flags = IORESOURCE_IRQ,
  143. },
  144. {
  145. .start = IRQ_UART2_ERROR,
  146. .end = IRQ_UART2_ERROR,
  147. .flags = IORESOURCE_IRQ,
  148. },
  149. {
  150. .start = CH_UART2_TX,
  151. .end = CH_UART2_TX,
  152. .flags = IORESOURCE_DMA,
  153. },
  154. {
  155. .start = CH_UART2_RX,
  156. .end = CH_UART2_RX,
  157. .flags = IORESOURCE_DMA,
  158. },
  159. };
  160. static unsigned short bfin_uart2_peripherals[] = {
  161. P_UART2_TX, P_UART2_RX, 0
  162. };
  163. static struct platform_device bfin_uart2_device = {
  164. .name = "bfin-uart",
  165. .id = 2,
  166. .num_resources = ARRAY_SIZE(bfin_uart2_resources),
  167. .resource = bfin_uart2_resources,
  168. .dev = {
  169. .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
  170. },
  171. };
  172. #endif
  173. #endif
  174. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  175. #ifdef CONFIG_BFIN_SIR0
  176. static struct resource bfin_sir0_resources[] = {
  177. {
  178. .start = 0xFFC00400,
  179. .end = 0xFFC004FF,
  180. .flags = IORESOURCE_MEM,
  181. },
  182. {
  183. .start = IRQ_UART0_RX,
  184. .end = IRQ_UART0_RX+1,
  185. .flags = IORESOURCE_IRQ,
  186. },
  187. {
  188. .start = CH_UART0_RX,
  189. .end = CH_UART0_RX+1,
  190. .flags = IORESOURCE_DMA,
  191. },
  192. };
  193. static struct platform_device bfin_sir0_device = {
  194. .name = "bfin_sir",
  195. .id = 0,
  196. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  197. .resource = bfin_sir0_resources,
  198. };
  199. #endif
  200. #ifdef CONFIG_BFIN_SIR1
  201. static struct resource bfin_sir1_resources[] = {
  202. {
  203. .start = 0xFFC02000,
  204. .end = 0xFFC020FF,
  205. .flags = IORESOURCE_MEM,
  206. },
  207. {
  208. .start = IRQ_UART1_RX,
  209. .end = IRQ_UART1_RX+1,
  210. .flags = IORESOURCE_IRQ,
  211. },
  212. {
  213. .start = CH_UART1_RX,
  214. .end = CH_UART1_RX+1,
  215. .flags = IORESOURCE_DMA,
  216. },
  217. };
  218. static struct platform_device bfin_sir1_device = {
  219. .name = "bfin_sir",
  220. .id = 1,
  221. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  222. .resource = bfin_sir1_resources,
  223. };
  224. #endif
  225. #ifdef CONFIG_BFIN_SIR2
  226. static struct resource bfin_sir2_resources[] = {
  227. {
  228. .start = 0xFFC02100,
  229. .end = 0xFFC021FF,
  230. .flags = IORESOURCE_MEM,
  231. },
  232. {
  233. .start = IRQ_UART2_RX,
  234. .end = IRQ_UART2_RX+1,
  235. .flags = IORESOURCE_IRQ,
  236. },
  237. {
  238. .start = CH_UART2_RX,
  239. .end = CH_UART2_RX+1,
  240. .flags = IORESOURCE_DMA,
  241. },
  242. };
  243. static struct platform_device bfin_sir2_device = {
  244. .name = "bfin_sir",
  245. .id = 2,
  246. .num_resources = ARRAY_SIZE(bfin_sir2_resources),
  247. .resource = bfin_sir2_resources,
  248. };
  249. #endif
  250. #endif
  251. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  252. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  253. static struct resource bfin_sport0_uart_resources[] = {
  254. {
  255. .start = SPORT0_TCR1,
  256. .end = SPORT0_MRCS3+4,
  257. .flags = IORESOURCE_MEM,
  258. },
  259. {
  260. .start = IRQ_SPORT0_RX,
  261. .end = IRQ_SPORT0_RX+1,
  262. .flags = IORESOURCE_IRQ,
  263. },
  264. {
  265. .start = IRQ_SPORT0_ERROR,
  266. .end = IRQ_SPORT0_ERROR,
  267. .flags = IORESOURCE_IRQ,
  268. },
  269. };
  270. static unsigned short bfin_sport0_peripherals[] = {
  271. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  272. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  273. };
  274. static struct platform_device bfin_sport0_uart_device = {
  275. .name = "bfin-sport-uart",
  276. .id = 0,
  277. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  278. .resource = bfin_sport0_uart_resources,
  279. .dev = {
  280. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  281. },
  282. };
  283. #endif
  284. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  285. static struct resource bfin_sport1_uart_resources[] = {
  286. {
  287. .start = SPORT1_TCR1,
  288. .end = SPORT1_MRCS3+4,
  289. .flags = IORESOURCE_MEM,
  290. },
  291. {
  292. .start = IRQ_SPORT1_RX,
  293. .end = IRQ_SPORT1_RX+1,
  294. .flags = IORESOURCE_IRQ,
  295. },
  296. {
  297. .start = IRQ_SPORT1_ERROR,
  298. .end = IRQ_SPORT1_ERROR,
  299. .flags = IORESOURCE_IRQ,
  300. },
  301. };
  302. static unsigned short bfin_sport1_peripherals[] = {
  303. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  304. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  305. };
  306. static struct platform_device bfin_sport1_uart_device = {
  307. .name = "bfin-sport-uart",
  308. .id = 1,
  309. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  310. .resource = bfin_sport1_uart_resources,
  311. .dev = {
  312. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  313. },
  314. };
  315. #endif
  316. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  317. static struct resource bfin_sport2_uart_resources[] = {
  318. {
  319. .start = SPORT2_TCR1,
  320. .end = SPORT2_MRCS3+4,
  321. .flags = IORESOURCE_MEM,
  322. },
  323. {
  324. .start = IRQ_SPORT2_RX,
  325. .end = IRQ_SPORT2_RX+1,
  326. .flags = IORESOURCE_IRQ,
  327. },
  328. {
  329. .start = IRQ_SPORT2_ERROR,
  330. .end = IRQ_SPORT2_ERROR,
  331. .flags = IORESOURCE_IRQ,
  332. },
  333. };
  334. static unsigned short bfin_sport2_peripherals[] = {
  335. P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
  336. P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
  337. };
  338. static struct platform_device bfin_sport2_uart_device = {
  339. .name = "bfin-sport-uart",
  340. .id = 2,
  341. .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
  342. .resource = bfin_sport2_uart_resources,
  343. .dev = {
  344. .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
  345. },
  346. };
  347. #endif
  348. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  349. static struct resource bfin_sport3_uart_resources[] = {
  350. {
  351. .start = SPORT3_TCR1,
  352. .end = SPORT3_MRCS3+4,
  353. .flags = IORESOURCE_MEM,
  354. },
  355. {
  356. .start = IRQ_SPORT3_RX,
  357. .end = IRQ_SPORT3_RX+1,
  358. .flags = IORESOURCE_IRQ,
  359. },
  360. {
  361. .start = IRQ_SPORT3_ERROR,
  362. .end = IRQ_SPORT3_ERROR,
  363. .flags = IORESOURCE_IRQ,
  364. },
  365. };
  366. static unsigned short bfin_sport3_peripherals[] = {
  367. P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
  368. P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
  369. };
  370. static struct platform_device bfin_sport3_uart_device = {
  371. .name = "bfin-sport-uart",
  372. .id = 3,
  373. .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
  374. .resource = bfin_sport3_uart_resources,
  375. .dev = {
  376. .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
  377. },
  378. };
  379. #endif
  380. #endif
  381. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  382. static unsigned short bfin_can_peripherals[] = {
  383. P_CAN0_RX, P_CAN0_TX, 0
  384. };
  385. static struct resource bfin_can_resources[] = {
  386. {
  387. .start = 0xFFC02A00,
  388. .end = 0xFFC02FFF,
  389. .flags = IORESOURCE_MEM,
  390. },
  391. {
  392. .start = IRQ_CAN_RX,
  393. .end = IRQ_CAN_RX,
  394. .flags = IORESOURCE_IRQ,
  395. },
  396. {
  397. .start = IRQ_CAN_TX,
  398. .end = IRQ_CAN_TX,
  399. .flags = IORESOURCE_IRQ,
  400. },
  401. {
  402. .start = IRQ_CAN_ERROR,
  403. .end = IRQ_CAN_ERROR,
  404. .flags = IORESOURCE_IRQ,
  405. },
  406. };
  407. static struct platform_device bfin_can_device = {
  408. .name = "bfin_can",
  409. .num_resources = ARRAY_SIZE(bfin_can_resources),
  410. .resource = bfin_can_resources,
  411. .dev = {
  412. .platform_data = &bfin_can_peripherals, /* Passed to driver */
  413. },
  414. };
  415. #endif
  416. /*
  417. * USB-LAN EzExtender board
  418. * Driver needs to know address, irq and flag pin.
  419. */
  420. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  421. #include <linux/smc91x.h>
  422. static struct smc91x_platdata smc91x_info = {
  423. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  424. .leda = RPC_LED_100_10,
  425. .ledb = RPC_LED_TX_RX,
  426. };
  427. static struct resource smc91x_resources[] = {
  428. {
  429. .name = "smc91x-regs",
  430. .start = 0x20310300,
  431. .end = 0x20310300 + 16,
  432. .flags = IORESOURCE_MEM,
  433. }, {
  434. .start = IRQ_PF0,
  435. .end = IRQ_PF0,
  436. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  437. },
  438. };
  439. static struct platform_device smc91x_device = {
  440. .name = "smc91x",
  441. .id = 0,
  442. .num_resources = ARRAY_SIZE(smc91x_resources),
  443. .resource = smc91x_resources,
  444. .dev = {
  445. .platform_data = &smc91x_info,
  446. },
  447. };
  448. #endif
  449. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  450. /* all SPI peripherals info goes here */
  451. #if defined(CONFIG_MTD_M25P80) \
  452. || defined(CONFIG_MTD_M25P80_MODULE)
  453. /* SPI flash chip (m25p16) */
  454. static struct mtd_partition bfin_spi_flash_partitions[] = {
  455. {
  456. .name = "bootloader(spi)",
  457. .size = 0x00040000,
  458. .offset = 0,
  459. .mask_flags = MTD_CAP_ROM
  460. }, {
  461. .name = "linux kernel(spi)",
  462. .size = 0x1c0000,
  463. .offset = 0x40000
  464. }
  465. };
  466. static struct flash_platform_data bfin_spi_flash_data = {
  467. .name = "m25p80",
  468. .parts = bfin_spi_flash_partitions,
  469. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  470. .type = "m25p16",
  471. };
  472. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  473. .enable_dma = 0, /* use dma transfer with this chip*/
  474. };
  475. #endif
  476. #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
  477. #include <linux/spi/ad7879.h>
  478. static const struct ad7879_platform_data bfin_ad7879_ts_info = {
  479. .model = 7879, /* Model = AD7879 */
  480. .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
  481. .pressure_max = 10000,
  482. .pressure_min = 0,
  483. .first_conversion_delay = 3, /* wait 512us before do a first conversion */
  484. .acquisition_time = 1, /* 4us acquisition time per sample */
  485. .median = 2, /* do 8 measurements */
  486. .averaging = 1, /* take the average of 4 middle samples */
  487. .pen_down_acc_interval = 255, /* 9.4 ms */
  488. .gpio_export = 1, /* Export GPIO to gpiolib */
  489. .gpio_base = -1, /* Dynamic allocation */
  490. };
  491. #endif
  492. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  493. #include <asm/bfin-lq035q1.h>
  494. static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
  495. .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
  496. .ppi_mode = USE_RGB565_16_BIT_PPI,
  497. .use_bl = 0, /* let something else control the LCD Blacklight */
  498. .gpio_bl = GPIO_PF7,
  499. };
  500. static struct resource bfin_lq035q1_resources[] = {
  501. {
  502. .start = IRQ_PPI_ERROR,
  503. .end = IRQ_PPI_ERROR,
  504. .flags = IORESOURCE_IRQ,
  505. },
  506. };
  507. static struct platform_device bfin_lq035q1_device = {
  508. .name = "bfin-lq035q1",
  509. .id = -1,
  510. .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
  511. .resource = bfin_lq035q1_resources,
  512. .dev = {
  513. .platform_data = &bfin_lq035q1_data,
  514. },
  515. };
  516. #endif
  517. static struct spi_board_info bf538_spi_board_info[] __initdata = {
  518. #if defined(CONFIG_MTD_M25P80) \
  519. || defined(CONFIG_MTD_M25P80_MODULE)
  520. {
  521. /* the modalias must be the same as spi device driver name */
  522. .modalias = "m25p80", /* Name of spi_driver for this device */
  523. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  524. .bus_num = 0, /* Framework bus number */
  525. .chip_select = 1, /* SPI_SSEL1*/
  526. .platform_data = &bfin_spi_flash_data,
  527. .controller_data = &spi_flash_chip_info,
  528. .mode = SPI_MODE_3,
  529. },
  530. #endif
  531. #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
  532. {
  533. .modalias = "ad7879",
  534. .platform_data = &bfin_ad7879_ts_info,
  535. .irq = IRQ_PF3,
  536. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  537. .bus_num = 0,
  538. .chip_select = 1,
  539. .mode = SPI_CPHA | SPI_CPOL,
  540. },
  541. #endif
  542. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  543. {
  544. .modalias = "bfin-lq035q1-spi",
  545. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  546. .bus_num = 0,
  547. .chip_select = 2,
  548. .mode = SPI_CPHA | SPI_CPOL,
  549. },
  550. #endif
  551. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  552. {
  553. .modalias = "spidev",
  554. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  555. .bus_num = 0,
  556. .chip_select = 1,
  557. },
  558. #endif
  559. };
  560. /* SPI (0) */
  561. static struct resource bfin_spi0_resource[] = {
  562. [0] = {
  563. .start = SPI0_REGBASE,
  564. .end = SPI0_REGBASE + 0xFF,
  565. .flags = IORESOURCE_MEM,
  566. },
  567. [1] = {
  568. .start = CH_SPI0,
  569. .end = CH_SPI0,
  570. .flags = IORESOURCE_DMA,
  571. },
  572. [2] = {
  573. .start = IRQ_SPI0,
  574. .end = IRQ_SPI0,
  575. .flags = IORESOURCE_IRQ,
  576. }
  577. };
  578. /* SPI (1) */
  579. static struct resource bfin_spi1_resource[] = {
  580. [0] = {
  581. .start = SPI1_REGBASE,
  582. .end = SPI1_REGBASE + 0xFF,
  583. .flags = IORESOURCE_MEM,
  584. },
  585. [1] = {
  586. .start = CH_SPI1,
  587. .end = CH_SPI1,
  588. .flags = IORESOURCE_DMA,
  589. },
  590. [2] = {
  591. .start = IRQ_SPI1,
  592. .end = IRQ_SPI1,
  593. .flags = IORESOURCE_IRQ,
  594. }
  595. };
  596. /* SPI (2) */
  597. static struct resource bfin_spi2_resource[] = {
  598. [0] = {
  599. .start = SPI2_REGBASE,
  600. .end = SPI2_REGBASE + 0xFF,
  601. .flags = IORESOURCE_MEM,
  602. },
  603. [1] = {
  604. .start = CH_SPI2,
  605. .end = CH_SPI2,
  606. .flags = IORESOURCE_DMA,
  607. },
  608. [2] = {
  609. .start = IRQ_SPI2,
  610. .end = IRQ_SPI2,
  611. .flags = IORESOURCE_IRQ,
  612. }
  613. };
  614. /* SPI controller data */
  615. static struct bfin5xx_spi_master bf538_spi_master_info0 = {
  616. .num_chipselect = 8,
  617. .enable_dma = 1, /* master has the ability to do dma transfer */
  618. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  619. };
  620. static struct platform_device bf538_spi_master0 = {
  621. .name = "bfin-spi",
  622. .id = 0, /* Bus number */
  623. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  624. .resource = bfin_spi0_resource,
  625. .dev = {
  626. .platform_data = &bf538_spi_master_info0, /* Passed to driver */
  627. },
  628. };
  629. static struct bfin5xx_spi_master bf538_spi_master_info1 = {
  630. .num_chipselect = 2,
  631. .enable_dma = 1, /* master has the ability to do dma transfer */
  632. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  633. };
  634. static struct platform_device bf538_spi_master1 = {
  635. .name = "bfin-spi",
  636. .id = 1, /* Bus number */
  637. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  638. .resource = bfin_spi1_resource,
  639. .dev = {
  640. .platform_data = &bf538_spi_master_info1, /* Passed to driver */
  641. },
  642. };
  643. static struct bfin5xx_spi_master bf538_spi_master_info2 = {
  644. .num_chipselect = 2,
  645. .enable_dma = 1, /* master has the ability to do dma transfer */
  646. .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
  647. };
  648. static struct platform_device bf538_spi_master2 = {
  649. .name = "bfin-spi",
  650. .id = 2, /* Bus number */
  651. .num_resources = ARRAY_SIZE(bfin_spi2_resource),
  652. .resource = bfin_spi2_resource,
  653. .dev = {
  654. .platform_data = &bf538_spi_master_info2, /* Passed to driver */
  655. },
  656. };
  657. #endif /* spi master and devices */
  658. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  659. static struct resource bfin_twi0_resource[] = {
  660. [0] = {
  661. .start = TWI0_REGBASE,
  662. .end = TWI0_REGBASE + 0xFF,
  663. .flags = IORESOURCE_MEM,
  664. },
  665. [1] = {
  666. .start = IRQ_TWI0,
  667. .end = IRQ_TWI0,
  668. .flags = IORESOURCE_IRQ,
  669. },
  670. };
  671. static struct platform_device i2c_bfin_twi0_device = {
  672. .name = "i2c-bfin-twi",
  673. .id = 0,
  674. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  675. .resource = bfin_twi0_resource,
  676. };
  677. #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
  678. static struct resource bfin_twi1_resource[] = {
  679. [0] = {
  680. .start = TWI1_REGBASE,
  681. .end = TWI1_REGBASE + 0xFF,
  682. .flags = IORESOURCE_MEM,
  683. },
  684. [1] = {
  685. .start = IRQ_TWI1,
  686. .end = IRQ_TWI1,
  687. .flags = IORESOURCE_IRQ,
  688. },
  689. };
  690. static struct platform_device i2c_bfin_twi1_device = {
  691. .name = "i2c-bfin-twi",
  692. .id = 1,
  693. .num_resources = ARRAY_SIZE(bfin_twi1_resource),
  694. .resource = bfin_twi1_resource,
  695. };
  696. #endif
  697. #endif
  698. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  699. #include <linux/gpio_keys.h>
  700. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  701. {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
  702. };
  703. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  704. .buttons = bfin_gpio_keys_table,
  705. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  706. };
  707. static struct platform_device bfin_device_gpiokeys = {
  708. .name = "gpio-keys",
  709. .dev = {
  710. .platform_data = &bfin_gpio_keys_data,
  711. },
  712. };
  713. #endif
  714. static const unsigned int cclk_vlev_datasheet[] =
  715. {
  716. /*
  717. * Internal VLEV BF538SBBC1533
  718. ****temporarily using these values until data sheet is updated
  719. */
  720. VRPAIR(VLEV_100, 150000000),
  721. VRPAIR(VLEV_100, 250000000),
  722. VRPAIR(VLEV_110, 276000000),
  723. VRPAIR(VLEV_115, 301000000),
  724. VRPAIR(VLEV_120, 525000000),
  725. VRPAIR(VLEV_125, 550000000),
  726. VRPAIR(VLEV_130, 600000000),
  727. };
  728. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  729. .tuple_tab = cclk_vlev_datasheet,
  730. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  731. .vr_settling_time = 25 /* us */,
  732. };
  733. static struct platform_device bfin_dpmc = {
  734. .name = "bfin dpmc",
  735. .dev = {
  736. .platform_data = &bfin_dmpc_vreg_data,
  737. },
  738. };
  739. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  740. static struct mtd_partition ezkit_partitions[] = {
  741. {
  742. .name = "bootloader(nor)",
  743. .size = 0x40000,
  744. .offset = 0,
  745. }, {
  746. .name = "linux kernel(nor)",
  747. .size = 0x180000,
  748. .offset = MTDPART_OFS_APPEND,
  749. }, {
  750. .name = "file system(nor)",
  751. .size = MTDPART_SIZ_FULL,
  752. .offset = MTDPART_OFS_APPEND,
  753. }
  754. };
  755. static struct physmap_flash_data ezkit_flash_data = {
  756. .width = 2,
  757. .parts = ezkit_partitions,
  758. .nr_parts = ARRAY_SIZE(ezkit_partitions),
  759. };
  760. static struct resource ezkit_flash_resource = {
  761. .start = 0x20000000,
  762. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  763. .end = 0x202fffff,
  764. #else
  765. .end = 0x203fffff,
  766. #endif
  767. .flags = IORESOURCE_MEM,
  768. };
  769. static struct platform_device ezkit_flash_device = {
  770. .name = "physmap-flash",
  771. .id = 0,
  772. .dev = {
  773. .platform_data = &ezkit_flash_data,
  774. },
  775. .num_resources = 1,
  776. .resource = &ezkit_flash_resource,
  777. };
  778. #endif
  779. static struct platform_device *cm_bf538_devices[] __initdata = {
  780. &bfin_dpmc,
  781. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  782. &rtc_device,
  783. #endif
  784. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  785. #ifdef CONFIG_SERIAL_BFIN_UART0
  786. &bfin_uart0_device,
  787. #endif
  788. #ifdef CONFIG_SERIAL_BFIN_UART1
  789. &bfin_uart1_device,
  790. #endif
  791. #ifdef CONFIG_SERIAL_BFIN_UART2
  792. &bfin_uart2_device,
  793. #endif
  794. #endif
  795. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  796. &bf538_spi_master0,
  797. &bf538_spi_master1,
  798. &bf538_spi_master2,
  799. #endif
  800. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  801. &i2c_bfin_twi0_device,
  802. &i2c_bfin_twi1_device,
  803. #endif
  804. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  805. #ifdef CONFIG_BFIN_SIR0
  806. &bfin_sir0_device,
  807. #endif
  808. #ifdef CONFIG_BFIN_SIR1
  809. &bfin_sir1_device,
  810. #endif
  811. #ifdef CONFIG_BFIN_SIR2
  812. &bfin_sir2_device,
  813. #endif
  814. #endif
  815. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  816. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  817. &bfin_sport0_uart_device,
  818. #endif
  819. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  820. &bfin_sport1_uart_device,
  821. #endif
  822. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  823. &bfin_sport2_uart_device,
  824. #endif
  825. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  826. &bfin_sport3_uart_device,
  827. #endif
  828. #endif
  829. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  830. &bfin_can_device,
  831. #endif
  832. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  833. &smc91x_device,
  834. #endif
  835. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  836. &bfin_lq035q1_device,
  837. #endif
  838. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  839. &bfin_device_gpiokeys,
  840. #endif
  841. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  842. &ezkit_flash_device,
  843. #endif
  844. };
  845. static int __init ezkit_init(void)
  846. {
  847. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  848. platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
  849. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  850. spi_register_board_info(bf538_spi_board_info,
  851. ARRAY_SIZE(bf538_spi_board_info));
  852. #endif
  853. return 0;
  854. }
  855. arch_initcall(ezkit_init);
  856. static struct platform_device *ezkit_early_devices[] __initdata = {
  857. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  858. #ifdef CONFIG_SERIAL_BFIN_UART0
  859. &bfin_uart0_device,
  860. #endif
  861. #ifdef CONFIG_SERIAL_BFIN_UART1
  862. &bfin_uart1_device,
  863. #endif
  864. #ifdef CONFIG_SERIAL_BFIN_UART2
  865. &bfin_uart2_device,
  866. #endif
  867. #endif
  868. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  869. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  870. &bfin_sport0_uart_device,
  871. #endif
  872. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  873. &bfin_sport1_uart_device,
  874. #endif
  875. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  876. &bfin_sport2_uart_device,
  877. #endif
  878. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  879. &bfin_sport3_uart_device,
  880. #endif
  881. #endif
  882. };
  883. void __init native_machine_early_platform_add_devices(void)
  884. {
  885. printk(KERN_INFO "register early platform devices\n");
  886. early_platform_add_devices(ezkit_early_devices,
  887. ARRAY_SIZE(ezkit_early_devices));
  888. }