topology.h 3.1 KB

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  1. /*
  2. * Copyright (C) 2002, Erich Focht, NEC
  3. *
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #ifndef _ASM_IA64_TOPOLOGY_H
  12. #define _ASM_IA64_TOPOLOGY_H
  13. #include <asm/acpi.h>
  14. #include <asm/numa.h>
  15. #include <asm/smp.h>
  16. #ifdef CONFIG_NUMA
  17. /* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
  18. #define PENALTY_FOR_NODE_WITH_CPUS 255
  19. /*
  20. * Distance above which we begin to use zone reclaim
  21. */
  22. #define RECLAIM_DISTANCE 15
  23. /*
  24. * Returns the number of the node containing CPU 'cpu'
  25. */
  26. #define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
  27. /*
  28. * Returns a bitmask of CPUs on Node 'node'.
  29. */
  30. #define node_to_cpumask(node) (node_to_cpu_mask[node])
  31. /*
  32. * Returns the number of the node containing Node 'nid'.
  33. * Not implemented here. Multi-level hierarchies detected with
  34. * the help of node_distance().
  35. */
  36. #define parent_node(nid) (nid)
  37. /*
  38. * Returns the number of the first CPU on Node 'node'.
  39. */
  40. #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
  41. /*
  42. * Determines the node for a given pci bus
  43. */
  44. #define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
  45. void build_cpu_to_node_map(void);
  46. #define SD_CPU_INIT (struct sched_domain) { \
  47. .parent = NULL, \
  48. .child = NULL, \
  49. .groups = NULL, \
  50. .min_interval = 1, \
  51. .max_interval = 4, \
  52. .busy_factor = 64, \
  53. .imbalance_pct = 125, \
  54. .cache_nice_tries = 2, \
  55. .busy_idx = 2, \
  56. .idle_idx = 1, \
  57. .newidle_idx = 2, \
  58. .wake_idx = 1, \
  59. .forkexec_idx = 1, \
  60. .flags = SD_LOAD_BALANCE \
  61. | SD_BALANCE_NEWIDLE \
  62. | SD_BALANCE_EXEC \
  63. | SD_WAKE_AFFINE, \
  64. .last_balance = jiffies, \
  65. .balance_interval = 1, \
  66. .nr_balance_failed = 0, \
  67. }
  68. /* sched_domains SD_NODE_INIT for IA64 NUMA machines */
  69. #define SD_NODE_INIT (struct sched_domain) { \
  70. .parent = NULL, \
  71. .child = NULL, \
  72. .groups = NULL, \
  73. .min_interval = 8, \
  74. .max_interval = 8*(min(num_online_cpus(), 32)), \
  75. .busy_factor = 64, \
  76. .imbalance_pct = 125, \
  77. .cache_nice_tries = 2, \
  78. .busy_idx = 3, \
  79. .idle_idx = 2, \
  80. .newidle_idx = 2, \
  81. .wake_idx = 1, \
  82. .forkexec_idx = 1, \
  83. .flags = SD_LOAD_BALANCE \
  84. | SD_BALANCE_EXEC \
  85. | SD_BALANCE_FORK \
  86. | SD_SERIALIZE \
  87. | SD_WAKE_BALANCE, \
  88. .last_balance = jiffies, \
  89. .balance_interval = 64, \
  90. .nr_balance_failed = 0, \
  91. }
  92. #endif /* CONFIG_NUMA */
  93. #ifdef CONFIG_SMP
  94. #define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
  95. #define topology_core_id(cpu) (cpu_data(cpu)->core_id)
  96. #define topology_core_siblings(cpu) (cpu_core_map[cpu])
  97. #define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
  98. #define smt_capable() (smp_num_siblings > 1)
  99. #endif
  100. extern void arch_fix_phys_package_id(int num, u32 slot);
  101. #define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
  102. CPU_MASK_ALL : \
  103. node_to_cpumask(pcibus_to_node(bus)) \
  104. )
  105. #include <asm-generic/topology.h>
  106. #endif /* _ASM_IA64_TOPOLOGY_H */