clock.c 12 KB

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  1. /*
  2. * Clock and PLL control for DaVinci devices
  3. *
  4. * Copyright (C) 2006-2007 Texas Instruments.
  5. * Copyright (C) 2008-2009 Deep Root Systems, LLC
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/errno.h>
  16. #include <linux/clk.h>
  17. #include <linux/err.h>
  18. #include <linux/mutex.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/delay.h>
  22. #include <mach/hardware.h>
  23. #include <mach/psc.h>
  24. #include <mach/cputype.h>
  25. #include "clock.h"
  26. static LIST_HEAD(clocks);
  27. static DEFINE_MUTEX(clocks_mutex);
  28. static DEFINE_SPINLOCK(clockfw_lock);
  29. static unsigned psc_domain(struct clk *clk)
  30. {
  31. return (clk->flags & PSC_DSP)
  32. ? DAVINCI_GPSC_DSPDOMAIN
  33. : DAVINCI_GPSC_ARMDOMAIN;
  34. }
  35. static void __clk_enable(struct clk *clk)
  36. {
  37. if (clk->parent)
  38. __clk_enable(clk->parent);
  39. if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
  40. davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
  41. clk->lpsc, 1);
  42. }
  43. static void __clk_disable(struct clk *clk)
  44. {
  45. if (WARN_ON(clk->usecount == 0))
  46. return;
  47. if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
  48. davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
  49. clk->lpsc, 0);
  50. if (clk->parent)
  51. __clk_disable(clk->parent);
  52. }
  53. int clk_enable(struct clk *clk)
  54. {
  55. unsigned long flags;
  56. if (clk == NULL || IS_ERR(clk))
  57. return -EINVAL;
  58. spin_lock_irqsave(&clockfw_lock, flags);
  59. __clk_enable(clk);
  60. spin_unlock_irqrestore(&clockfw_lock, flags);
  61. return 0;
  62. }
  63. EXPORT_SYMBOL(clk_enable);
  64. void clk_disable(struct clk *clk)
  65. {
  66. unsigned long flags;
  67. if (clk == NULL || IS_ERR(clk))
  68. return;
  69. spin_lock_irqsave(&clockfw_lock, flags);
  70. __clk_disable(clk);
  71. spin_unlock_irqrestore(&clockfw_lock, flags);
  72. }
  73. EXPORT_SYMBOL(clk_disable);
  74. unsigned long clk_get_rate(struct clk *clk)
  75. {
  76. if (clk == NULL || IS_ERR(clk))
  77. return -EINVAL;
  78. return clk->rate;
  79. }
  80. EXPORT_SYMBOL(clk_get_rate);
  81. long clk_round_rate(struct clk *clk, unsigned long rate)
  82. {
  83. if (clk == NULL || IS_ERR(clk))
  84. return -EINVAL;
  85. if (clk->round_rate)
  86. return clk->round_rate(clk, rate);
  87. return clk->rate;
  88. }
  89. EXPORT_SYMBOL(clk_round_rate);
  90. /* Propagate rate to children */
  91. static void propagate_rate(struct clk *root)
  92. {
  93. struct clk *clk;
  94. list_for_each_entry(clk, &root->children, childnode) {
  95. if (clk->recalc)
  96. clk->rate = clk->recalc(clk);
  97. propagate_rate(clk);
  98. }
  99. }
  100. int clk_set_rate(struct clk *clk, unsigned long rate)
  101. {
  102. unsigned long flags;
  103. int ret = -EINVAL;
  104. if (clk == NULL || IS_ERR(clk))
  105. return ret;
  106. spin_lock_irqsave(&clockfw_lock, flags);
  107. if (clk->set_rate)
  108. ret = clk->set_rate(clk, rate);
  109. if (ret == 0) {
  110. if (clk->recalc)
  111. clk->rate = clk->recalc(clk);
  112. propagate_rate(clk);
  113. }
  114. spin_unlock_irqrestore(&clockfw_lock, flags);
  115. return ret;
  116. }
  117. EXPORT_SYMBOL(clk_set_rate);
  118. int clk_set_parent(struct clk *clk, struct clk *parent)
  119. {
  120. unsigned long flags;
  121. if (clk == NULL || IS_ERR(clk))
  122. return -EINVAL;
  123. /* Cannot change parent on enabled clock */
  124. if (WARN_ON(clk->usecount))
  125. return -EINVAL;
  126. mutex_lock(&clocks_mutex);
  127. clk->parent = parent;
  128. list_del_init(&clk->childnode);
  129. list_add(&clk->childnode, &clk->parent->children);
  130. mutex_unlock(&clocks_mutex);
  131. spin_lock_irqsave(&clockfw_lock, flags);
  132. if (clk->recalc)
  133. clk->rate = clk->recalc(clk);
  134. propagate_rate(clk);
  135. spin_unlock_irqrestore(&clockfw_lock, flags);
  136. return 0;
  137. }
  138. EXPORT_SYMBOL(clk_set_parent);
  139. int clk_register(struct clk *clk)
  140. {
  141. if (clk == NULL || IS_ERR(clk))
  142. return -EINVAL;
  143. if (WARN(clk->parent && !clk->parent->rate,
  144. "CLK: %s parent %s has no rate!\n",
  145. clk->name, clk->parent->name))
  146. return -EINVAL;
  147. INIT_LIST_HEAD(&clk->children);
  148. mutex_lock(&clocks_mutex);
  149. list_add_tail(&clk->node, &clocks);
  150. if (clk->parent)
  151. list_add_tail(&clk->childnode, &clk->parent->children);
  152. mutex_unlock(&clocks_mutex);
  153. /* If rate is already set, use it */
  154. if (clk->rate)
  155. return 0;
  156. /* Else, see if there is a way to calculate it */
  157. if (clk->recalc)
  158. clk->rate = clk->recalc(clk);
  159. /* Otherwise, default to parent rate */
  160. else if (clk->parent)
  161. clk->rate = clk->parent->rate;
  162. return 0;
  163. }
  164. EXPORT_SYMBOL(clk_register);
  165. void clk_unregister(struct clk *clk)
  166. {
  167. if (clk == NULL || IS_ERR(clk))
  168. return;
  169. mutex_lock(&clocks_mutex);
  170. list_del(&clk->node);
  171. list_del(&clk->childnode);
  172. mutex_unlock(&clocks_mutex);
  173. }
  174. EXPORT_SYMBOL(clk_unregister);
  175. #ifdef CONFIG_DAVINCI_RESET_CLOCKS
  176. /*
  177. * Disable any unused clocks left on by the bootloader
  178. */
  179. static int __init clk_disable_unused(void)
  180. {
  181. struct clk *ck;
  182. spin_lock_irq(&clockfw_lock);
  183. list_for_each_entry(ck, &clocks, node) {
  184. if (ck->usecount > 0)
  185. continue;
  186. if (!(ck->flags & CLK_PSC))
  187. continue;
  188. /* ignore if in Disabled or SwRstDisable states */
  189. if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
  190. continue;
  191. pr_info("Clocks: disable unused %s\n", ck->name);
  192. davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
  193. }
  194. spin_unlock_irq(&clockfw_lock);
  195. return 0;
  196. }
  197. late_initcall(clk_disable_unused);
  198. #endif
  199. static unsigned long clk_sysclk_recalc(struct clk *clk)
  200. {
  201. u32 v, plldiv;
  202. struct pll_data *pll;
  203. unsigned long rate = clk->rate;
  204. /* If this is the PLL base clock, no more calculations needed */
  205. if (clk->pll_data)
  206. return rate;
  207. if (WARN_ON(!clk->parent))
  208. return rate;
  209. rate = clk->parent->rate;
  210. /* Otherwise, the parent must be a PLL */
  211. if (WARN_ON(!clk->parent->pll_data))
  212. return rate;
  213. pll = clk->parent->pll_data;
  214. /* If pre-PLL, source clock is before the multiplier and divider(s) */
  215. if (clk->flags & PRE_PLL)
  216. rate = pll->input_rate;
  217. if (!clk->div_reg)
  218. return rate;
  219. v = __raw_readl(pll->base + clk->div_reg);
  220. if (v & PLLDIV_EN) {
  221. plldiv = (v & PLLDIV_RATIO_MASK) + 1;
  222. if (plldiv)
  223. rate /= plldiv;
  224. }
  225. return rate;
  226. }
  227. static unsigned long clk_leafclk_recalc(struct clk *clk)
  228. {
  229. if (WARN_ON(!clk->parent))
  230. return clk->rate;
  231. return clk->parent->rate;
  232. }
  233. static unsigned long clk_pllclk_recalc(struct clk *clk)
  234. {
  235. u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
  236. u8 bypass;
  237. struct pll_data *pll = clk->pll_data;
  238. unsigned long rate = clk->rate;
  239. pll->base = IO_ADDRESS(pll->phys_base);
  240. ctrl = __raw_readl(pll->base + PLLCTL);
  241. rate = pll->input_rate = clk->parent->rate;
  242. if (ctrl & PLLCTL_PLLEN) {
  243. bypass = 0;
  244. mult = __raw_readl(pll->base + PLLM);
  245. if (cpu_is_davinci_dm365())
  246. mult = 2 * (mult & PLLM_PLLM_MASK);
  247. else
  248. mult = (mult & PLLM_PLLM_MASK) + 1;
  249. } else
  250. bypass = 1;
  251. if (pll->flags & PLL_HAS_PREDIV) {
  252. prediv = __raw_readl(pll->base + PREDIV);
  253. if (prediv & PLLDIV_EN)
  254. prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
  255. else
  256. prediv = 1;
  257. }
  258. /* pre-divider is fixed, but (some?) chips won't report that */
  259. if (cpu_is_davinci_dm355() && pll->num == 1)
  260. prediv = 8;
  261. if (pll->flags & PLL_HAS_POSTDIV) {
  262. postdiv = __raw_readl(pll->base + POSTDIV);
  263. if (postdiv & PLLDIV_EN)
  264. postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
  265. else
  266. postdiv = 1;
  267. }
  268. if (!bypass) {
  269. rate /= prediv;
  270. rate *= mult;
  271. rate /= postdiv;
  272. }
  273. pr_debug("PLL%d: input = %lu MHz [ ",
  274. pll->num, clk->parent->rate / 1000000);
  275. if (bypass)
  276. pr_debug("bypass ");
  277. if (prediv > 1)
  278. pr_debug("/ %d ", prediv);
  279. if (mult > 1)
  280. pr_debug("* %d ", mult);
  281. if (postdiv > 1)
  282. pr_debug("/ %d ", postdiv);
  283. pr_debug("] --> %lu MHz output.\n", rate / 1000000);
  284. return rate;
  285. }
  286. /**
  287. * davinci_set_pllrate - set the output rate of a given PLL.
  288. *
  289. * Note: Currently tested to work with OMAP-L138 only.
  290. *
  291. * @pll: pll whose rate needs to be changed.
  292. * @prediv: The pre divider value. Passing 0 disables the pre-divider.
  293. * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
  294. * @postdiv: The post divider value. Passing 0 disables the post-divider.
  295. */
  296. int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
  297. unsigned int mult, unsigned int postdiv)
  298. {
  299. u32 ctrl;
  300. unsigned int locktime;
  301. if (pll->base == NULL)
  302. return -EINVAL;
  303. /*
  304. * PLL lock time required per OMAP-L138 datasheet is
  305. * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
  306. * as 4 and OSCIN cycle as 25 MHz.
  307. */
  308. if (prediv) {
  309. locktime = ((2000 * prediv) / 100);
  310. prediv = (prediv - 1) | PLLDIV_EN;
  311. } else {
  312. locktime = 20;
  313. }
  314. if (postdiv)
  315. postdiv = (postdiv - 1) | PLLDIV_EN;
  316. if (mult)
  317. mult = mult - 1;
  318. ctrl = __raw_readl(pll->base + PLLCTL);
  319. /* Switch the PLL to bypass mode */
  320. ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
  321. __raw_writel(ctrl, pll->base + PLLCTL);
  322. /*
  323. * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
  324. * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
  325. * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
  326. */
  327. udelay(1);
  328. /* Reset and enable PLL */
  329. ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
  330. __raw_writel(ctrl, pll->base + PLLCTL);
  331. if (pll->flags & PLL_HAS_PREDIV)
  332. __raw_writel(prediv, pll->base + PREDIV);
  333. __raw_writel(mult, pll->base + PLLM);
  334. if (pll->flags & PLL_HAS_POSTDIV)
  335. __raw_writel(postdiv, pll->base + POSTDIV);
  336. /*
  337. * Wait for PLL to reset properly, OMAP-L138 datasheet says
  338. * 'min' time = 125ns
  339. */
  340. udelay(1);
  341. /* Bring PLL out of reset */
  342. ctrl |= PLLCTL_PLLRST;
  343. __raw_writel(ctrl, pll->base + PLLCTL);
  344. udelay(locktime);
  345. /* Remove PLL from bypass mode */
  346. ctrl |= PLLCTL_PLLEN;
  347. __raw_writel(ctrl, pll->base + PLLCTL);
  348. return 0;
  349. }
  350. EXPORT_SYMBOL(davinci_set_pllrate);
  351. int __init davinci_clk_init(struct davinci_clk *clocks)
  352. {
  353. struct davinci_clk *c;
  354. struct clk *clk;
  355. for (c = clocks; c->lk.clk; c++) {
  356. clk = c->lk.clk;
  357. if (!clk->recalc) {
  358. /* Check if clock is a PLL */
  359. if (clk->pll_data)
  360. clk->recalc = clk_pllclk_recalc;
  361. /* Else, if it is a PLL-derived clock */
  362. else if (clk->flags & CLK_PLL)
  363. clk->recalc = clk_sysclk_recalc;
  364. /* Otherwise, it is a leaf clock (PSC clock) */
  365. else if (clk->parent)
  366. clk->recalc = clk_leafclk_recalc;
  367. }
  368. if (clk->recalc)
  369. clk->rate = clk->recalc(clk);
  370. if (clk->lpsc)
  371. clk->flags |= CLK_PSC;
  372. clkdev_add(&c->lk);
  373. clk_register(clk);
  374. /* Turn on clocks that Linux doesn't otherwise manage */
  375. if (clk->flags & ALWAYS_ENABLED)
  376. clk_enable(clk);
  377. }
  378. return 0;
  379. }
  380. #ifdef CONFIG_PROC_FS
  381. #include <linux/proc_fs.h>
  382. #include <linux/seq_file.h>
  383. static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
  384. {
  385. return *pos < 1 ? (void *)1 : NULL;
  386. }
  387. static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
  388. {
  389. ++*pos;
  390. return NULL;
  391. }
  392. static void davinci_ck_stop(struct seq_file *m, void *v)
  393. {
  394. }
  395. #define CLKNAME_MAX 10 /* longest clock name */
  396. #define NEST_DELTA 2
  397. #define NEST_MAX 4
  398. static void
  399. dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
  400. {
  401. char *state;
  402. char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
  403. struct clk *clk;
  404. unsigned i;
  405. if (parent->flags & CLK_PLL)
  406. state = "pll";
  407. else if (parent->flags & CLK_PSC)
  408. state = "psc";
  409. else
  410. state = "";
  411. /* <nest spaces> name <pad to end> */
  412. memset(buf, ' ', sizeof(buf) - 1);
  413. buf[sizeof(buf) - 1] = 0;
  414. i = strlen(parent->name);
  415. memcpy(buf + nest, parent->name,
  416. min(i, (unsigned)(sizeof(buf) - 1 - nest)));
  417. seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
  418. buf, parent->usecount, state, clk_get_rate(parent));
  419. /* REVISIT show device associations too */
  420. /* cost is now small, but not linear... */
  421. list_for_each_entry(clk, &parent->children, childnode) {
  422. dump_clock(s, nest + NEST_DELTA, clk);
  423. }
  424. }
  425. static int davinci_ck_show(struct seq_file *m, void *v)
  426. {
  427. /* Show clock tree; we know the main oscillator is first.
  428. * We trust nonzero usecounts equate to PSC enables...
  429. */
  430. mutex_lock(&clocks_mutex);
  431. if (!list_empty(&clocks))
  432. dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
  433. mutex_unlock(&clocks_mutex);
  434. return 0;
  435. }
  436. static const struct seq_operations davinci_ck_op = {
  437. .start = davinci_ck_start,
  438. .next = davinci_ck_next,
  439. .stop = davinci_ck_stop,
  440. .show = davinci_ck_show
  441. };
  442. static int davinci_ck_open(struct inode *inode, struct file *file)
  443. {
  444. return seq_open(file, &davinci_ck_op);
  445. }
  446. static const struct file_operations proc_davinci_ck_operations = {
  447. .open = davinci_ck_open,
  448. .read = seq_read,
  449. .llseek = seq_lseek,
  450. .release = seq_release,
  451. };
  452. static int __init davinci_ck_proc_init(void)
  453. {
  454. proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
  455. return 0;
  456. }
  457. __initcall(davinci_ck_proc_init);
  458. #endif /* CONFIG_DEBUG_PROC_FS */