wl1251_ops.c 18 KB

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  1. /*
  2. * This file is part of wl1251
  3. *
  4. * Copyright (C) 2008-2009 Nokia Corporation
  5. *
  6. * Contact: Kalle Valo <kalle.valo@nokia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. *
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include "wl1251_ops.h"
  26. #include "reg.h"
  27. #include "wl1251_spi.h"
  28. #include "wl1251_boot.h"
  29. #include "wl1251_event.h"
  30. #include "wl1251_acx.h"
  31. #include "wl1251_tx.h"
  32. #include "wl1251_rx.h"
  33. #include "wl1251_ps.h"
  34. #include "wl1251_init.h"
  35. static struct wl1251_partition_set wl1251_part_table[PART_TABLE_LEN] = {
  36. [PART_DOWN] = {
  37. .mem = {
  38. .start = 0x00000000,
  39. .size = 0x00016800
  40. },
  41. .reg = {
  42. .start = REGISTERS_BASE,
  43. .size = REGISTERS_DOWN_SIZE
  44. },
  45. },
  46. [PART_WORK] = {
  47. .mem = {
  48. .start = 0x00028000,
  49. .size = 0x00014000
  50. },
  51. .reg = {
  52. .start = REGISTERS_BASE,
  53. .size = REGISTERS_WORK_SIZE
  54. },
  55. },
  56. /* WL1251 doesn't use the DRPW partition, so we don't set it here */
  57. };
  58. static enum wl12xx_acx_int_reg wl1251_acx_reg_table[ACX_REG_TABLE_LEN] = {
  59. [ACX_REG_INTERRUPT_TRIG] = (REGISTERS_BASE + 0x0474),
  60. [ACX_REG_INTERRUPT_TRIG_H] = (REGISTERS_BASE + 0x0478),
  61. [ACX_REG_INTERRUPT_MASK] = (REGISTERS_BASE + 0x0494),
  62. [ACX_REG_HINT_MASK_SET] = (REGISTERS_BASE + 0x0498),
  63. [ACX_REG_HINT_MASK_CLR] = (REGISTERS_BASE + 0x049C),
  64. [ACX_REG_INTERRUPT_NO_CLEAR] = (REGISTERS_BASE + 0x04B0),
  65. [ACX_REG_INTERRUPT_CLEAR] = (REGISTERS_BASE + 0x04A4),
  66. [ACX_REG_INTERRUPT_ACK] = (REGISTERS_BASE + 0x04A8),
  67. [ACX_REG_SLV_SOFT_RESET] = (REGISTERS_BASE + 0x0000),
  68. [ACX_REG_EE_START] = (REGISTERS_BASE + 0x080C),
  69. [ACX_REG_ECPU_CONTROL] = (REGISTERS_BASE + 0x0804)
  70. };
  71. static int wl1251_upload_firmware(struct wl1251 *wl)
  72. {
  73. struct wl1251_partition_set *p_table = wl->chip.p_table;
  74. int addr, chunk_num, partition_limit;
  75. size_t fw_data_len;
  76. u8 *p;
  77. /* whal_FwCtrl_LoadFwImageSm() */
  78. wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
  79. wl1251_reg_read32(wl, CHIP_ID_B));
  80. /* 10.0 check firmware length and set partition */
  81. fw_data_len = (wl->fw[4] << 24) | (wl->fw[5] << 16) |
  82. (wl->fw[6] << 8) | (wl->fw[7]);
  83. wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
  84. CHUNK_SIZE);
  85. if ((fw_data_len % 4) != 0) {
  86. wl1251_error("firmware length not multiple of four");
  87. return -EIO;
  88. }
  89. wl1251_set_partition(wl,
  90. p_table[PART_DOWN].mem.start,
  91. p_table[PART_DOWN].mem.size,
  92. p_table[PART_DOWN].reg.start,
  93. p_table[PART_DOWN].reg.size);
  94. /* 10.1 set partition limit and chunk num */
  95. chunk_num = 0;
  96. partition_limit = p_table[PART_DOWN].mem.size;
  97. while (chunk_num < fw_data_len / CHUNK_SIZE) {
  98. /* 10.2 update partition, if needed */
  99. addr = p_table[PART_DOWN].mem.start +
  100. (chunk_num + 2) * CHUNK_SIZE;
  101. if (addr > partition_limit) {
  102. addr = p_table[PART_DOWN].mem.start +
  103. chunk_num * CHUNK_SIZE;
  104. partition_limit = chunk_num * CHUNK_SIZE +
  105. p_table[PART_DOWN].mem.size;
  106. wl1251_set_partition(wl,
  107. addr,
  108. p_table[PART_DOWN].mem.size,
  109. p_table[PART_DOWN].reg.start,
  110. p_table[PART_DOWN].reg.size);
  111. }
  112. /* 10.3 upload the chunk */
  113. addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE;
  114. p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
  115. wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
  116. p, addr);
  117. wl1251_spi_mem_write(wl, addr, p, CHUNK_SIZE);
  118. chunk_num++;
  119. }
  120. /* 10.4 upload the last chunk */
  121. addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE;
  122. p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
  123. wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
  124. fw_data_len % CHUNK_SIZE, p, addr);
  125. wl1251_spi_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE);
  126. return 0;
  127. }
  128. static int wl1251_upload_nvs(struct wl1251 *wl)
  129. {
  130. size_t nvs_len, nvs_bytes_written, burst_len;
  131. int nvs_start, i;
  132. u32 dest_addr, val;
  133. u8 *nvs_ptr, *nvs;
  134. nvs = wl->nvs;
  135. if (nvs == NULL)
  136. return -ENODEV;
  137. nvs_ptr = nvs;
  138. nvs_len = wl->nvs_len;
  139. nvs_start = wl->fw_len;
  140. /*
  141. * Layout before the actual NVS tables:
  142. * 1 byte : burst length.
  143. * 2 bytes: destination address.
  144. * n bytes: data to burst copy.
  145. *
  146. * This is ended by a 0 length, then the NVS tables.
  147. */
  148. while (nvs_ptr[0]) {
  149. burst_len = nvs_ptr[0];
  150. dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
  151. /* We move our pointer to the data */
  152. nvs_ptr += 3;
  153. for (i = 0; i < burst_len; i++) {
  154. val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
  155. | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
  156. wl1251_debug(DEBUG_BOOT,
  157. "nvs burst write 0x%x: 0x%x",
  158. dest_addr, val);
  159. wl1251_mem_write32(wl, dest_addr, val);
  160. nvs_ptr += 4;
  161. dest_addr += 4;
  162. }
  163. }
  164. /*
  165. * We've reached the first zero length, the first NVS table
  166. * is 7 bytes further.
  167. */
  168. nvs_ptr += 7;
  169. nvs_len -= nvs_ptr - nvs;
  170. nvs_len = ALIGN(nvs_len, 4);
  171. /* Now we must set the partition correctly */
  172. wl1251_set_partition(wl, nvs_start,
  173. wl->chip.p_table[PART_DOWN].mem.size,
  174. wl->chip.p_table[PART_DOWN].reg.start,
  175. wl->chip.p_table[PART_DOWN].reg.size);
  176. /* And finally we upload the NVS tables */
  177. nvs_bytes_written = 0;
  178. while (nvs_bytes_written < nvs_len) {
  179. val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
  180. | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
  181. val = cpu_to_le32(val);
  182. wl1251_debug(DEBUG_BOOT,
  183. "nvs write table 0x%x: 0x%x",
  184. nvs_start, val);
  185. wl1251_mem_write32(wl, nvs_start, val);
  186. nvs_ptr += 4;
  187. nvs_bytes_written += 4;
  188. nvs_start += 4;
  189. }
  190. return 0;
  191. }
  192. static int wl1251_boot(struct wl1251 *wl)
  193. {
  194. int ret = 0, minor_minor_e2_ver;
  195. u32 tmp, boot_data;
  196. ret = wl1251_boot_soft_reset(wl);
  197. if (ret < 0)
  198. goto out;
  199. /* 2. start processing NVS file */
  200. ret = wl->chip.op_upload_nvs(wl);
  201. if (ret < 0)
  202. goto out;
  203. /* write firmware's last address (ie. it's length) to
  204. * ACX_EEPROMLESS_IND_REG */
  205. wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
  206. /* 6. read the EEPROM parameters */
  207. tmp = wl1251_reg_read32(wl, SCR_PAD2);
  208. /* 7. read bootdata */
  209. wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
  210. wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
  211. tmp = wl1251_reg_read32(wl, SCR_PAD3);
  212. /* 8. check bootdata and call restart sequence */
  213. wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
  214. minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
  215. wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
  216. "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
  217. wl->boot_attr.radio_type, wl->boot_attr.major,
  218. wl->boot_attr.minor, minor_minor_e2_ver);
  219. ret = wl1251_boot_init_seq(wl);
  220. if (ret < 0)
  221. goto out;
  222. /* 9. NVS processing done */
  223. boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
  224. wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
  225. /* 10. check that ECPU_CONTROL_HALT bits are set in
  226. * pWhalBus->uBootData and start uploading firmware
  227. */
  228. if ((boot_data & ECPU_CONTROL_HALT) == 0) {
  229. wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
  230. ret = -EIO;
  231. goto out;
  232. }
  233. ret = wl->chip.op_upload_fw(wl);
  234. if (ret < 0)
  235. goto out;
  236. /* 10.5 start firmware */
  237. ret = wl1251_boot_run_firmware(wl);
  238. if (ret < 0)
  239. goto out;
  240. out:
  241. return ret;
  242. }
  243. static int wl1251_mem_cfg(struct wl1251 *wl)
  244. {
  245. struct wl1251_acx_config_memory *mem_conf;
  246. int ret, i;
  247. wl1251_debug(DEBUG_ACX, "wl1251 mem cfg");
  248. mem_conf = kzalloc(sizeof(*mem_conf), GFP_KERNEL);
  249. if (!mem_conf) {
  250. ret = -ENOMEM;
  251. goto out;
  252. }
  253. /* memory config */
  254. mem_conf->mem_config.num_stations = cpu_to_le16(DEFAULT_NUM_STATIONS);
  255. mem_conf->mem_config.rx_mem_block_num = 35;
  256. mem_conf->mem_config.tx_min_mem_block_num = 64;
  257. mem_conf->mem_config.num_tx_queues = MAX_TX_QUEUES;
  258. mem_conf->mem_config.host_if_options = HOSTIF_PKT_RING;
  259. mem_conf->mem_config.num_ssid_profiles = 1;
  260. mem_conf->mem_config.debug_buffer_size =
  261. cpu_to_le16(TRACE_BUFFER_MAX_SIZE);
  262. /* RX queue config */
  263. mem_conf->rx_queue_config.dma_address = 0;
  264. mem_conf->rx_queue_config.num_descs = ACX_RX_DESC_DEF;
  265. mem_conf->rx_queue_config.priority = DEFAULT_RXQ_PRIORITY;
  266. mem_conf->rx_queue_config.type = DEFAULT_RXQ_TYPE;
  267. /* TX queue config */
  268. for (i = 0; i < MAX_TX_QUEUES; i++) {
  269. mem_conf->tx_queue_config[i].num_descs = ACX_TX_DESC_DEF;
  270. mem_conf->tx_queue_config[i].attributes = i;
  271. }
  272. ret = wl1251_cmd_configure(wl, ACX_MEM_CFG, mem_conf,
  273. sizeof(*mem_conf));
  274. if (ret < 0) {
  275. wl1251_warning("wl1251 mem config failed: %d", ret);
  276. goto out;
  277. }
  278. out:
  279. kfree(mem_conf);
  280. return ret;
  281. }
  282. static int wl1251_hw_init_mem_config(struct wl1251 *wl)
  283. {
  284. int ret;
  285. ret = wl1251_mem_cfg(wl);
  286. if (ret < 0)
  287. return ret;
  288. wl->target_mem_map = kzalloc(sizeof(struct wl1251_acx_mem_map),
  289. GFP_KERNEL);
  290. if (!wl->target_mem_map) {
  291. wl1251_error("couldn't allocate target memory map");
  292. return -ENOMEM;
  293. }
  294. /* we now ask for the firmware built memory map */
  295. ret = wl1251_acx_mem_map(wl, wl->target_mem_map,
  296. sizeof(struct wl1251_acx_mem_map));
  297. if (ret < 0) {
  298. wl1251_error("couldn't retrieve firmware memory map");
  299. kfree(wl->target_mem_map);
  300. wl->target_mem_map = NULL;
  301. return ret;
  302. }
  303. return 0;
  304. }
  305. static void wl1251_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
  306. {
  307. u32 cpu_ctrl;
  308. /* 10.5.0 run the firmware (I) */
  309. cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
  310. /* 10.5.1 run the firmware (II) */
  311. cpu_ctrl &= ~flag;
  312. wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
  313. }
  314. static void wl1251_target_enable_interrupts(struct wl1251 *wl)
  315. {
  316. /* Enable target's interrupts */
  317. wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
  318. WL1251_ACX_INTR_RX1_DATA |
  319. WL1251_ACX_INTR_TX_RESULT |
  320. WL1251_ACX_INTR_EVENT_A |
  321. WL1251_ACX_INTR_EVENT_B |
  322. WL1251_ACX_INTR_INIT_COMPLETE;
  323. wl1251_boot_target_enable_interrupts(wl);
  324. }
  325. static void wl1251_fw_version(struct wl1251 *wl)
  326. {
  327. wl1251_acx_fw_version(wl, wl->chip.fw_ver, sizeof(wl->chip.fw_ver));
  328. }
  329. static void wl1251_irq_work(struct work_struct *work)
  330. {
  331. u32 intr;
  332. struct wl1251 *wl =
  333. container_of(work, struct wl1251, irq_work);
  334. int ret;
  335. mutex_lock(&wl->mutex);
  336. wl1251_debug(DEBUG_IRQ, "IRQ work");
  337. if (wl->state == WL1251_STATE_OFF)
  338. goto out;
  339. ret = wl1251_ps_elp_wakeup(wl);
  340. if (ret < 0)
  341. goto out;
  342. wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1251_ACX_INTR_ALL);
  343. intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR);
  344. wl1251_debug(DEBUG_IRQ, "intr: 0x%x", intr);
  345. if (wl->data_path) {
  346. wl->rx_counter =
  347. wl1251_mem_read32(wl, wl->data_path->rx_control_addr);
  348. /* We handle a firmware bug here */
  349. switch ((wl->rx_counter - wl->rx_handled) & 0xf) {
  350. case 0:
  351. wl1251_debug(DEBUG_IRQ, "RX: FW and host in sync");
  352. intr &= ~WL1251_ACX_INTR_RX0_DATA;
  353. intr &= ~WL1251_ACX_INTR_RX1_DATA;
  354. break;
  355. case 1:
  356. wl1251_debug(DEBUG_IRQ, "RX: FW +1");
  357. intr |= WL1251_ACX_INTR_RX0_DATA;
  358. intr &= ~WL1251_ACX_INTR_RX1_DATA;
  359. break;
  360. case 2:
  361. wl1251_debug(DEBUG_IRQ, "RX: FW +2");
  362. intr |= WL1251_ACX_INTR_RX0_DATA;
  363. intr |= WL1251_ACX_INTR_RX1_DATA;
  364. break;
  365. default:
  366. wl1251_warning("RX: FW and host out of sync: %d",
  367. wl->rx_counter - wl->rx_handled);
  368. break;
  369. }
  370. wl->rx_handled = wl->rx_counter;
  371. wl1251_debug(DEBUG_IRQ, "RX counter: %d", wl->rx_counter);
  372. }
  373. intr &= wl->intr_mask;
  374. if (intr == 0) {
  375. wl1251_debug(DEBUG_IRQ, "INTR is 0");
  376. wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
  377. ~(wl->intr_mask));
  378. goto out_sleep;
  379. }
  380. if (intr & WL1251_ACX_INTR_RX0_DATA) {
  381. wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX0_DATA");
  382. wl1251_rx(wl);
  383. }
  384. if (intr & WL1251_ACX_INTR_RX1_DATA) {
  385. wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX1_DATA");
  386. wl1251_rx(wl);
  387. }
  388. if (intr & WL1251_ACX_INTR_TX_RESULT) {
  389. wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_TX_RESULT");
  390. wl1251_tx_complete(wl);
  391. }
  392. if (intr & (WL1251_ACX_INTR_EVENT_A | WL1251_ACX_INTR_EVENT_B)) {
  393. wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_EVENT (0x%x)", intr);
  394. if (intr & WL1251_ACX_INTR_EVENT_A)
  395. wl1251_event_handle(wl, 0);
  396. else
  397. wl1251_event_handle(wl, 1);
  398. }
  399. if (intr & WL1251_ACX_INTR_INIT_COMPLETE)
  400. wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_INIT_COMPLETE");
  401. wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
  402. out_sleep:
  403. wl1251_ps_elp_sleep(wl);
  404. out:
  405. mutex_unlock(&wl->mutex);
  406. }
  407. static int wl1251_hw_init_txq_fill(u8 qid,
  408. struct acx_tx_queue_qos_config *config,
  409. u32 num_blocks)
  410. {
  411. config->qid = qid;
  412. switch (qid) {
  413. case QOS_AC_BE:
  414. config->high_threshold =
  415. (QOS_TX_HIGH_BE_DEF * num_blocks) / 100;
  416. config->low_threshold =
  417. (QOS_TX_LOW_BE_DEF * num_blocks) / 100;
  418. break;
  419. case QOS_AC_BK:
  420. config->high_threshold =
  421. (QOS_TX_HIGH_BK_DEF * num_blocks) / 100;
  422. config->low_threshold =
  423. (QOS_TX_LOW_BK_DEF * num_blocks) / 100;
  424. break;
  425. case QOS_AC_VI:
  426. config->high_threshold =
  427. (QOS_TX_HIGH_VI_DEF * num_blocks) / 100;
  428. config->low_threshold =
  429. (QOS_TX_LOW_VI_DEF * num_blocks) / 100;
  430. break;
  431. case QOS_AC_VO:
  432. config->high_threshold =
  433. (QOS_TX_HIGH_VO_DEF * num_blocks) / 100;
  434. config->low_threshold =
  435. (QOS_TX_LOW_VO_DEF * num_blocks) / 100;
  436. break;
  437. default:
  438. wl1251_error("Invalid TX queue id: %d", qid);
  439. return -EINVAL;
  440. }
  441. return 0;
  442. }
  443. static int wl1251_hw_init_tx_queue_config(struct wl1251 *wl)
  444. {
  445. struct acx_tx_queue_qos_config *config;
  446. struct wl1251_acx_mem_map *wl_mem_map = wl->target_mem_map;
  447. int ret, i;
  448. wl1251_debug(DEBUG_ACX, "acx tx queue config");
  449. config = kzalloc(sizeof(*config), GFP_KERNEL);
  450. if (!config) {
  451. ret = -ENOMEM;
  452. goto out;
  453. }
  454. for (i = 0; i < MAX_NUM_OF_AC; i++) {
  455. ret = wl1251_hw_init_txq_fill(i, config,
  456. wl_mem_map->num_tx_mem_blocks);
  457. if (ret < 0)
  458. goto out;
  459. ret = wl1251_cmd_configure(wl, ACX_TX_QUEUE_CFG,
  460. config, sizeof(*config));
  461. if (ret < 0)
  462. goto out;
  463. }
  464. out:
  465. kfree(config);
  466. return ret;
  467. }
  468. static int wl1251_hw_init_data_path_config(struct wl1251 *wl)
  469. {
  470. int ret;
  471. /* asking for the data path parameters */
  472. wl->data_path = kzalloc(sizeof(struct acx_data_path_params_resp),
  473. GFP_KERNEL);
  474. if (!wl->data_path) {
  475. wl1251_error("Couldn't allocate data path parameters");
  476. return -ENOMEM;
  477. }
  478. ret = wl1251_acx_data_path_params(wl, wl->data_path);
  479. if (ret < 0) {
  480. kfree(wl->data_path);
  481. wl->data_path = NULL;
  482. return ret;
  483. }
  484. return 0;
  485. }
  486. static int wl1251_hw_init(struct wl1251 *wl)
  487. {
  488. struct wl1251_acx_mem_map *wl_mem_map;
  489. int ret;
  490. ret = wl1251_hw_init_hwenc_config(wl);
  491. if (ret < 0)
  492. return ret;
  493. /* Template settings */
  494. ret = wl1251_hw_init_templates_config(wl);
  495. if (ret < 0)
  496. return ret;
  497. /* Default memory configuration */
  498. ret = wl1251_hw_init_mem_config(wl);
  499. if (ret < 0)
  500. return ret;
  501. /* Default data path configuration */
  502. ret = wl1251_hw_init_data_path_config(wl);
  503. if (ret < 0)
  504. goto out_free_memmap;
  505. /* RX config */
  506. ret = wl1251_hw_init_rx_config(wl,
  507. RX_CFG_PROMISCUOUS | RX_CFG_TSF,
  508. RX_FILTER_OPTION_DEF);
  509. /* RX_CONFIG_OPTION_ANY_DST_ANY_BSS,
  510. RX_FILTER_OPTION_FILTER_ALL); */
  511. if (ret < 0)
  512. goto out_free_data_path;
  513. /* TX queues config */
  514. ret = wl1251_hw_init_tx_queue_config(wl);
  515. if (ret < 0)
  516. goto out_free_data_path;
  517. /* PHY layer config */
  518. ret = wl1251_hw_init_phy_config(wl);
  519. if (ret < 0)
  520. goto out_free_data_path;
  521. /* Beacon filtering */
  522. ret = wl1251_hw_init_beacon_filter(wl);
  523. if (ret < 0)
  524. goto out_free_data_path;
  525. /* Bluetooth WLAN coexistence */
  526. ret = wl1251_hw_init_pta(wl);
  527. if (ret < 0)
  528. goto out_free_data_path;
  529. /* Energy detection */
  530. ret = wl1251_hw_init_energy_detection(wl);
  531. if (ret < 0)
  532. goto out_free_data_path;
  533. /* Beacons and boradcast settings */
  534. ret = wl1251_hw_init_beacon_broadcast(wl);
  535. if (ret < 0)
  536. goto out_free_data_path;
  537. /* Enable data path */
  538. ret = wl1251_cmd_data_path(wl, wl->channel, 1);
  539. if (ret < 0)
  540. goto out_free_data_path;
  541. /* Default power state */
  542. ret = wl1251_hw_init_power_auth(wl);
  543. if (ret < 0)
  544. goto out_free_data_path;
  545. wl_mem_map = wl->target_mem_map;
  546. wl1251_info("%d tx blocks at 0x%x, %d rx blocks at 0x%x",
  547. wl_mem_map->num_tx_mem_blocks,
  548. wl->data_path->tx_control_addr,
  549. wl_mem_map->num_rx_mem_blocks,
  550. wl->data_path->rx_control_addr);
  551. return 0;
  552. out_free_data_path:
  553. kfree(wl->data_path);
  554. out_free_memmap:
  555. kfree(wl->target_mem_map);
  556. return ret;
  557. }
  558. static int wl1251_plt_init(struct wl1251 *wl)
  559. {
  560. int ret;
  561. ret = wl1251_hw_init_mem_config(wl);
  562. if (ret < 0)
  563. return ret;
  564. ret = wl1251_cmd_data_path(wl, wl->channel, 1);
  565. if (ret < 0)
  566. return ret;
  567. return 0;
  568. }
  569. void wl1251_setup(struct wl1251 *wl)
  570. {
  571. /* FIXME: Is it better to use strncpy here or is this ok? */
  572. wl->chip.fw_filename = WL1251_FW_NAME;
  573. wl->chip.nvs_filename = WL1251_NVS_NAME;
  574. /* Now we know what chip we're using, so adjust the power on sleep
  575. * time accordingly */
  576. wl->chip.power_on_sleep = WL1251_POWER_ON_SLEEP;
  577. wl->chip.intr_cmd_complete = WL1251_ACX_INTR_CMD_COMPLETE;
  578. wl->chip.intr_init_complete = WL1251_ACX_INTR_INIT_COMPLETE;
  579. wl->chip.op_upload_nvs = wl1251_upload_nvs;
  580. wl->chip.op_upload_fw = wl1251_upload_firmware;
  581. wl->chip.op_boot = wl1251_boot;
  582. wl->chip.op_set_ecpu_ctrl = wl1251_set_ecpu_ctrl;
  583. wl->chip.op_target_enable_interrupts = wl1251_target_enable_interrupts;
  584. wl->chip.op_hw_init = wl1251_hw_init;
  585. wl->chip.op_plt_init = wl1251_plt_init;
  586. wl->chip.op_fw_version = wl1251_fw_version;
  587. wl->chip.op_tx_flush = wl1251_tx_flush;
  588. wl->chip.op_cmd_join = wl1251_cmd_join;
  589. wl->chip.p_table = wl1251_part_table;
  590. wl->chip.acx_reg_table = wl1251_acx_reg_table;
  591. INIT_WORK(&wl->irq_work, wl1251_irq_work);
  592. INIT_WORK(&wl->tx_work, wl1251_tx_work);
  593. }