config.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253
  1. /***************************************************************************/
  2. /*
  3. * linux/arch/m68knommu/platform/528x/config.c
  4. *
  5. * Sub-architcture dependent initialization code for the Freescale
  6. * 5280, 5281 and 5282 CPUs.
  7. *
  8. * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
  9. * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  10. */
  11. /***************************************************************************/
  12. #include <linux/kernel.h>
  13. #include <linux/param.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/io.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/gpio.h>
  19. #include <asm/machdep.h>
  20. #include <asm/coldfire.h>
  21. #include <asm/mcfsim.h>
  22. #include <asm/mcfuart.h>
  23. #include <asm/mcfqspi.h>
  24. /***************************************************************************/
  25. #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
  26. static struct resource m528x_qspi_resources[] = {
  27. {
  28. .start = MCFQSPI_IOBASE,
  29. .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
  30. .flags = IORESOURCE_MEM,
  31. },
  32. {
  33. .start = MCFINT_VECBASE + MCFINT_QSPI,
  34. .end = MCFINT_VECBASE + MCFINT_QSPI,
  35. .flags = IORESOURCE_IRQ,
  36. },
  37. };
  38. #define MCFQSPI_CS0 147
  39. #define MCFQSPI_CS1 148
  40. #define MCFQSPI_CS2 149
  41. #define MCFQSPI_CS3 150
  42. static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
  43. {
  44. int status;
  45. status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
  46. if (status) {
  47. pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
  48. goto fail0;
  49. }
  50. status = gpio_direction_output(MCFQSPI_CS0, 1);
  51. if (status) {
  52. pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
  53. goto fail1;
  54. }
  55. status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
  56. if (status) {
  57. pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
  58. goto fail1;
  59. }
  60. status = gpio_direction_output(MCFQSPI_CS1, 1);
  61. if (status) {
  62. pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
  63. goto fail2;
  64. }
  65. status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
  66. if (status) {
  67. pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
  68. goto fail2;
  69. }
  70. status = gpio_direction_output(MCFQSPI_CS2, 1);
  71. if (status) {
  72. pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
  73. goto fail3;
  74. }
  75. status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
  76. if (status) {
  77. pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
  78. goto fail3;
  79. }
  80. status = gpio_direction_output(MCFQSPI_CS3, 1);
  81. if (status) {
  82. pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
  83. goto fail4;
  84. }
  85. return 0;
  86. fail4:
  87. gpio_free(MCFQSPI_CS3);
  88. fail3:
  89. gpio_free(MCFQSPI_CS2);
  90. fail2:
  91. gpio_free(MCFQSPI_CS1);
  92. fail1:
  93. gpio_free(MCFQSPI_CS0);
  94. fail0:
  95. return status;
  96. }
  97. static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
  98. {
  99. gpio_free(MCFQSPI_CS3);
  100. gpio_free(MCFQSPI_CS2);
  101. gpio_free(MCFQSPI_CS1);
  102. gpio_free(MCFQSPI_CS0);
  103. }
  104. static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
  105. u8 chip_select, bool cs_high)
  106. {
  107. gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
  108. }
  109. static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
  110. u8 chip_select, bool cs_high)
  111. {
  112. gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
  113. }
  114. static struct mcfqspi_cs_control m528x_cs_control = {
  115. .setup = m528x_cs_setup,
  116. .teardown = m528x_cs_teardown,
  117. .select = m528x_cs_select,
  118. .deselect = m528x_cs_deselect,
  119. };
  120. static struct mcfqspi_platform_data m528x_qspi_data = {
  121. .bus_num = 0,
  122. .num_chipselect = 4,
  123. .cs_control = &m528x_cs_control,
  124. };
  125. static struct platform_device m528x_qspi = {
  126. .name = "mcfqspi",
  127. .id = 0,
  128. .num_resources = ARRAY_SIZE(m528x_qspi_resources),
  129. .resource = m528x_qspi_resources,
  130. .dev.platform_data = &m528x_qspi_data,
  131. };
  132. static void __init m528x_qspi_init(void)
  133. {
  134. /* setup Port QS for QSPI with gpio CS control */
  135. __raw_writeb(0x07, MCFGPIO_PQSPAR);
  136. }
  137. #endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
  138. static struct platform_device *m528x_devices[] __initdata = {
  139. #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
  140. &m528x_qspi,
  141. #endif
  142. };
  143. /***************************************************************************/
  144. static void __init m528x_uarts_init(void)
  145. {
  146. u8 port;
  147. /* make sure PUAPAR is set for UART0 and UART1 */
  148. port = readb(MCF5282_GPIO_PUAPAR);
  149. port |= 0x03 | (0x03 << 2);
  150. writeb(port, MCF5282_GPIO_PUAPAR);
  151. }
  152. /***************************************************************************/
  153. static void __init m528x_fec_init(void)
  154. {
  155. u16 v16;
  156. /* Set multi-function pins to ethernet mode for fec0 */
  157. v16 = readw(MCF_IPSBAR + 0x100056);
  158. writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
  159. writeb(0xc0, MCF_IPSBAR + 0x100058);
  160. }
  161. /***************************************************************************/
  162. static void m528x_cpu_reset(void)
  163. {
  164. local_irq_disable();
  165. __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
  166. }
  167. /***************************************************************************/
  168. #ifdef CONFIG_WILDFIRE
  169. void wildfire_halt(void)
  170. {
  171. writeb(0, 0x30000007);
  172. writeb(0x2, 0x30000007);
  173. }
  174. #endif
  175. #ifdef CONFIG_WILDFIREMOD
  176. void wildfiremod_halt(void)
  177. {
  178. printk(KERN_INFO "WildFireMod hibernating...\n");
  179. /* Set portE.5 to Digital IO */
  180. MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
  181. /* Make portE.5 an output */
  182. MCF5282_GPIO_DDRE |= (1 << 5);
  183. /* Now toggle portE.5 from low to high */
  184. MCF5282_GPIO_PORTE &= ~(1 << 5);
  185. MCF5282_GPIO_PORTE |= (1 << 5);
  186. printk(KERN_EMERG "Failed to hibernate. Halting!\n");
  187. }
  188. #endif
  189. void __init config_BSP(char *commandp, int size)
  190. {
  191. #ifdef CONFIG_WILDFIRE
  192. mach_halt = wildfire_halt;
  193. #endif
  194. #ifdef CONFIG_WILDFIREMOD
  195. mach_halt = wildfiremod_halt;
  196. #endif
  197. }
  198. /***************************************************************************/
  199. static int __init init_BSP(void)
  200. {
  201. mach_reset = m528x_cpu_reset;
  202. mach_sched_init = hw_timer_init;
  203. m528x_uarts_init();
  204. m528x_fec_init();
  205. #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
  206. m528x_qspi_init();
  207. #endif
  208. platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
  209. return 0;
  210. }
  211. arch_initcall(init_BSP);
  212. /***************************************************************************/