perf_event_intel.c 42 KB

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  1. #ifdef CONFIG_CPU_SUP_INTEL
  2. /*
  3. * Per core/cpu state
  4. *
  5. * Used to coordinate shared registers between HT threads or
  6. * among events on a single PMU.
  7. */
  8. struct intel_shared_regs {
  9. struct er_account regs[EXTRA_REG_MAX];
  10. int refcnt; /* per-core: #HT threads */
  11. unsigned core_id; /* per-core: core id */
  12. };
  13. /*
  14. * Intel PerfMon, used on Core and later.
  15. */
  16. static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  17. {
  18. [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
  19. [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
  20. [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
  21. [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
  22. [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
  23. [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
  24. [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
  25. };
  26. static struct event_constraint intel_core_event_constraints[] __read_mostly =
  27. {
  28. INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  29. INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  30. INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  31. INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  32. INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  33. INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  34. EVENT_CONSTRAINT_END
  35. };
  36. static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  37. {
  38. FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  39. FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  40. /*
  41. * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
  42. * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
  43. * ratio between these counters.
  44. */
  45. /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  46. INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  47. INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  48. INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  49. INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  50. INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  51. INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  52. INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  53. INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  54. INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  55. INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  56. EVENT_CONSTRAINT_END
  57. };
  58. static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  59. {
  60. FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  61. FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  62. /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  63. INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  64. INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  65. INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  66. INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  67. INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  68. INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  69. INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  70. INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  71. EVENT_CONSTRAINT_END
  72. };
  73. static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  74. {
  75. INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  76. EVENT_EXTRA_END
  77. };
  78. static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  79. {
  80. FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  81. FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  82. /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  83. INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  84. INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  85. INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  86. INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
  87. EVENT_CONSTRAINT_END
  88. };
  89. static struct event_constraint intel_snb_event_constraints[] __read_mostly =
  90. {
  91. FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  92. FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  93. /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  94. INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
  95. INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
  96. INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
  97. EVENT_CONSTRAINT_END
  98. };
  99. static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
  100. {
  101. INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  102. INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
  103. EVENT_EXTRA_END
  104. };
  105. static struct event_constraint intel_gen_event_constraints[] __read_mostly =
  106. {
  107. FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  108. FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  109. /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  110. EVENT_CONSTRAINT_END
  111. };
  112. static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
  113. INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
  114. INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
  115. EVENT_EXTRA_END
  116. };
  117. static u64 intel_pmu_event_map(int hw_event)
  118. {
  119. return intel_perfmon_event_map[hw_event];
  120. }
  121. static __initconst const u64 snb_hw_cache_event_ids
  122. [PERF_COUNT_HW_CACHE_MAX]
  123. [PERF_COUNT_HW_CACHE_OP_MAX]
  124. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  125. {
  126. [ C(L1D) ] = {
  127. [ C(OP_READ) ] = {
  128. [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
  129. [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
  130. },
  131. [ C(OP_WRITE) ] = {
  132. [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
  133. [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
  134. },
  135. [ C(OP_PREFETCH) ] = {
  136. [ C(RESULT_ACCESS) ] = 0x0,
  137. [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
  138. },
  139. },
  140. [ C(L1I ) ] = {
  141. [ C(OP_READ) ] = {
  142. [ C(RESULT_ACCESS) ] = 0x0,
  143. [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
  144. },
  145. [ C(OP_WRITE) ] = {
  146. [ C(RESULT_ACCESS) ] = -1,
  147. [ C(RESULT_MISS) ] = -1,
  148. },
  149. [ C(OP_PREFETCH) ] = {
  150. [ C(RESULT_ACCESS) ] = 0x0,
  151. [ C(RESULT_MISS) ] = 0x0,
  152. },
  153. },
  154. [ C(LL ) ] = {
  155. [ C(OP_READ) ] = {
  156. /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
  157. [ C(RESULT_ACCESS) ] = 0x01b7,
  158. /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
  159. [ C(RESULT_MISS) ] = 0x01b7,
  160. },
  161. [ C(OP_WRITE) ] = {
  162. /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
  163. [ C(RESULT_ACCESS) ] = 0x01b7,
  164. /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
  165. [ C(RESULT_MISS) ] = 0x01b7,
  166. },
  167. [ C(OP_PREFETCH) ] = {
  168. /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
  169. [ C(RESULT_ACCESS) ] = 0x01b7,
  170. /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
  171. [ C(RESULT_MISS) ] = 0x01b7,
  172. },
  173. },
  174. [ C(DTLB) ] = {
  175. [ C(OP_READ) ] = {
  176. [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
  177. [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
  178. },
  179. [ C(OP_WRITE) ] = {
  180. [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
  181. [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
  182. },
  183. [ C(OP_PREFETCH) ] = {
  184. [ C(RESULT_ACCESS) ] = 0x0,
  185. [ C(RESULT_MISS) ] = 0x0,
  186. },
  187. },
  188. [ C(ITLB) ] = {
  189. [ C(OP_READ) ] = {
  190. [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
  191. [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
  192. },
  193. [ C(OP_WRITE) ] = {
  194. [ C(RESULT_ACCESS) ] = -1,
  195. [ C(RESULT_MISS) ] = -1,
  196. },
  197. [ C(OP_PREFETCH) ] = {
  198. [ C(RESULT_ACCESS) ] = -1,
  199. [ C(RESULT_MISS) ] = -1,
  200. },
  201. },
  202. [ C(BPU ) ] = {
  203. [ C(OP_READ) ] = {
  204. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
  205. [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
  206. },
  207. [ C(OP_WRITE) ] = {
  208. [ C(RESULT_ACCESS) ] = -1,
  209. [ C(RESULT_MISS) ] = -1,
  210. },
  211. [ C(OP_PREFETCH) ] = {
  212. [ C(RESULT_ACCESS) ] = -1,
  213. [ C(RESULT_MISS) ] = -1,
  214. },
  215. },
  216. };
  217. static __initconst const u64 westmere_hw_cache_event_ids
  218. [PERF_COUNT_HW_CACHE_MAX]
  219. [PERF_COUNT_HW_CACHE_OP_MAX]
  220. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  221. {
  222. [ C(L1D) ] = {
  223. [ C(OP_READ) ] = {
  224. [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
  225. [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
  226. },
  227. [ C(OP_WRITE) ] = {
  228. [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
  229. [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
  230. },
  231. [ C(OP_PREFETCH) ] = {
  232. [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
  233. [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
  234. },
  235. },
  236. [ C(L1I ) ] = {
  237. [ C(OP_READ) ] = {
  238. [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
  239. [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
  240. },
  241. [ C(OP_WRITE) ] = {
  242. [ C(RESULT_ACCESS) ] = -1,
  243. [ C(RESULT_MISS) ] = -1,
  244. },
  245. [ C(OP_PREFETCH) ] = {
  246. [ C(RESULT_ACCESS) ] = 0x0,
  247. [ C(RESULT_MISS) ] = 0x0,
  248. },
  249. },
  250. [ C(LL ) ] = {
  251. [ C(OP_READ) ] = {
  252. /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
  253. [ C(RESULT_ACCESS) ] = 0x01b7,
  254. /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
  255. [ C(RESULT_MISS) ] = 0x01b7,
  256. },
  257. /*
  258. * Use RFO, not WRITEBACK, because a write miss would typically occur
  259. * on RFO.
  260. */
  261. [ C(OP_WRITE) ] = {
  262. /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
  263. [ C(RESULT_ACCESS) ] = 0x01b7,
  264. /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
  265. [ C(RESULT_MISS) ] = 0x01b7,
  266. },
  267. [ C(OP_PREFETCH) ] = {
  268. /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
  269. [ C(RESULT_ACCESS) ] = 0x01b7,
  270. /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
  271. [ C(RESULT_MISS) ] = 0x01b7,
  272. },
  273. },
  274. [ C(DTLB) ] = {
  275. [ C(OP_READ) ] = {
  276. [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
  277. [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
  278. },
  279. [ C(OP_WRITE) ] = {
  280. [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
  281. [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
  282. },
  283. [ C(OP_PREFETCH) ] = {
  284. [ C(RESULT_ACCESS) ] = 0x0,
  285. [ C(RESULT_MISS) ] = 0x0,
  286. },
  287. },
  288. [ C(ITLB) ] = {
  289. [ C(OP_READ) ] = {
  290. [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
  291. [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
  292. },
  293. [ C(OP_WRITE) ] = {
  294. [ C(RESULT_ACCESS) ] = -1,
  295. [ C(RESULT_MISS) ] = -1,
  296. },
  297. [ C(OP_PREFETCH) ] = {
  298. [ C(RESULT_ACCESS) ] = -1,
  299. [ C(RESULT_MISS) ] = -1,
  300. },
  301. },
  302. [ C(BPU ) ] = {
  303. [ C(OP_READ) ] = {
  304. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
  305. [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
  306. },
  307. [ C(OP_WRITE) ] = {
  308. [ C(RESULT_ACCESS) ] = -1,
  309. [ C(RESULT_MISS) ] = -1,
  310. },
  311. [ C(OP_PREFETCH) ] = {
  312. [ C(RESULT_ACCESS) ] = -1,
  313. [ C(RESULT_MISS) ] = -1,
  314. },
  315. },
  316. };
  317. /*
  318. * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
  319. * See IA32 SDM Vol 3B 30.6.1.3
  320. */
  321. #define NHM_DMND_DATA_RD (1 << 0)
  322. #define NHM_DMND_RFO (1 << 1)
  323. #define NHM_DMND_IFETCH (1 << 2)
  324. #define NHM_DMND_WB (1 << 3)
  325. #define NHM_PF_DATA_RD (1 << 4)
  326. #define NHM_PF_DATA_RFO (1 << 5)
  327. #define NHM_PF_IFETCH (1 << 6)
  328. #define NHM_OFFCORE_OTHER (1 << 7)
  329. #define NHM_UNCORE_HIT (1 << 8)
  330. #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
  331. #define NHM_OTHER_CORE_HITM (1 << 10)
  332. /* reserved */
  333. #define NHM_REMOTE_CACHE_FWD (1 << 12)
  334. #define NHM_REMOTE_DRAM (1 << 13)
  335. #define NHM_LOCAL_DRAM (1 << 14)
  336. #define NHM_NON_DRAM (1 << 15)
  337. #define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
  338. #define NHM_DMND_READ (NHM_DMND_DATA_RD)
  339. #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
  340. #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
  341. #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
  342. #define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
  343. #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
  344. static __initconst const u64 nehalem_hw_cache_extra_regs
  345. [PERF_COUNT_HW_CACHE_MAX]
  346. [PERF_COUNT_HW_CACHE_OP_MAX]
  347. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  348. {
  349. [ C(LL ) ] = {
  350. [ C(OP_READ) ] = {
  351. [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
  352. [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
  353. },
  354. [ C(OP_WRITE) ] = {
  355. [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
  356. [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
  357. },
  358. [ C(OP_PREFETCH) ] = {
  359. [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
  360. [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
  361. },
  362. }
  363. };
  364. static __initconst const u64 nehalem_hw_cache_event_ids
  365. [PERF_COUNT_HW_CACHE_MAX]
  366. [PERF_COUNT_HW_CACHE_OP_MAX]
  367. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  368. {
  369. [ C(L1D) ] = {
  370. [ C(OP_READ) ] = {
  371. [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
  372. [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
  373. },
  374. [ C(OP_WRITE) ] = {
  375. [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
  376. [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
  377. },
  378. [ C(OP_PREFETCH) ] = {
  379. [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
  380. [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
  381. },
  382. },
  383. [ C(L1I ) ] = {
  384. [ C(OP_READ) ] = {
  385. [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
  386. [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
  387. },
  388. [ C(OP_WRITE) ] = {
  389. [ C(RESULT_ACCESS) ] = -1,
  390. [ C(RESULT_MISS) ] = -1,
  391. },
  392. [ C(OP_PREFETCH) ] = {
  393. [ C(RESULT_ACCESS) ] = 0x0,
  394. [ C(RESULT_MISS) ] = 0x0,
  395. },
  396. },
  397. [ C(LL ) ] = {
  398. [ C(OP_READ) ] = {
  399. /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
  400. [ C(RESULT_ACCESS) ] = 0x01b7,
  401. /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
  402. [ C(RESULT_MISS) ] = 0x01b7,
  403. },
  404. /*
  405. * Use RFO, not WRITEBACK, because a write miss would typically occur
  406. * on RFO.
  407. */
  408. [ C(OP_WRITE) ] = {
  409. /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
  410. [ C(RESULT_ACCESS) ] = 0x01b7,
  411. /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
  412. [ C(RESULT_MISS) ] = 0x01b7,
  413. },
  414. [ C(OP_PREFETCH) ] = {
  415. /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
  416. [ C(RESULT_ACCESS) ] = 0x01b7,
  417. /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
  418. [ C(RESULT_MISS) ] = 0x01b7,
  419. },
  420. },
  421. [ C(DTLB) ] = {
  422. [ C(OP_READ) ] = {
  423. [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
  424. [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
  425. },
  426. [ C(OP_WRITE) ] = {
  427. [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
  428. [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
  429. },
  430. [ C(OP_PREFETCH) ] = {
  431. [ C(RESULT_ACCESS) ] = 0x0,
  432. [ C(RESULT_MISS) ] = 0x0,
  433. },
  434. },
  435. [ C(ITLB) ] = {
  436. [ C(OP_READ) ] = {
  437. [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
  438. [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
  439. },
  440. [ C(OP_WRITE) ] = {
  441. [ C(RESULT_ACCESS) ] = -1,
  442. [ C(RESULT_MISS) ] = -1,
  443. },
  444. [ C(OP_PREFETCH) ] = {
  445. [ C(RESULT_ACCESS) ] = -1,
  446. [ C(RESULT_MISS) ] = -1,
  447. },
  448. },
  449. [ C(BPU ) ] = {
  450. [ C(OP_READ) ] = {
  451. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
  452. [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
  453. },
  454. [ C(OP_WRITE) ] = {
  455. [ C(RESULT_ACCESS) ] = -1,
  456. [ C(RESULT_MISS) ] = -1,
  457. },
  458. [ C(OP_PREFETCH) ] = {
  459. [ C(RESULT_ACCESS) ] = -1,
  460. [ C(RESULT_MISS) ] = -1,
  461. },
  462. },
  463. };
  464. static __initconst const u64 core2_hw_cache_event_ids
  465. [PERF_COUNT_HW_CACHE_MAX]
  466. [PERF_COUNT_HW_CACHE_OP_MAX]
  467. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  468. {
  469. [ C(L1D) ] = {
  470. [ C(OP_READ) ] = {
  471. [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
  472. [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
  473. },
  474. [ C(OP_WRITE) ] = {
  475. [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
  476. [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
  477. },
  478. [ C(OP_PREFETCH) ] = {
  479. [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
  480. [ C(RESULT_MISS) ] = 0,
  481. },
  482. },
  483. [ C(L1I ) ] = {
  484. [ C(OP_READ) ] = {
  485. [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
  486. [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
  487. },
  488. [ C(OP_WRITE) ] = {
  489. [ C(RESULT_ACCESS) ] = -1,
  490. [ C(RESULT_MISS) ] = -1,
  491. },
  492. [ C(OP_PREFETCH) ] = {
  493. [ C(RESULT_ACCESS) ] = 0,
  494. [ C(RESULT_MISS) ] = 0,
  495. },
  496. },
  497. [ C(LL ) ] = {
  498. [ C(OP_READ) ] = {
  499. [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
  500. [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
  501. },
  502. [ C(OP_WRITE) ] = {
  503. [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
  504. [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
  505. },
  506. [ C(OP_PREFETCH) ] = {
  507. [ C(RESULT_ACCESS) ] = 0,
  508. [ C(RESULT_MISS) ] = 0,
  509. },
  510. },
  511. [ C(DTLB) ] = {
  512. [ C(OP_READ) ] = {
  513. [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
  514. [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
  515. },
  516. [ C(OP_WRITE) ] = {
  517. [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
  518. [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
  519. },
  520. [ C(OP_PREFETCH) ] = {
  521. [ C(RESULT_ACCESS) ] = 0,
  522. [ C(RESULT_MISS) ] = 0,
  523. },
  524. },
  525. [ C(ITLB) ] = {
  526. [ C(OP_READ) ] = {
  527. [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
  528. [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
  529. },
  530. [ C(OP_WRITE) ] = {
  531. [ C(RESULT_ACCESS) ] = -1,
  532. [ C(RESULT_MISS) ] = -1,
  533. },
  534. [ C(OP_PREFETCH) ] = {
  535. [ C(RESULT_ACCESS) ] = -1,
  536. [ C(RESULT_MISS) ] = -1,
  537. },
  538. },
  539. [ C(BPU ) ] = {
  540. [ C(OP_READ) ] = {
  541. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
  542. [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
  543. },
  544. [ C(OP_WRITE) ] = {
  545. [ C(RESULT_ACCESS) ] = -1,
  546. [ C(RESULT_MISS) ] = -1,
  547. },
  548. [ C(OP_PREFETCH) ] = {
  549. [ C(RESULT_ACCESS) ] = -1,
  550. [ C(RESULT_MISS) ] = -1,
  551. },
  552. },
  553. };
  554. static __initconst const u64 atom_hw_cache_event_ids
  555. [PERF_COUNT_HW_CACHE_MAX]
  556. [PERF_COUNT_HW_CACHE_OP_MAX]
  557. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  558. {
  559. [ C(L1D) ] = {
  560. [ C(OP_READ) ] = {
  561. [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
  562. [ C(RESULT_MISS) ] = 0,
  563. },
  564. [ C(OP_WRITE) ] = {
  565. [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
  566. [ C(RESULT_MISS) ] = 0,
  567. },
  568. [ C(OP_PREFETCH) ] = {
  569. [ C(RESULT_ACCESS) ] = 0x0,
  570. [ C(RESULT_MISS) ] = 0,
  571. },
  572. },
  573. [ C(L1I ) ] = {
  574. [ C(OP_READ) ] = {
  575. [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
  576. [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
  577. },
  578. [ C(OP_WRITE) ] = {
  579. [ C(RESULT_ACCESS) ] = -1,
  580. [ C(RESULT_MISS) ] = -1,
  581. },
  582. [ C(OP_PREFETCH) ] = {
  583. [ C(RESULT_ACCESS) ] = 0,
  584. [ C(RESULT_MISS) ] = 0,
  585. },
  586. },
  587. [ C(LL ) ] = {
  588. [ C(OP_READ) ] = {
  589. [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
  590. [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
  591. },
  592. [ C(OP_WRITE) ] = {
  593. [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
  594. [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
  595. },
  596. [ C(OP_PREFETCH) ] = {
  597. [ C(RESULT_ACCESS) ] = 0,
  598. [ C(RESULT_MISS) ] = 0,
  599. },
  600. },
  601. [ C(DTLB) ] = {
  602. [ C(OP_READ) ] = {
  603. [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
  604. [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
  605. },
  606. [ C(OP_WRITE) ] = {
  607. [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
  608. [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
  609. },
  610. [ C(OP_PREFETCH) ] = {
  611. [ C(RESULT_ACCESS) ] = 0,
  612. [ C(RESULT_MISS) ] = 0,
  613. },
  614. },
  615. [ C(ITLB) ] = {
  616. [ C(OP_READ) ] = {
  617. [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
  618. [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
  619. },
  620. [ C(OP_WRITE) ] = {
  621. [ C(RESULT_ACCESS) ] = -1,
  622. [ C(RESULT_MISS) ] = -1,
  623. },
  624. [ C(OP_PREFETCH) ] = {
  625. [ C(RESULT_ACCESS) ] = -1,
  626. [ C(RESULT_MISS) ] = -1,
  627. },
  628. },
  629. [ C(BPU ) ] = {
  630. [ C(OP_READ) ] = {
  631. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
  632. [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
  633. },
  634. [ C(OP_WRITE) ] = {
  635. [ C(RESULT_ACCESS) ] = -1,
  636. [ C(RESULT_MISS) ] = -1,
  637. },
  638. [ C(OP_PREFETCH) ] = {
  639. [ C(RESULT_ACCESS) ] = -1,
  640. [ C(RESULT_MISS) ] = -1,
  641. },
  642. },
  643. };
  644. static void intel_pmu_disable_all(void)
  645. {
  646. struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
  647. wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
  648. if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
  649. intel_pmu_disable_bts();
  650. intel_pmu_pebs_disable_all();
  651. intel_pmu_lbr_disable_all();
  652. }
  653. static void intel_pmu_enable_all(int added)
  654. {
  655. struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
  656. intel_pmu_pebs_enable_all();
  657. intel_pmu_lbr_enable_all();
  658. wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
  659. if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
  660. struct perf_event *event =
  661. cpuc->events[X86_PMC_IDX_FIXED_BTS];
  662. if (WARN_ON_ONCE(!event))
  663. return;
  664. intel_pmu_enable_bts(event->hw.config);
  665. }
  666. }
  667. /*
  668. * Workaround for:
  669. * Intel Errata AAK100 (model 26)
  670. * Intel Errata AAP53 (model 30)
  671. * Intel Errata BD53 (model 44)
  672. *
  673. * The official story:
  674. * These chips need to be 'reset' when adding counters by programming the
  675. * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
  676. * in sequence on the same PMC or on different PMCs.
  677. *
  678. * In practise it appears some of these events do in fact count, and
  679. * we need to programm all 4 events.
  680. */
  681. static void intel_pmu_nhm_workaround(void)
  682. {
  683. struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
  684. static const unsigned long nhm_magic[4] = {
  685. 0x4300B5,
  686. 0x4300D2,
  687. 0x4300B1,
  688. 0x4300B1
  689. };
  690. struct perf_event *event;
  691. int i;
  692. /*
  693. * The Errata requires below steps:
  694. * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
  695. * 2) Configure 4 PERFEVTSELx with the magic events and clear
  696. * the corresponding PMCx;
  697. * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
  698. * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
  699. * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
  700. */
  701. /*
  702. * The real steps we choose are a little different from above.
  703. * A) To reduce MSR operations, we don't run step 1) as they
  704. * are already cleared before this function is called;
  705. * B) Call x86_perf_event_update to save PMCx before configuring
  706. * PERFEVTSELx with magic number;
  707. * C) With step 5), we do clear only when the PERFEVTSELx is
  708. * not used currently.
  709. * D) Call x86_perf_event_set_period to restore PMCx;
  710. */
  711. /* We always operate 4 pairs of PERF Counters */
  712. for (i = 0; i < 4; i++) {
  713. event = cpuc->events[i];
  714. if (event)
  715. x86_perf_event_update(event);
  716. }
  717. for (i = 0; i < 4; i++) {
  718. wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
  719. wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
  720. }
  721. wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
  722. wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
  723. for (i = 0; i < 4; i++) {
  724. event = cpuc->events[i];
  725. if (event) {
  726. x86_perf_event_set_period(event);
  727. __x86_pmu_enable_event(&event->hw,
  728. ARCH_PERFMON_EVENTSEL_ENABLE);
  729. } else
  730. wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
  731. }
  732. }
  733. static void intel_pmu_nhm_enable_all(int added)
  734. {
  735. if (added)
  736. intel_pmu_nhm_workaround();
  737. intel_pmu_enable_all(added);
  738. }
  739. static inline u64 intel_pmu_get_status(void)
  740. {
  741. u64 status;
  742. rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
  743. return status;
  744. }
  745. static inline void intel_pmu_ack_status(u64 ack)
  746. {
  747. wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
  748. }
  749. static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
  750. {
  751. int idx = hwc->idx - X86_PMC_IDX_FIXED;
  752. u64 ctrl_val, mask;
  753. mask = 0xfULL << (idx * 4);
  754. rdmsrl(hwc->config_base, ctrl_val);
  755. ctrl_val &= ~mask;
  756. wrmsrl(hwc->config_base, ctrl_val);
  757. }
  758. static void intel_pmu_disable_event(struct perf_event *event)
  759. {
  760. struct hw_perf_event *hwc = &event->hw;
  761. if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
  762. intel_pmu_disable_bts();
  763. intel_pmu_drain_bts_buffer();
  764. return;
  765. }
  766. if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
  767. intel_pmu_disable_fixed(hwc);
  768. return;
  769. }
  770. x86_pmu_disable_event(event);
  771. if (unlikely(event->attr.precise_ip))
  772. intel_pmu_pebs_disable(event);
  773. }
  774. static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
  775. {
  776. int idx = hwc->idx - X86_PMC_IDX_FIXED;
  777. u64 ctrl_val, bits, mask;
  778. /*
  779. * Enable IRQ generation (0x8),
  780. * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
  781. * if requested:
  782. */
  783. bits = 0x8ULL;
  784. if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
  785. bits |= 0x2;
  786. if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
  787. bits |= 0x1;
  788. /*
  789. * ANY bit is supported in v3 and up
  790. */
  791. if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
  792. bits |= 0x4;
  793. bits <<= (idx * 4);
  794. mask = 0xfULL << (idx * 4);
  795. rdmsrl(hwc->config_base, ctrl_val);
  796. ctrl_val &= ~mask;
  797. ctrl_val |= bits;
  798. wrmsrl(hwc->config_base, ctrl_val);
  799. }
  800. static void intel_pmu_enable_event(struct perf_event *event)
  801. {
  802. struct hw_perf_event *hwc = &event->hw;
  803. if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
  804. if (!__this_cpu_read(cpu_hw_events.enabled))
  805. return;
  806. intel_pmu_enable_bts(hwc->config);
  807. return;
  808. }
  809. if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
  810. intel_pmu_enable_fixed(hwc);
  811. return;
  812. }
  813. if (unlikely(event->attr.precise_ip))
  814. intel_pmu_pebs_enable(event);
  815. __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
  816. }
  817. /*
  818. * Save and restart an expired event. Called by NMI contexts,
  819. * so it has to be careful about preempting normal event ops:
  820. */
  821. static int intel_pmu_save_and_restart(struct perf_event *event)
  822. {
  823. x86_perf_event_update(event);
  824. return x86_perf_event_set_period(event);
  825. }
  826. static void intel_pmu_reset(void)
  827. {
  828. struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
  829. unsigned long flags;
  830. int idx;
  831. if (!x86_pmu.num_counters)
  832. return;
  833. local_irq_save(flags);
  834. printk("clearing PMU state on CPU#%d\n", smp_processor_id());
  835. for (idx = 0; idx < x86_pmu.num_counters; idx++) {
  836. checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
  837. checking_wrmsrl(x86_pmu_event_addr(idx), 0ull);
  838. }
  839. for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
  840. checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
  841. if (ds)
  842. ds->bts_index = ds->bts_buffer_base;
  843. local_irq_restore(flags);
  844. }
  845. /*
  846. * This handler is triggered by the local APIC, so the APIC IRQ handling
  847. * rules apply:
  848. */
  849. static int intel_pmu_handle_irq(struct pt_regs *regs)
  850. {
  851. struct perf_sample_data data;
  852. struct cpu_hw_events *cpuc;
  853. int bit, loops;
  854. u64 status;
  855. int handled;
  856. perf_sample_data_init(&data, 0);
  857. cpuc = &__get_cpu_var(cpu_hw_events);
  858. /*
  859. * Some chipsets need to unmask the LVTPC in a particular spot
  860. * inside the nmi handler. As a result, the unmasking was pushed
  861. * into all the nmi handlers.
  862. *
  863. * This handler doesn't seem to have any issues with the unmasking
  864. * so it was left at the top.
  865. */
  866. apic_write(APIC_LVTPC, APIC_DM_NMI);
  867. intel_pmu_disable_all();
  868. handled = intel_pmu_drain_bts_buffer();
  869. status = intel_pmu_get_status();
  870. if (!status) {
  871. intel_pmu_enable_all(0);
  872. return handled;
  873. }
  874. loops = 0;
  875. again:
  876. intel_pmu_ack_status(status);
  877. if (++loops > 100) {
  878. WARN_ONCE(1, "perfevents: irq loop stuck!\n");
  879. perf_event_print_debug();
  880. intel_pmu_reset();
  881. goto done;
  882. }
  883. inc_irq_stat(apic_perf_irqs);
  884. intel_pmu_lbr_read();
  885. /*
  886. * PEBS overflow sets bit 62 in the global status register
  887. */
  888. if (__test_and_clear_bit(62, (unsigned long *)&status)) {
  889. handled++;
  890. x86_pmu.drain_pebs(regs);
  891. }
  892. for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
  893. struct perf_event *event = cpuc->events[bit];
  894. handled++;
  895. if (!test_bit(bit, cpuc->active_mask))
  896. continue;
  897. if (!intel_pmu_save_and_restart(event))
  898. continue;
  899. data.period = event->hw.last_period;
  900. if (perf_event_overflow(event, &data, regs))
  901. x86_pmu_stop(event, 0);
  902. }
  903. /*
  904. * Repeat if there is more work to be done:
  905. */
  906. status = intel_pmu_get_status();
  907. if (status)
  908. goto again;
  909. done:
  910. intel_pmu_enable_all(0);
  911. return handled;
  912. }
  913. static struct event_constraint *
  914. intel_bts_constraints(struct perf_event *event)
  915. {
  916. struct hw_perf_event *hwc = &event->hw;
  917. unsigned int hw_event, bts_event;
  918. if (event->attr.freq)
  919. return NULL;
  920. hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
  921. bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
  922. if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
  923. return &bts_constraint;
  924. return NULL;
  925. }
  926. static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
  927. {
  928. if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
  929. return false;
  930. if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
  931. event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
  932. event->hw.config |= 0x01bb;
  933. event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
  934. event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
  935. } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
  936. event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
  937. event->hw.config |= 0x01b7;
  938. event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
  939. event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
  940. }
  941. if (event->hw.extra_reg.idx == orig_idx)
  942. return false;
  943. return true;
  944. }
  945. /*
  946. * manage allocation of shared extra msr for certain events
  947. *
  948. * sharing can be:
  949. * per-cpu: to be shared between the various events on a single PMU
  950. * per-core: per-cpu + shared by HT threads
  951. */
  952. static struct event_constraint *
  953. __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
  954. struct perf_event *event)
  955. {
  956. struct event_constraint *c = &emptyconstraint;
  957. struct hw_perf_event_extra *reg = &event->hw.extra_reg;
  958. struct er_account *era;
  959. unsigned long flags;
  960. int orig_idx = reg->idx;
  961. /* already allocated shared msr */
  962. if (reg->alloc)
  963. return &unconstrained;
  964. again:
  965. era = &cpuc->shared_regs->regs[reg->idx];
  966. /*
  967. * we use spin_lock_irqsave() to avoid lockdep issues when
  968. * passing a fake cpuc
  969. */
  970. raw_spin_lock_irqsave(&era->lock, flags);
  971. if (!atomic_read(&era->ref) || era->config == reg->config) {
  972. /* lock in msr value */
  973. era->config = reg->config;
  974. era->reg = reg->reg;
  975. /* one more user */
  976. atomic_inc(&era->ref);
  977. /* no need to reallocate during incremental event scheduling */
  978. reg->alloc = 1;
  979. /*
  980. * All events using extra_reg are unconstrained.
  981. * Avoids calling x86_get_event_constraints()
  982. *
  983. * Must revisit if extra_reg controlling events
  984. * ever have constraints. Worst case we go through
  985. * the regular event constraint table.
  986. */
  987. c = &unconstrained;
  988. } else if (intel_try_alt_er(event, orig_idx)) {
  989. raw_spin_unlock(&era->lock);
  990. goto again;
  991. }
  992. raw_spin_unlock_irqrestore(&era->lock, flags);
  993. return c;
  994. }
  995. static void
  996. __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
  997. struct hw_perf_event_extra *reg)
  998. {
  999. struct er_account *era;
  1000. /*
  1001. * only put constraint if extra reg was actually
  1002. * allocated. Also takes care of event which do
  1003. * not use an extra shared reg
  1004. */
  1005. if (!reg->alloc)
  1006. return;
  1007. era = &cpuc->shared_regs->regs[reg->idx];
  1008. /* one fewer user */
  1009. atomic_dec(&era->ref);
  1010. /* allocate again next time */
  1011. reg->alloc = 0;
  1012. }
  1013. static struct event_constraint *
  1014. intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
  1015. struct perf_event *event)
  1016. {
  1017. struct event_constraint *c = NULL;
  1018. if (event->hw.extra_reg.idx != EXTRA_REG_NONE)
  1019. c = __intel_shared_reg_get_constraints(cpuc, event);
  1020. return c;
  1021. }
  1022. static struct event_constraint *
  1023. intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
  1024. {
  1025. struct event_constraint *c;
  1026. c = intel_bts_constraints(event);
  1027. if (c)
  1028. return c;
  1029. c = intel_pebs_constraints(event);
  1030. if (c)
  1031. return c;
  1032. c = intel_shared_regs_constraints(cpuc, event);
  1033. if (c)
  1034. return c;
  1035. return x86_get_event_constraints(cpuc, event);
  1036. }
  1037. static void
  1038. intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
  1039. struct perf_event *event)
  1040. {
  1041. struct hw_perf_event_extra *reg;
  1042. reg = &event->hw.extra_reg;
  1043. if (reg->idx != EXTRA_REG_NONE)
  1044. __intel_shared_reg_put_constraints(cpuc, reg);
  1045. }
  1046. static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
  1047. struct perf_event *event)
  1048. {
  1049. intel_put_shared_regs_event_constraints(cpuc, event);
  1050. }
  1051. static int intel_pmu_hw_config(struct perf_event *event)
  1052. {
  1053. int ret = x86_pmu_hw_config(event);
  1054. if (ret)
  1055. return ret;
  1056. if (event->attr.precise_ip &&
  1057. (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
  1058. /*
  1059. * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
  1060. * (0x003c) so that we can use it with PEBS.
  1061. *
  1062. * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
  1063. * PEBS capable. However we can use INST_RETIRED.ANY_P
  1064. * (0x00c0), which is a PEBS capable event, to get the same
  1065. * count.
  1066. *
  1067. * INST_RETIRED.ANY_P counts the number of cycles that retires
  1068. * CNTMASK instructions. By setting CNTMASK to a value (16)
  1069. * larger than the maximum number of instructions that can be
  1070. * retired per cycle (4) and then inverting the condition, we
  1071. * count all cycles that retire 16 or less instructions, which
  1072. * is every cycle.
  1073. *
  1074. * Thereby we gain a PEBS capable cycle counter.
  1075. */
  1076. u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
  1077. alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
  1078. event->hw.config = alt_config;
  1079. }
  1080. if (event->attr.type != PERF_TYPE_RAW)
  1081. return 0;
  1082. if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
  1083. return 0;
  1084. if (x86_pmu.version < 3)
  1085. return -EINVAL;
  1086. if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
  1087. return -EACCES;
  1088. event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
  1089. return 0;
  1090. }
  1091. static __initconst const struct x86_pmu core_pmu = {
  1092. .name = "core",
  1093. .handle_irq = x86_pmu_handle_irq,
  1094. .disable_all = x86_pmu_disable_all,
  1095. .enable_all = x86_pmu_enable_all,
  1096. .enable = x86_pmu_enable_event,
  1097. .disable = x86_pmu_disable_event,
  1098. .hw_config = x86_pmu_hw_config,
  1099. .schedule_events = x86_schedule_events,
  1100. .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
  1101. .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
  1102. .event_map = intel_pmu_event_map,
  1103. .max_events = ARRAY_SIZE(intel_perfmon_event_map),
  1104. .apic = 1,
  1105. /*
  1106. * Intel PMCs cannot be accessed sanely above 32 bit width,
  1107. * so we install an artificial 1<<31 period regardless of
  1108. * the generic event period:
  1109. */
  1110. .max_period = (1ULL << 31) - 1,
  1111. .get_event_constraints = intel_get_event_constraints,
  1112. .put_event_constraints = intel_put_event_constraints,
  1113. .event_constraints = intel_core_event_constraints,
  1114. };
  1115. static struct intel_shared_regs *allocate_shared_regs(int cpu)
  1116. {
  1117. struct intel_shared_regs *regs;
  1118. int i;
  1119. regs = kzalloc_node(sizeof(struct intel_shared_regs),
  1120. GFP_KERNEL, cpu_to_node(cpu));
  1121. if (regs) {
  1122. /*
  1123. * initialize the locks to keep lockdep happy
  1124. */
  1125. for (i = 0; i < EXTRA_REG_MAX; i++)
  1126. raw_spin_lock_init(&regs->regs[i].lock);
  1127. regs->core_id = -1;
  1128. }
  1129. return regs;
  1130. }
  1131. static int intel_pmu_cpu_prepare(int cpu)
  1132. {
  1133. struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
  1134. if (!x86_pmu.extra_regs)
  1135. return NOTIFY_OK;
  1136. cpuc->shared_regs = allocate_shared_regs(cpu);
  1137. if (!cpuc->shared_regs)
  1138. return NOTIFY_BAD;
  1139. return NOTIFY_OK;
  1140. }
  1141. static void intel_pmu_cpu_starting(int cpu)
  1142. {
  1143. struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
  1144. int core_id = topology_core_id(cpu);
  1145. int i;
  1146. init_debug_store_on_cpu(cpu);
  1147. /*
  1148. * Deal with CPUs that don't clear their LBRs on power-up.
  1149. */
  1150. intel_pmu_lbr_reset();
  1151. if (!cpuc->shared_regs || (x86_pmu.er_flags & ERF_NO_HT_SHARING))
  1152. return;
  1153. for_each_cpu(i, topology_thread_cpumask(cpu)) {
  1154. struct intel_shared_regs *pc;
  1155. pc = per_cpu(cpu_hw_events, i).shared_regs;
  1156. if (pc && pc->core_id == core_id) {
  1157. kfree(cpuc->shared_regs);
  1158. cpuc->shared_regs = pc;
  1159. break;
  1160. }
  1161. }
  1162. cpuc->shared_regs->core_id = core_id;
  1163. cpuc->shared_regs->refcnt++;
  1164. }
  1165. static void intel_pmu_cpu_dying(int cpu)
  1166. {
  1167. struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
  1168. struct intel_shared_regs *pc;
  1169. pc = cpuc->shared_regs;
  1170. if (pc) {
  1171. if (pc->core_id == -1 || --pc->refcnt == 0)
  1172. kfree(pc);
  1173. cpuc->shared_regs = NULL;
  1174. }
  1175. fini_debug_store_on_cpu(cpu);
  1176. }
  1177. static __initconst const struct x86_pmu intel_pmu = {
  1178. .name = "Intel",
  1179. .handle_irq = intel_pmu_handle_irq,
  1180. .disable_all = intel_pmu_disable_all,
  1181. .enable_all = intel_pmu_enable_all,
  1182. .enable = intel_pmu_enable_event,
  1183. .disable = intel_pmu_disable_event,
  1184. .hw_config = intel_pmu_hw_config,
  1185. .schedule_events = x86_schedule_events,
  1186. .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
  1187. .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
  1188. .event_map = intel_pmu_event_map,
  1189. .max_events = ARRAY_SIZE(intel_perfmon_event_map),
  1190. .apic = 1,
  1191. /*
  1192. * Intel PMCs cannot be accessed sanely above 32 bit width,
  1193. * so we install an artificial 1<<31 period regardless of
  1194. * the generic event period:
  1195. */
  1196. .max_period = (1ULL << 31) - 1,
  1197. .get_event_constraints = intel_get_event_constraints,
  1198. .put_event_constraints = intel_put_event_constraints,
  1199. .cpu_prepare = intel_pmu_cpu_prepare,
  1200. .cpu_starting = intel_pmu_cpu_starting,
  1201. .cpu_dying = intel_pmu_cpu_dying,
  1202. };
  1203. static void intel_clovertown_quirks(void)
  1204. {
  1205. /*
  1206. * PEBS is unreliable due to:
  1207. *
  1208. * AJ67 - PEBS may experience CPL leaks
  1209. * AJ68 - PEBS PMI may be delayed by one event
  1210. * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
  1211. * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
  1212. *
  1213. * AJ67 could be worked around by restricting the OS/USR flags.
  1214. * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
  1215. *
  1216. * AJ106 could possibly be worked around by not allowing LBR
  1217. * usage from PEBS, including the fixup.
  1218. * AJ68 could possibly be worked around by always programming
  1219. * a pebs_event_reset[0] value and coping with the lost events.
  1220. *
  1221. * But taken together it might just make sense to not enable PEBS on
  1222. * these chips.
  1223. */
  1224. printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
  1225. x86_pmu.pebs = 0;
  1226. x86_pmu.pebs_constraints = NULL;
  1227. }
  1228. static __init int intel_pmu_init(void)
  1229. {
  1230. union cpuid10_edx edx;
  1231. union cpuid10_eax eax;
  1232. unsigned int unused;
  1233. unsigned int ebx;
  1234. int version;
  1235. if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
  1236. switch (boot_cpu_data.x86) {
  1237. case 0x6:
  1238. return p6_pmu_init();
  1239. case 0xf:
  1240. return p4_pmu_init();
  1241. }
  1242. return -ENODEV;
  1243. }
  1244. /*
  1245. * Check whether the Architectural PerfMon supports
  1246. * Branch Misses Retired hw_event or not.
  1247. */
  1248. cpuid(10, &eax.full, &ebx, &unused, &edx.full);
  1249. if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
  1250. return -ENODEV;
  1251. version = eax.split.version_id;
  1252. if (version < 2)
  1253. x86_pmu = core_pmu;
  1254. else
  1255. x86_pmu = intel_pmu;
  1256. x86_pmu.version = version;
  1257. x86_pmu.num_counters = eax.split.num_counters;
  1258. x86_pmu.cntval_bits = eax.split.bit_width;
  1259. x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
  1260. /*
  1261. * Quirk: v2 perfmon does not report fixed-purpose events, so
  1262. * assume at least 3 events:
  1263. */
  1264. if (version > 1)
  1265. x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
  1266. /*
  1267. * v2 and above have a perf capabilities MSR
  1268. */
  1269. if (version > 1) {
  1270. u64 capabilities;
  1271. rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
  1272. x86_pmu.intel_cap.capabilities = capabilities;
  1273. }
  1274. intel_ds_init();
  1275. /*
  1276. * Install the hw-cache-events table:
  1277. */
  1278. switch (boot_cpu_data.x86_model) {
  1279. case 14: /* 65 nm core solo/duo, "Yonah" */
  1280. pr_cont("Core events, ");
  1281. break;
  1282. case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
  1283. x86_pmu.quirks = intel_clovertown_quirks;
  1284. case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
  1285. case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
  1286. case 29: /* six-core 45 nm xeon "Dunnington" */
  1287. memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
  1288. sizeof(hw_cache_event_ids));
  1289. intel_pmu_lbr_init_core();
  1290. x86_pmu.event_constraints = intel_core2_event_constraints;
  1291. x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
  1292. pr_cont("Core2 events, ");
  1293. break;
  1294. case 26: /* 45 nm nehalem, "Bloomfield" */
  1295. case 30: /* 45 nm nehalem, "Lynnfield" */
  1296. case 46: /* 45 nm nehalem-ex, "Beckton" */
  1297. memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
  1298. sizeof(hw_cache_event_ids));
  1299. memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
  1300. sizeof(hw_cache_extra_regs));
  1301. intel_pmu_lbr_init_nhm();
  1302. x86_pmu.event_constraints = intel_nehalem_event_constraints;
  1303. x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
  1304. x86_pmu.enable_all = intel_pmu_nhm_enable_all;
  1305. x86_pmu.extra_regs = intel_nehalem_extra_regs;
  1306. /* UOPS_ISSUED.STALLED_CYCLES */
  1307. intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
  1308. /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
  1309. intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
  1310. if (ebx & 0x40) {
  1311. /*
  1312. * Erratum AAJ80 detected, we work it around by using
  1313. * the BR_MISP_EXEC.ANY event. This will over-count
  1314. * branch-misses, but it's still much better than the
  1315. * architectural event which is often completely bogus:
  1316. */
  1317. intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
  1318. pr_cont("erratum AAJ80 worked around, ");
  1319. }
  1320. pr_cont("Nehalem events, ");
  1321. break;
  1322. case 28: /* Atom */
  1323. memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
  1324. sizeof(hw_cache_event_ids));
  1325. intel_pmu_lbr_init_atom();
  1326. x86_pmu.event_constraints = intel_gen_event_constraints;
  1327. x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
  1328. pr_cont("Atom events, ");
  1329. break;
  1330. case 37: /* 32 nm nehalem, "Clarkdale" */
  1331. case 44: /* 32 nm nehalem, "Gulftown" */
  1332. case 47: /* 32 nm Xeon E7 */
  1333. memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
  1334. sizeof(hw_cache_event_ids));
  1335. memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
  1336. sizeof(hw_cache_extra_regs));
  1337. intel_pmu_lbr_init_nhm();
  1338. x86_pmu.event_constraints = intel_westmere_event_constraints;
  1339. x86_pmu.enable_all = intel_pmu_nhm_enable_all;
  1340. x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
  1341. x86_pmu.extra_regs = intel_westmere_extra_regs;
  1342. x86_pmu.er_flags |= ERF_HAS_RSP_1;
  1343. /* UOPS_ISSUED.STALLED_CYCLES */
  1344. intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
  1345. /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
  1346. intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
  1347. pr_cont("Westmere events, ");
  1348. break;
  1349. case 42: /* SandyBridge */
  1350. memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
  1351. sizeof(hw_cache_event_ids));
  1352. intel_pmu_lbr_init_nhm();
  1353. x86_pmu.event_constraints = intel_snb_event_constraints;
  1354. x86_pmu.pebs_constraints = intel_snb_pebs_events;
  1355. x86_pmu.extra_regs = intel_snb_extra_regs;
  1356. /* all extra regs are per-cpu when HT is on */
  1357. x86_pmu.er_flags |= ERF_HAS_RSP_1;
  1358. x86_pmu.er_flags |= ERF_NO_HT_SHARING;
  1359. /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
  1360. intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
  1361. /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
  1362. intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
  1363. pr_cont("SandyBridge events, ");
  1364. break;
  1365. default:
  1366. /*
  1367. * default constraints for v2 and up
  1368. */
  1369. x86_pmu.event_constraints = intel_gen_event_constraints;
  1370. pr_cont("generic architected perfmon, ");
  1371. }
  1372. return 0;
  1373. }
  1374. #else /* CONFIG_CPU_SUP_INTEL */
  1375. static int intel_pmu_init(void)
  1376. {
  1377. return 0;
  1378. }
  1379. static struct intel_shared_regs *allocate_shared_regs(int cpu)
  1380. {
  1381. return NULL;
  1382. }
  1383. #endif /* CONFIG_CPU_SUP_INTEL */