mtd.c 16 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2010 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/module.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/rtnetlink.h>
  16. #include "net_driver.h"
  17. #include "spi.h"
  18. #include "efx.h"
  19. #include "nic.h"
  20. #include "mcdi.h"
  21. #include "mcdi_pcol.h"
  22. #define FALCON_SPI_VERIFY_BUF_LEN 16
  23. struct efx_mtd_partition {
  24. struct list_head node;
  25. struct mtd_info mtd;
  26. union {
  27. struct {
  28. bool updating;
  29. u8 nvram_type;
  30. u16 fw_subtype;
  31. } mcdi;
  32. struct {
  33. const struct falcon_spi_device *spi;
  34. size_t offset;
  35. } falcon;
  36. };
  37. const char *dev_type_name;
  38. const char *type_name;
  39. char name[IFNAMSIZ + 20];
  40. };
  41. struct efx_mtd_ops {
  42. int (*read)(struct mtd_info *mtd, loff_t start, size_t len,
  43. size_t *retlen, u8 *buffer);
  44. int (*erase)(struct mtd_info *mtd, loff_t start, size_t len);
  45. int (*write)(struct mtd_info *mtd, loff_t start, size_t len,
  46. size_t *retlen, const u8 *buffer);
  47. int (*sync)(struct mtd_info *mtd);
  48. };
  49. #define to_efx_mtd_partition(mtd) \
  50. container_of(mtd, struct efx_mtd_partition, mtd)
  51. static int falcon_mtd_probe(struct efx_nic *efx);
  52. static int siena_mtd_probe(struct efx_nic *efx);
  53. /* SPI utilities */
  54. static int
  55. falcon_spi_slow_wait(struct efx_mtd_partition *part, bool uninterruptible)
  56. {
  57. const struct falcon_spi_device *spi = part->falcon.spi;
  58. struct efx_nic *efx = part->mtd.priv;
  59. u8 status;
  60. int rc, i;
  61. /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
  62. for (i = 0; i < 40; i++) {
  63. __set_current_state(uninterruptible ?
  64. TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
  65. schedule_timeout(HZ / 10);
  66. rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
  67. &status, sizeof(status));
  68. if (rc)
  69. return rc;
  70. if (!(status & SPI_STATUS_NRDY))
  71. return 0;
  72. if (signal_pending(current))
  73. return -EINTR;
  74. }
  75. pr_err("%s: timed out waiting for %s\n",
  76. part->name, part->dev_type_name);
  77. return -ETIMEDOUT;
  78. }
  79. static int
  80. falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi)
  81. {
  82. const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
  83. SPI_STATUS_BP0);
  84. u8 status;
  85. int rc;
  86. rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
  87. &status, sizeof(status));
  88. if (rc)
  89. return rc;
  90. if (!(status & unlock_mask))
  91. return 0; /* already unlocked */
  92. rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
  93. if (rc)
  94. return rc;
  95. rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
  96. if (rc)
  97. return rc;
  98. status &= ~unlock_mask;
  99. rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
  100. NULL, sizeof(status));
  101. if (rc)
  102. return rc;
  103. rc = falcon_spi_wait_write(efx, spi);
  104. if (rc)
  105. return rc;
  106. return 0;
  107. }
  108. static int
  109. falcon_spi_erase(struct efx_mtd_partition *part, loff_t start, size_t len)
  110. {
  111. const struct falcon_spi_device *spi = part->falcon.spi;
  112. struct efx_nic *efx = part->mtd.priv;
  113. unsigned pos, block_len;
  114. u8 empty[FALCON_SPI_VERIFY_BUF_LEN];
  115. u8 buffer[FALCON_SPI_VERIFY_BUF_LEN];
  116. int rc;
  117. if (len != spi->erase_size)
  118. return -EINVAL;
  119. if (spi->erase_command == 0)
  120. return -EOPNOTSUPP;
  121. rc = falcon_spi_unlock(efx, spi);
  122. if (rc)
  123. return rc;
  124. rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
  125. if (rc)
  126. return rc;
  127. rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
  128. NULL, 0);
  129. if (rc)
  130. return rc;
  131. rc = falcon_spi_slow_wait(part, false);
  132. /* Verify the entire region has been wiped */
  133. memset(empty, 0xff, sizeof(empty));
  134. for (pos = 0; pos < len; pos += block_len) {
  135. block_len = min(len - pos, sizeof(buffer));
  136. rc = falcon_spi_read(efx, spi, start + pos, block_len,
  137. NULL, buffer);
  138. if (rc)
  139. return rc;
  140. if (memcmp(empty, buffer, block_len))
  141. return -EIO;
  142. /* Avoid locking up the system */
  143. cond_resched();
  144. if (signal_pending(current))
  145. return -EINTR;
  146. }
  147. return rc;
  148. }
  149. /* MTD interface */
  150. static int efx_mtd_erase(struct mtd_info *mtd, struct erase_info *erase)
  151. {
  152. struct efx_nic *efx = mtd->priv;
  153. int rc;
  154. rc = efx->mtd_ops->erase(mtd, erase->addr, erase->len);
  155. if (rc == 0) {
  156. erase->state = MTD_ERASE_DONE;
  157. } else {
  158. erase->state = MTD_ERASE_FAILED;
  159. erase->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
  160. }
  161. mtd_erase_callback(erase);
  162. return rc;
  163. }
  164. static void efx_mtd_sync(struct mtd_info *mtd)
  165. {
  166. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  167. struct efx_nic *efx = mtd->priv;
  168. int rc;
  169. rc = efx->mtd_ops->sync(mtd);
  170. if (rc)
  171. pr_err("%s: %s sync failed (%d)\n",
  172. part->name, part->dev_type_name, rc);
  173. }
  174. static void efx_mtd_remove_partition(struct efx_mtd_partition *part)
  175. {
  176. int rc;
  177. for (;;) {
  178. rc = mtd_device_unregister(&part->mtd);
  179. if (rc != -EBUSY)
  180. break;
  181. ssleep(1);
  182. }
  183. WARN_ON(rc);
  184. list_del(&part->node);
  185. }
  186. static void efx_mtd_rename_partition(struct efx_mtd_partition *part)
  187. {
  188. struct efx_nic *efx = part->mtd.priv;
  189. if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
  190. snprintf(part->name, sizeof(part->name), "%s %s:%02x",
  191. efx->name, part->type_name, part->mcdi.fw_subtype);
  192. else
  193. snprintf(part->name, sizeof(part->name), "%s %s",
  194. efx->name, part->type_name);
  195. }
  196. static int efx_mtd_add(struct efx_nic *efx,
  197. struct efx_mtd_partition *parts, size_t n_parts)
  198. {
  199. struct efx_mtd_partition *part;
  200. size_t i;
  201. for (i = 0; i < n_parts; i++) {
  202. part = &parts[i];
  203. part->mtd.writesize = 1;
  204. part->mtd.owner = THIS_MODULE;
  205. part->mtd.priv = efx;
  206. part->mtd.name = part->name;
  207. part->mtd._erase = efx_mtd_erase;
  208. part->mtd._read = efx->mtd_ops->read;
  209. part->mtd._write = efx->mtd_ops->write;
  210. part->mtd._sync = efx_mtd_sync;
  211. efx_mtd_rename_partition(part);
  212. if (mtd_device_register(&part->mtd, NULL, 0))
  213. goto fail;
  214. /* Add to list in order - efx_mtd_remove() depends on this */
  215. list_add_tail(&part->node, &efx->mtd_list);
  216. }
  217. return 0;
  218. fail:
  219. while (i--)
  220. efx_mtd_remove_partition(&parts[i]);
  221. /* Failure is unlikely here, but probably means we're out of memory */
  222. return -ENOMEM;
  223. }
  224. void efx_mtd_remove(struct efx_nic *efx)
  225. {
  226. struct efx_mtd_partition *parts, *part, *next;
  227. WARN_ON(efx_dev_registered(efx));
  228. if (list_empty(&efx->mtd_list))
  229. return;
  230. parts = list_first_entry(&efx->mtd_list, struct efx_mtd_partition,
  231. node);
  232. list_for_each_entry_safe(part, next, &efx->mtd_list, node)
  233. efx_mtd_remove_partition(part);
  234. kfree(parts);
  235. }
  236. void efx_mtd_rename(struct efx_nic *efx)
  237. {
  238. struct efx_mtd_partition *part;
  239. ASSERT_RTNL();
  240. list_for_each_entry(part, &efx->mtd_list, node)
  241. efx_mtd_rename_partition(part);
  242. }
  243. int efx_mtd_probe(struct efx_nic *efx)
  244. {
  245. if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
  246. return siena_mtd_probe(efx);
  247. else
  248. return falcon_mtd_probe(efx);
  249. }
  250. /* Implementation of MTD operations for Falcon */
  251. static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
  252. size_t len, size_t *retlen, u8 *buffer)
  253. {
  254. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  255. struct efx_nic *efx = mtd->priv;
  256. struct falcon_nic_data *nic_data = efx->nic_data;
  257. int rc;
  258. rc = mutex_lock_interruptible(&nic_data->spi_lock);
  259. if (rc)
  260. return rc;
  261. rc = falcon_spi_read(efx, part->falcon.spi, part->falcon.offset + start,
  262. len, retlen, buffer);
  263. mutex_unlock(&nic_data->spi_lock);
  264. return rc;
  265. }
  266. static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
  267. {
  268. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  269. struct efx_nic *efx = mtd->priv;
  270. struct falcon_nic_data *nic_data = efx->nic_data;
  271. int rc;
  272. rc = mutex_lock_interruptible(&nic_data->spi_lock);
  273. if (rc)
  274. return rc;
  275. rc = falcon_spi_erase(part, part->falcon.offset + start, len);
  276. mutex_unlock(&nic_data->spi_lock);
  277. return rc;
  278. }
  279. static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
  280. size_t len, size_t *retlen, const u8 *buffer)
  281. {
  282. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  283. struct efx_nic *efx = mtd->priv;
  284. struct falcon_nic_data *nic_data = efx->nic_data;
  285. int rc;
  286. rc = mutex_lock_interruptible(&nic_data->spi_lock);
  287. if (rc)
  288. return rc;
  289. rc = falcon_spi_write(efx, part->falcon.spi,
  290. part->falcon.offset + start, len, retlen, buffer);
  291. mutex_unlock(&nic_data->spi_lock);
  292. return rc;
  293. }
  294. static int falcon_mtd_sync(struct mtd_info *mtd)
  295. {
  296. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  297. struct efx_nic *efx = mtd->priv;
  298. struct falcon_nic_data *nic_data = efx->nic_data;
  299. int rc;
  300. mutex_lock(&nic_data->spi_lock);
  301. rc = falcon_spi_slow_wait(part, true);
  302. mutex_unlock(&nic_data->spi_lock);
  303. return rc;
  304. }
  305. static const struct efx_mtd_ops falcon_mtd_ops = {
  306. .read = falcon_mtd_read,
  307. .erase = falcon_mtd_erase,
  308. .write = falcon_mtd_write,
  309. .sync = falcon_mtd_sync,
  310. };
  311. static int falcon_mtd_probe(struct efx_nic *efx)
  312. {
  313. struct falcon_nic_data *nic_data = efx->nic_data;
  314. struct efx_mtd_partition *parts;
  315. struct falcon_spi_device *spi;
  316. size_t n_parts;
  317. int rc = -ENODEV;
  318. ASSERT_RTNL();
  319. efx->mtd_ops = &falcon_mtd_ops;
  320. /* Allocate space for maximum number of partitions */
  321. parts = kcalloc(2, sizeof(*parts), GFP_KERNEL);
  322. n_parts = 0;
  323. spi = &nic_data->spi_flash;
  324. if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
  325. parts[n_parts].falcon.spi = spi;
  326. parts[n_parts].falcon.offset = FALCON_FLASH_BOOTCODE_START;
  327. parts[n_parts].dev_type_name = "flash";
  328. parts[n_parts].type_name = "sfc_flash_bootrom";
  329. parts[n_parts].mtd.type = MTD_NORFLASH;
  330. parts[n_parts].mtd.flags = MTD_CAP_NORFLASH;
  331. parts[n_parts].mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
  332. parts[n_parts].mtd.erasesize = spi->erase_size;
  333. n_parts++;
  334. }
  335. spi = &nic_data->spi_eeprom;
  336. if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) {
  337. parts[n_parts].falcon.spi = spi;
  338. parts[n_parts].falcon.offset = FALCON_EEPROM_BOOTCONFIG_START;
  339. parts[n_parts].dev_type_name = "EEPROM";
  340. parts[n_parts].type_name = "sfc_bootconfig";
  341. parts[n_parts].mtd.type = MTD_RAM;
  342. parts[n_parts].mtd.flags = MTD_CAP_RAM;
  343. parts[n_parts].mtd.size =
  344. min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) -
  345. FALCON_EEPROM_BOOTCONFIG_START;
  346. parts[n_parts].mtd.erasesize = spi->erase_size;
  347. n_parts++;
  348. }
  349. rc = efx_mtd_add(efx, parts, n_parts);
  350. if (rc)
  351. kfree(parts);
  352. return rc;
  353. }
  354. /* Implementation of MTD operations for Siena */
  355. static int siena_mtd_read(struct mtd_info *mtd, loff_t start,
  356. size_t len, size_t *retlen, u8 *buffer)
  357. {
  358. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  359. struct efx_nic *efx = mtd->priv;
  360. loff_t offset = start;
  361. loff_t end = min_t(loff_t, start + len, mtd->size);
  362. size_t chunk;
  363. int rc = 0;
  364. while (offset < end) {
  365. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  366. rc = efx_mcdi_nvram_read(efx, part->mcdi.nvram_type, offset,
  367. buffer, chunk);
  368. if (rc)
  369. goto out;
  370. offset += chunk;
  371. buffer += chunk;
  372. }
  373. out:
  374. *retlen = offset - start;
  375. return rc;
  376. }
  377. static int siena_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
  378. {
  379. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  380. struct efx_nic *efx = mtd->priv;
  381. loff_t offset = start & ~((loff_t)(mtd->erasesize - 1));
  382. loff_t end = min_t(loff_t, start + len, mtd->size);
  383. size_t chunk = part->mtd.erasesize;
  384. int rc = 0;
  385. if (!part->mcdi.updating) {
  386. rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
  387. if (rc)
  388. goto out;
  389. part->mcdi.updating = true;
  390. }
  391. /* The MCDI interface can in fact do multiple erase blocks at once;
  392. * but erasing may be slow, so we make multiple calls here to avoid
  393. * tripping the MCDI RPC timeout. */
  394. while (offset < end) {
  395. rc = efx_mcdi_nvram_erase(efx, part->mcdi.nvram_type, offset,
  396. chunk);
  397. if (rc)
  398. goto out;
  399. offset += chunk;
  400. }
  401. out:
  402. return rc;
  403. }
  404. static int siena_mtd_write(struct mtd_info *mtd, loff_t start,
  405. size_t len, size_t *retlen, const u8 *buffer)
  406. {
  407. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  408. struct efx_nic *efx = mtd->priv;
  409. loff_t offset = start;
  410. loff_t end = min_t(loff_t, start + len, mtd->size);
  411. size_t chunk;
  412. int rc = 0;
  413. if (!part->mcdi.updating) {
  414. rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
  415. if (rc)
  416. goto out;
  417. part->mcdi.updating = true;
  418. }
  419. while (offset < end) {
  420. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  421. rc = efx_mcdi_nvram_write(efx, part->mcdi.nvram_type, offset,
  422. buffer, chunk);
  423. if (rc)
  424. goto out;
  425. offset += chunk;
  426. buffer += chunk;
  427. }
  428. out:
  429. *retlen = offset - start;
  430. return rc;
  431. }
  432. static int siena_mtd_sync(struct mtd_info *mtd)
  433. {
  434. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  435. struct efx_nic *efx = mtd->priv;
  436. int rc = 0;
  437. if (part->mcdi.updating) {
  438. part->mcdi.updating = false;
  439. rc = efx_mcdi_nvram_update_finish(efx, part->mcdi.nvram_type);
  440. }
  441. return rc;
  442. }
  443. static const struct efx_mtd_ops siena_mtd_ops = {
  444. .read = siena_mtd_read,
  445. .erase = siena_mtd_erase,
  446. .write = siena_mtd_write,
  447. .sync = siena_mtd_sync,
  448. };
  449. struct siena_nvram_type_info {
  450. int port;
  451. const char *name;
  452. };
  453. static const struct siena_nvram_type_info siena_nvram_types[] = {
  454. [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
  455. [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
  456. [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
  457. [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
  458. [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
  459. [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
  460. [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
  461. [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
  462. [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
  463. [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
  464. [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
  465. [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
  466. [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" },
  467. };
  468. static int siena_mtd_probe_partition(struct efx_nic *efx,
  469. struct efx_mtd_partition *part,
  470. unsigned int type)
  471. {
  472. const struct siena_nvram_type_info *info;
  473. size_t size, erase_size;
  474. bool protected;
  475. int rc;
  476. if (type >= ARRAY_SIZE(siena_nvram_types) ||
  477. siena_nvram_types[type].name == NULL)
  478. return -ENODEV;
  479. info = &siena_nvram_types[type];
  480. if (info->port != efx_port_num(efx))
  481. return -ENODEV;
  482. rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
  483. if (rc)
  484. return rc;
  485. if (protected)
  486. return -ENODEV; /* hide it */
  487. part->mcdi.nvram_type = type;
  488. part->dev_type_name = "Siena NVRAM manager";
  489. part->type_name = info->name;
  490. part->mtd.type = MTD_NORFLASH;
  491. part->mtd.flags = MTD_CAP_NORFLASH;
  492. part->mtd.size = size;
  493. part->mtd.erasesize = erase_size;
  494. return 0;
  495. }
  496. static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
  497. struct efx_mtd_partition *parts,
  498. size_t n_parts)
  499. {
  500. uint16_t fw_subtype_list[
  501. MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM];
  502. size_t i;
  503. int rc;
  504. rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL);
  505. if (rc)
  506. return rc;
  507. for (i = 0; i < n_parts; i++)
  508. parts[i].mcdi.fw_subtype =
  509. fw_subtype_list[parts[i].mcdi.nvram_type];
  510. return 0;
  511. }
  512. static int siena_mtd_probe(struct efx_nic *efx)
  513. {
  514. struct efx_mtd_partition *parts;
  515. u32 nvram_types;
  516. unsigned int type;
  517. size_t n_parts;
  518. int rc;
  519. ASSERT_RTNL();
  520. efx->mtd_ops = &siena_mtd_ops;
  521. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  522. if (rc)
  523. return rc;
  524. parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL);
  525. if (!parts)
  526. return -ENOMEM;
  527. type = 0;
  528. n_parts = 0;
  529. while (nvram_types != 0) {
  530. if (nvram_types & 1) {
  531. rc = siena_mtd_probe_partition(efx, &parts[n_parts],
  532. type);
  533. if (rc == 0)
  534. n_parts++;
  535. else if (rc != -ENODEV)
  536. goto fail;
  537. }
  538. type++;
  539. nvram_types >>= 1;
  540. }
  541. rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts);
  542. if (rc)
  543. goto fail;
  544. rc = efx_mtd_add(efx, parts, n_parts);
  545. fail:
  546. if (rc)
  547. kfree(parts);
  548. return rc;
  549. }