twl4030.c 61 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. struct snd_pcm_substream *master_substream;
  122. struct snd_pcm_substream *slave_substream;
  123. unsigned int configured;
  124. unsigned int rate;
  125. unsigned int sample_bits;
  126. unsigned int channels;
  127. };
  128. /*
  129. * read twl4030 register cache
  130. */
  131. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  132. unsigned int reg)
  133. {
  134. u8 *cache = codec->reg_cache;
  135. if (reg >= TWL4030_CACHEREGNUM)
  136. return -EIO;
  137. return cache[reg];
  138. }
  139. /*
  140. * write twl4030 register cache
  141. */
  142. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  143. u8 reg, u8 value)
  144. {
  145. u8 *cache = codec->reg_cache;
  146. if (reg >= TWL4030_CACHEREGNUM)
  147. return;
  148. cache[reg] = value;
  149. }
  150. /*
  151. * write to the twl4030 register space
  152. */
  153. static int twl4030_write(struct snd_soc_codec *codec,
  154. unsigned int reg, unsigned int value)
  155. {
  156. twl4030_write_reg_cache(codec, reg, value);
  157. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  158. }
  159. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  160. {
  161. struct twl4030_priv *twl4030 = codec->private_data;
  162. u8 mode;
  163. if (enable == twl4030->codec_powered)
  164. return;
  165. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  166. if (enable)
  167. mode |= TWL4030_CODECPDZ;
  168. else
  169. mode &= ~TWL4030_CODECPDZ;
  170. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  171. twl4030->codec_powered = enable;
  172. /* REVISIT: this delay is present in TI sample drivers */
  173. /* but there seems to be no TRM requirement for it */
  174. udelay(10);
  175. }
  176. static void twl4030_init_chip(struct snd_soc_codec *codec)
  177. {
  178. int i;
  179. /* clear CODECPDZ prior to setting register defaults */
  180. twl4030_codec_enable(codec, 0);
  181. /* set all audio section registers to reasonable defaults */
  182. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  183. twl4030_write(codec, i, twl4030_reg[i]);
  184. }
  185. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  186. {
  187. struct twl4030_priv *twl4030 = codec->private_data;
  188. u8 reg_val;
  189. if (mute == twl4030->codec_muted)
  190. return;
  191. if (mute) {
  192. /* Bypass the reg_cache and mute the volumes
  193. * Headset mute is done in it's own event handler
  194. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  195. */
  196. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  197. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  198. reg_val & (~TWL4030_EAR_GAIN),
  199. TWL4030_REG_EAR_CTL);
  200. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  201. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. reg_val & (~TWL4030_PREDL_GAIN),
  203. TWL4030_REG_PREDL_CTL);
  204. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  205. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  206. reg_val & (~TWL4030_PREDR_GAIN),
  207. TWL4030_REG_PREDL_CTL);
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  209. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  210. reg_val & (~TWL4030_PRECKL_GAIN),
  211. TWL4030_REG_PRECKL_CTL);
  212. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  213. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  214. reg_val & (~TWL4030_PRECKR_GAIN),
  215. TWL4030_REG_PRECKR_CTL);
  216. /* Disable PLL */
  217. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  218. reg_val &= ~TWL4030_APLL_EN;
  219. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  220. } else {
  221. /* Restore the volumes
  222. * Headset mute is done in it's own event handler
  223. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  224. */
  225. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  226. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  227. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  228. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  229. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  230. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  231. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  232. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  233. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  234. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  235. /* Enable PLL */
  236. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  237. reg_val |= TWL4030_APLL_EN;
  238. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  239. }
  240. twl4030->codec_muted = mute;
  241. }
  242. static void twl4030_power_up(struct snd_soc_codec *codec)
  243. {
  244. struct twl4030_priv *twl4030 = codec->private_data;
  245. u8 anamicl, regmisc1, byte;
  246. int i = 0;
  247. if (twl4030->codec_powered)
  248. return;
  249. /* set CODECPDZ to turn on codec */
  250. twl4030_codec_enable(codec, 1);
  251. /* initiate offset cancellation */
  252. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  253. twl4030_write(codec, TWL4030_REG_ANAMICL,
  254. anamicl | TWL4030_CNCL_OFFSET_START);
  255. /* wait for offset cancellation to complete */
  256. do {
  257. /* this takes a little while, so don't slam i2c */
  258. udelay(2000);
  259. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  260. TWL4030_REG_ANAMICL);
  261. } while ((i++ < 100) &&
  262. ((byte & TWL4030_CNCL_OFFSET_START) ==
  263. TWL4030_CNCL_OFFSET_START));
  264. /* Make sure that the reg_cache has the same value as the HW */
  265. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  266. /* anti-pop when changing analog gain */
  267. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  268. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  269. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  270. /* toggle CODECPDZ as per TRM */
  271. twl4030_codec_enable(codec, 0);
  272. twl4030_codec_enable(codec, 1);
  273. }
  274. /*
  275. * Unconditional power down
  276. */
  277. static void twl4030_power_down(struct snd_soc_codec *codec)
  278. {
  279. /* power down */
  280. twl4030_codec_enable(codec, 0);
  281. }
  282. /* Earpiece */
  283. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  284. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  285. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  286. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  287. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  288. };
  289. /* PreDrive Left */
  290. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  291. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  292. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  293. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  294. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  295. };
  296. /* PreDrive Right */
  297. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  298. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  299. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  300. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  301. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  302. };
  303. /* Headset Left */
  304. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  305. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  306. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  307. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  308. };
  309. /* Headset Right */
  310. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  311. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  312. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  313. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  314. };
  315. /* Carkit Left */
  316. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  317. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  318. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  319. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  320. };
  321. /* Carkit Right */
  322. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  323. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  324. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  325. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  326. };
  327. /* Handsfree Left */
  328. static const char *twl4030_handsfreel_texts[] =
  329. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  330. static const struct soc_enum twl4030_handsfreel_enum =
  331. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  332. ARRAY_SIZE(twl4030_handsfreel_texts),
  333. twl4030_handsfreel_texts);
  334. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  335. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  336. /* Handsfree Right */
  337. static const char *twl4030_handsfreer_texts[] =
  338. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  339. static const struct soc_enum twl4030_handsfreer_enum =
  340. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  341. ARRAY_SIZE(twl4030_handsfreer_texts),
  342. twl4030_handsfreer_texts);
  343. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  344. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  345. /* Vibra */
  346. /* Vibra audio path selection */
  347. static const char *twl4030_vibra_texts[] =
  348. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  349. static const struct soc_enum twl4030_vibra_enum =
  350. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  351. ARRAY_SIZE(twl4030_vibra_texts),
  352. twl4030_vibra_texts);
  353. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  354. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  355. /* Vibra path selection: local vibrator (PWM) or audio driven */
  356. static const char *twl4030_vibrapath_texts[] =
  357. {"Local vibrator", "Audio"};
  358. static const struct soc_enum twl4030_vibrapath_enum =
  359. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  360. ARRAY_SIZE(twl4030_vibrapath_texts),
  361. twl4030_vibrapath_texts);
  362. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  363. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  364. /* Left analog microphone selection */
  365. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  366. SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
  367. SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
  368. SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
  369. SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
  370. };
  371. /* Right analog microphone selection */
  372. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  373. SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
  374. SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
  375. };
  376. /* TX1 L/R Analog/Digital microphone selection */
  377. static const char *twl4030_micpathtx1_texts[] =
  378. {"Analog", "Digimic0"};
  379. static const struct soc_enum twl4030_micpathtx1_enum =
  380. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  381. ARRAY_SIZE(twl4030_micpathtx1_texts),
  382. twl4030_micpathtx1_texts);
  383. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  384. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  385. /* TX2 L/R Analog/Digital microphone selection */
  386. static const char *twl4030_micpathtx2_texts[] =
  387. {"Analog", "Digimic1"};
  388. static const struct soc_enum twl4030_micpathtx2_enum =
  389. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  390. ARRAY_SIZE(twl4030_micpathtx2_texts),
  391. twl4030_micpathtx2_texts);
  392. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  393. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  394. /* Analog bypass for AudioR1 */
  395. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  396. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  397. /* Analog bypass for AudioL1 */
  398. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  399. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  400. /* Analog bypass for AudioR2 */
  401. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  402. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  403. /* Analog bypass for AudioL2 */
  404. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  405. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  406. /* Analog bypass for Voice */
  407. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  408. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  409. /* Digital bypass gain, 0 mutes the bypass */
  410. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  411. TLV_DB_RANGE_HEAD(2),
  412. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  413. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  414. };
  415. /* Digital bypass left (TX1L -> RX2L) */
  416. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  417. SOC_DAPM_SINGLE_TLV("Volume",
  418. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  419. twl4030_dapm_dbypass_tlv);
  420. /* Digital bypass right (TX1R -> RX2R) */
  421. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  422. SOC_DAPM_SINGLE_TLV("Volume",
  423. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  424. twl4030_dapm_dbypass_tlv);
  425. /*
  426. * Voice Sidetone GAIN volume control:
  427. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  428. */
  429. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  430. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  431. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  432. SOC_DAPM_SINGLE_TLV("Volume",
  433. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  434. twl4030_dapm_dbypassv_tlv);
  435. static int micpath_event(struct snd_soc_dapm_widget *w,
  436. struct snd_kcontrol *kcontrol, int event)
  437. {
  438. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  439. unsigned char adcmicsel, micbias_ctl;
  440. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  441. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  442. /* Prepare the bits for the given TX path:
  443. * shift_l == 0: TX1 microphone path
  444. * shift_l == 2: TX2 microphone path */
  445. if (e->shift_l) {
  446. /* TX2 microphone path */
  447. if (adcmicsel & TWL4030_TX2IN_SEL)
  448. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  449. else
  450. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  451. } else {
  452. /* TX1 microphone path */
  453. if (adcmicsel & TWL4030_TX1IN_SEL)
  454. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  455. else
  456. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  457. }
  458. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  459. return 0;
  460. }
  461. static int handsfree_event(struct snd_soc_dapm_widget *w,
  462. struct snd_kcontrol *kcontrol, int event)
  463. {
  464. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  465. unsigned char hs_ctl;
  466. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  467. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  468. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  469. twl4030_write(w->codec, e->reg, hs_ctl);
  470. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  471. twl4030_write(w->codec, e->reg, hs_ctl);
  472. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  473. twl4030_write(w->codec, e->reg, hs_ctl);
  474. } else {
  475. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  476. | TWL4030_HF_CTL_HB_EN);
  477. twl4030_write(w->codec, e->reg, hs_ctl);
  478. }
  479. return 0;
  480. }
  481. static int headsetl_event(struct snd_soc_dapm_widget *w,
  482. struct snd_kcontrol *kcontrol, int event)
  483. {
  484. unsigned char hs_gain, hs_pop;
  485. /* Save the current volume */
  486. hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
  487. hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
  488. switch (event) {
  489. case SND_SOC_DAPM_POST_PMU:
  490. /* Do the anti-pop/bias ramp enable according to the TRM */
  491. hs_pop |= TWL4030_VMID_EN;
  492. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  493. /* Is this needed? Can we just use whatever gain here? */
  494. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
  495. (hs_gain & (~0x0f)) | 0x0a);
  496. hs_pop |= TWL4030_RAMP_EN;
  497. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  498. /* Restore the original volume */
  499. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  500. break;
  501. case SND_SOC_DAPM_POST_PMD:
  502. /* Do the anti-pop/bias ramp disable according to the TRM */
  503. hs_pop &= ~TWL4030_RAMP_EN;
  504. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  505. /* Bypass the reg_cache to mute the headset */
  506. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  507. hs_gain & (~0x0f),
  508. TWL4030_REG_HS_GAIN_SET);
  509. hs_pop &= ~TWL4030_VMID_EN;
  510. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  511. break;
  512. }
  513. return 0;
  514. }
  515. static int bypass_event(struct snd_soc_dapm_widget *w,
  516. struct snd_kcontrol *kcontrol, int event)
  517. {
  518. struct soc_mixer_control *m =
  519. (struct soc_mixer_control *)w->kcontrols->private_value;
  520. struct twl4030_priv *twl4030 = w->codec->private_data;
  521. unsigned char reg, misc;
  522. reg = twl4030_read_reg_cache(w->codec, m->reg);
  523. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  524. /* Analog bypass */
  525. if (reg & (1 << m->shift))
  526. twl4030->bypass_state |=
  527. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  528. else
  529. twl4030->bypass_state &=
  530. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  531. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  532. /* Analog voice bypass */
  533. if (reg & (1 << m->shift))
  534. twl4030->bypass_state |= (1 << 4);
  535. else
  536. twl4030->bypass_state &= ~(1 << 4);
  537. } else if (m->reg == TWL4030_REG_VSTPGA) {
  538. /* Voice digital bypass */
  539. if (reg)
  540. twl4030->bypass_state |= (1 << 5);
  541. else
  542. twl4030->bypass_state &= ~(1 << 5);
  543. } else {
  544. /* Digital bypass */
  545. if (reg & (0x7 << m->shift))
  546. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  547. else
  548. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  549. }
  550. /* Enable master analog loopback mode if any analog switch is enabled*/
  551. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  552. if (twl4030->bypass_state & 0x1F)
  553. misc |= TWL4030_FMLOOP_EN;
  554. else
  555. misc &= ~TWL4030_FMLOOP_EN;
  556. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  557. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  558. if (twl4030->bypass_state)
  559. twl4030_codec_mute(w->codec, 0);
  560. else
  561. twl4030_codec_mute(w->codec, 1);
  562. }
  563. return 0;
  564. }
  565. /*
  566. * Some of the gain controls in TWL (mostly those which are associated with
  567. * the outputs) are implemented in an interesting way:
  568. * 0x0 : Power down (mute)
  569. * 0x1 : 6dB
  570. * 0x2 : 0 dB
  571. * 0x3 : -6 dB
  572. * Inverting not going to help with these.
  573. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  574. */
  575. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  576. xinvert, tlv_array) \
  577. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  578. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  579. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  580. .tlv.p = (tlv_array), \
  581. .info = snd_soc_info_volsw, \
  582. .get = snd_soc_get_volsw_twl4030, \
  583. .put = snd_soc_put_volsw_twl4030, \
  584. .private_value = (unsigned long)&(struct soc_mixer_control) \
  585. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  586. .max = xmax, .invert = xinvert} }
  587. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  588. xinvert, tlv_array) \
  589. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  590. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  591. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  592. .tlv.p = (tlv_array), \
  593. .info = snd_soc_info_volsw_2r, \
  594. .get = snd_soc_get_volsw_r2_twl4030,\
  595. .put = snd_soc_put_volsw_r2_twl4030, \
  596. .private_value = (unsigned long)&(struct soc_mixer_control) \
  597. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  598. .rshift = xshift, .max = xmax, .invert = xinvert} }
  599. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  600. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  601. xinvert, tlv_array)
  602. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  603. struct snd_ctl_elem_value *ucontrol)
  604. {
  605. struct soc_mixer_control *mc =
  606. (struct soc_mixer_control *)kcontrol->private_value;
  607. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  608. unsigned int reg = mc->reg;
  609. unsigned int shift = mc->shift;
  610. unsigned int rshift = mc->rshift;
  611. int max = mc->max;
  612. int mask = (1 << fls(max)) - 1;
  613. ucontrol->value.integer.value[0] =
  614. (snd_soc_read(codec, reg) >> shift) & mask;
  615. if (ucontrol->value.integer.value[0])
  616. ucontrol->value.integer.value[0] =
  617. max + 1 - ucontrol->value.integer.value[0];
  618. if (shift != rshift) {
  619. ucontrol->value.integer.value[1] =
  620. (snd_soc_read(codec, reg) >> rshift) & mask;
  621. if (ucontrol->value.integer.value[1])
  622. ucontrol->value.integer.value[1] =
  623. max + 1 - ucontrol->value.integer.value[1];
  624. }
  625. return 0;
  626. }
  627. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  628. struct snd_ctl_elem_value *ucontrol)
  629. {
  630. struct soc_mixer_control *mc =
  631. (struct soc_mixer_control *)kcontrol->private_value;
  632. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  633. unsigned int reg = mc->reg;
  634. unsigned int shift = mc->shift;
  635. unsigned int rshift = mc->rshift;
  636. int max = mc->max;
  637. int mask = (1 << fls(max)) - 1;
  638. unsigned short val, val2, val_mask;
  639. val = (ucontrol->value.integer.value[0] & mask);
  640. val_mask = mask << shift;
  641. if (val)
  642. val = max + 1 - val;
  643. val = val << shift;
  644. if (shift != rshift) {
  645. val2 = (ucontrol->value.integer.value[1] & mask);
  646. val_mask |= mask << rshift;
  647. if (val2)
  648. val2 = max + 1 - val2;
  649. val |= val2 << rshift;
  650. }
  651. return snd_soc_update_bits(codec, reg, val_mask, val);
  652. }
  653. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  654. struct snd_ctl_elem_value *ucontrol)
  655. {
  656. struct soc_mixer_control *mc =
  657. (struct soc_mixer_control *)kcontrol->private_value;
  658. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  659. unsigned int reg = mc->reg;
  660. unsigned int reg2 = mc->rreg;
  661. unsigned int shift = mc->shift;
  662. int max = mc->max;
  663. int mask = (1<<fls(max))-1;
  664. ucontrol->value.integer.value[0] =
  665. (snd_soc_read(codec, reg) >> shift) & mask;
  666. ucontrol->value.integer.value[1] =
  667. (snd_soc_read(codec, reg2) >> shift) & mask;
  668. if (ucontrol->value.integer.value[0])
  669. ucontrol->value.integer.value[0] =
  670. max + 1 - ucontrol->value.integer.value[0];
  671. if (ucontrol->value.integer.value[1])
  672. ucontrol->value.integer.value[1] =
  673. max + 1 - ucontrol->value.integer.value[1];
  674. return 0;
  675. }
  676. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  677. struct snd_ctl_elem_value *ucontrol)
  678. {
  679. struct soc_mixer_control *mc =
  680. (struct soc_mixer_control *)kcontrol->private_value;
  681. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  682. unsigned int reg = mc->reg;
  683. unsigned int reg2 = mc->rreg;
  684. unsigned int shift = mc->shift;
  685. int max = mc->max;
  686. int mask = (1 << fls(max)) - 1;
  687. int err;
  688. unsigned short val, val2, val_mask;
  689. val_mask = mask << shift;
  690. val = (ucontrol->value.integer.value[0] & mask);
  691. val2 = (ucontrol->value.integer.value[1] & mask);
  692. if (val)
  693. val = max + 1 - val;
  694. if (val2)
  695. val2 = max + 1 - val2;
  696. val = val << shift;
  697. val2 = val2 << shift;
  698. err = snd_soc_update_bits(codec, reg, val_mask, val);
  699. if (err < 0)
  700. return err;
  701. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  702. return err;
  703. }
  704. /* Codec operation modes */
  705. static const char *twl4030_op_modes_texts[] = {
  706. "Option 2 (voice/audio)", "Option 1 (audio)"
  707. };
  708. static const struct soc_enum twl4030_op_modes_enum =
  709. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  710. ARRAY_SIZE(twl4030_op_modes_texts),
  711. twl4030_op_modes_texts);
  712. int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  713. struct snd_ctl_elem_value *ucontrol)
  714. {
  715. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  716. struct twl4030_priv *twl4030 = codec->private_data;
  717. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  718. unsigned short val;
  719. unsigned short mask, bitmask;
  720. if (twl4030->configured) {
  721. printk(KERN_ERR "twl4030 operation mode cannot be "
  722. "changed on-the-fly\n");
  723. return -EBUSY;
  724. }
  725. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  726. ;
  727. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  728. return -EINVAL;
  729. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  730. mask = (bitmask - 1) << e->shift_l;
  731. if (e->shift_l != e->shift_r) {
  732. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  733. return -EINVAL;
  734. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  735. mask |= (bitmask - 1) << e->shift_r;
  736. }
  737. return snd_soc_update_bits(codec, e->reg, mask, val);
  738. }
  739. /*
  740. * FGAIN volume control:
  741. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  742. */
  743. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  744. /*
  745. * CGAIN volume control:
  746. * 0 dB to 12 dB in 6 dB steps
  747. * value 2 and 3 means 12 dB
  748. */
  749. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  750. /*
  751. * Voice Downlink GAIN volume control:
  752. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  753. */
  754. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  755. /*
  756. * Analog playback gain
  757. * -24 dB to 12 dB in 2 dB steps
  758. */
  759. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  760. /*
  761. * Gain controls tied to outputs
  762. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  763. */
  764. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  765. /*
  766. * Gain control for earpiece amplifier
  767. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  768. */
  769. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  770. /*
  771. * Capture gain after the ADCs
  772. * from 0 dB to 31 dB in 1 dB steps
  773. */
  774. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  775. /*
  776. * Gain control for input amplifiers
  777. * 0 dB to 30 dB in 6 dB steps
  778. */
  779. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  780. static const char *twl4030_rampdelay_texts[] = {
  781. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  782. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  783. "3495/2581/1748 ms"
  784. };
  785. static const struct soc_enum twl4030_rampdelay_enum =
  786. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  787. ARRAY_SIZE(twl4030_rampdelay_texts),
  788. twl4030_rampdelay_texts);
  789. /* Vibra H-bridge direction mode */
  790. static const char *twl4030_vibradirmode_texts[] = {
  791. "Vibra H-bridge direction", "Audio data MSB",
  792. };
  793. static const struct soc_enum twl4030_vibradirmode_enum =
  794. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  795. ARRAY_SIZE(twl4030_vibradirmode_texts),
  796. twl4030_vibradirmode_texts);
  797. /* Vibra H-bridge direction */
  798. static const char *twl4030_vibradir_texts[] = {
  799. "Positive polarity", "Negative polarity",
  800. };
  801. static const struct soc_enum twl4030_vibradir_enum =
  802. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  803. ARRAY_SIZE(twl4030_vibradir_texts),
  804. twl4030_vibradir_texts);
  805. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  806. /* Codec operation mode control */
  807. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  808. snd_soc_get_enum_double,
  809. snd_soc_put_twl4030_opmode_enum_double),
  810. /* Common playback gain controls */
  811. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  812. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  813. 0, 0x3f, 0, digital_fine_tlv),
  814. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  815. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  816. 0, 0x3f, 0, digital_fine_tlv),
  817. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  818. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  819. 6, 0x2, 0, digital_coarse_tlv),
  820. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  821. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  822. 6, 0x2, 0, digital_coarse_tlv),
  823. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  824. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  825. 3, 0x12, 1, analog_tlv),
  826. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  827. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  828. 3, 0x12, 1, analog_tlv),
  829. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  830. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  831. 1, 1, 0),
  832. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  833. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  834. 1, 1, 0),
  835. /* Common voice downlink gain controls */
  836. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  837. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  838. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  839. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  840. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  841. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  842. /* Separate output gain controls */
  843. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  844. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  845. 4, 3, 0, output_tvl),
  846. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  847. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  848. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  849. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  850. 4, 3, 0, output_tvl),
  851. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  852. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  853. /* Common capture gain controls */
  854. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  855. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  856. 0, 0x1f, 0, digital_capture_tlv),
  857. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  858. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  859. 0, 0x1f, 0, digital_capture_tlv),
  860. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  861. 0, 3, 5, 0, input_gain_tlv),
  862. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  863. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  864. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  865. };
  866. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  867. /* Left channel inputs */
  868. SND_SOC_DAPM_INPUT("MAINMIC"),
  869. SND_SOC_DAPM_INPUT("HSMIC"),
  870. SND_SOC_DAPM_INPUT("AUXL"),
  871. SND_SOC_DAPM_INPUT("CARKITMIC"),
  872. /* Right channel inputs */
  873. SND_SOC_DAPM_INPUT("SUBMIC"),
  874. SND_SOC_DAPM_INPUT("AUXR"),
  875. /* Digital microphones (Stereo) */
  876. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  877. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  878. /* Outputs */
  879. SND_SOC_DAPM_OUTPUT("OUTL"),
  880. SND_SOC_DAPM_OUTPUT("OUTR"),
  881. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  882. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  883. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  884. SND_SOC_DAPM_OUTPUT("HSOL"),
  885. SND_SOC_DAPM_OUTPUT("HSOR"),
  886. SND_SOC_DAPM_OUTPUT("CARKITL"),
  887. SND_SOC_DAPM_OUTPUT("CARKITR"),
  888. SND_SOC_DAPM_OUTPUT("HFL"),
  889. SND_SOC_DAPM_OUTPUT("HFR"),
  890. SND_SOC_DAPM_OUTPUT("VIBRA"),
  891. /* DACs */
  892. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  893. SND_SOC_NOPM, 0, 0),
  894. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  895. SND_SOC_NOPM, 0, 0),
  896. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  897. SND_SOC_NOPM, 0, 0),
  898. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  899. SND_SOC_NOPM, 0, 0),
  900. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  901. SND_SOC_NOPM, 0, 0),
  902. /* Analog PGAs */
  903. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  904. 0, 0, NULL, 0),
  905. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  906. 0, 0, NULL, 0),
  907. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  908. 0, 0, NULL, 0),
  909. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  910. 0, 0, NULL, 0),
  911. SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
  912. 0, 0, NULL, 0),
  913. /* Analog bypasses */
  914. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  915. &twl4030_dapm_abypassr1_control, bypass_event,
  916. SND_SOC_DAPM_POST_REG),
  917. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  918. &twl4030_dapm_abypassl1_control,
  919. bypass_event, SND_SOC_DAPM_POST_REG),
  920. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  921. &twl4030_dapm_abypassr2_control,
  922. bypass_event, SND_SOC_DAPM_POST_REG),
  923. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  924. &twl4030_dapm_abypassl2_control,
  925. bypass_event, SND_SOC_DAPM_POST_REG),
  926. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  927. &twl4030_dapm_abypassv_control,
  928. bypass_event, SND_SOC_DAPM_POST_REG),
  929. /* Digital bypasses */
  930. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  931. &twl4030_dapm_dbypassl_control, bypass_event,
  932. SND_SOC_DAPM_POST_REG),
  933. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  934. &twl4030_dapm_dbypassr_control, bypass_event,
  935. SND_SOC_DAPM_POST_REG),
  936. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  937. &twl4030_dapm_dbypassv_control, bypass_event,
  938. SND_SOC_DAPM_POST_REG),
  939. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  940. 0, 0, NULL, 0),
  941. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  942. 1, 0, NULL, 0),
  943. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  944. 2, 0, NULL, 0),
  945. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  946. 3, 0, NULL, 0),
  947. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", TWL4030_REG_AVDAC_CTL,
  948. 4, 0, NULL, 0),
  949. /* Output MIXER controls */
  950. /* Earpiece */
  951. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  952. &twl4030_dapm_earpiece_controls[0],
  953. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  954. /* PreDrivL/R */
  955. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  956. &twl4030_dapm_predrivel_controls[0],
  957. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  958. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  959. &twl4030_dapm_predriver_controls[0],
  960. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  961. /* HeadsetL/R */
  962. SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  963. &twl4030_dapm_hsol_controls[0],
  964. ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
  965. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  966. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  967. &twl4030_dapm_hsor_controls[0],
  968. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  969. /* CarkitL/R */
  970. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  971. &twl4030_dapm_carkitl_controls[0],
  972. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  973. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  974. &twl4030_dapm_carkitr_controls[0],
  975. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  976. /* Output MUX controls */
  977. /* HandsfreeL/R */
  978. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  979. &twl4030_dapm_handsfreel_control, handsfree_event,
  980. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  981. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  982. &twl4030_dapm_handsfreer_control, handsfree_event,
  983. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  984. /* Vibra */
  985. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  986. &twl4030_dapm_vibra_control),
  987. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  988. &twl4030_dapm_vibrapath_control),
  989. /* Introducing four virtual ADC, since TWL4030 have four channel for
  990. capture */
  991. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  992. SND_SOC_NOPM, 0, 0),
  993. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  994. SND_SOC_NOPM, 0, 0),
  995. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  996. SND_SOC_NOPM, 0, 0),
  997. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  998. SND_SOC_NOPM, 0, 0),
  999. /* Analog/Digital mic path selection.
  1000. TX1 Left/Right: either analog Left/Right or Digimic0
  1001. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1002. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1003. &twl4030_dapm_micpathtx1_control, micpath_event,
  1004. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1005. SND_SOC_DAPM_POST_REG),
  1006. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1007. &twl4030_dapm_micpathtx2_control, micpath_event,
  1008. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1009. SND_SOC_DAPM_POST_REG),
  1010. /* Analog input mixers for the capture amplifiers */
  1011. SND_SOC_DAPM_MIXER("Analog Left Capture Route",
  1012. TWL4030_REG_ANAMICL, 4, 0,
  1013. &twl4030_dapm_analoglmic_controls[0],
  1014. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1015. SND_SOC_DAPM_MIXER("Analog Right Capture Route",
  1016. TWL4030_REG_ANAMICR, 4, 0,
  1017. &twl4030_dapm_analogrmic_controls[0],
  1018. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1019. SND_SOC_DAPM_PGA("ADC Physical Left",
  1020. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1021. SND_SOC_DAPM_PGA("ADC Physical Right",
  1022. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1023. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1024. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1025. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1026. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1027. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1028. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1029. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1030. };
  1031. static const struct snd_soc_dapm_route intercon[] = {
  1032. {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
  1033. {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
  1034. {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
  1035. {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
  1036. {"Analog Voice Playback Mixer", NULL, "DAC Voice"},
  1037. {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
  1038. {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
  1039. {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
  1040. {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
  1041. {"VDL_APGA", NULL, "Analog Voice Playback Mixer"},
  1042. /* Internal playback routings */
  1043. /* Earpiece */
  1044. {"Earpiece Mixer", "Voice", "VDL_APGA"},
  1045. {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
  1046. {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
  1047. {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
  1048. /* PreDrivL */
  1049. {"PredriveL Mixer", "Voice", "VDL_APGA"},
  1050. {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
  1051. {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
  1052. {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
  1053. /* PreDrivR */
  1054. {"PredriveR Mixer", "Voice", "VDL_APGA"},
  1055. {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
  1056. {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
  1057. {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
  1058. /* HeadsetL */
  1059. {"HeadsetL Mixer", "Voice", "VDL_APGA"},
  1060. {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
  1061. {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
  1062. /* HeadsetR */
  1063. {"HeadsetR Mixer", "Voice", "VDL_APGA"},
  1064. {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
  1065. {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
  1066. /* CarkitL */
  1067. {"CarkitL Mixer", "Voice", "VDL_APGA"},
  1068. {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
  1069. {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
  1070. /* CarkitR */
  1071. {"CarkitR Mixer", "Voice", "VDL_APGA"},
  1072. {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
  1073. {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
  1074. /* HandsfreeL */
  1075. {"HandsfreeL Mux", "Voice", "VDL_APGA"},
  1076. {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
  1077. {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
  1078. {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
  1079. /* HandsfreeR */
  1080. {"HandsfreeR Mux", "Voice", "VDL_APGA"},
  1081. {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
  1082. {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
  1083. {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
  1084. /* Vibra */
  1085. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1086. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1087. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1088. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1089. /* outputs */
  1090. {"OUTL", NULL, "ARXL2_APGA"},
  1091. {"OUTR", NULL, "ARXR2_APGA"},
  1092. {"EARPIECE", NULL, "Earpiece Mixer"},
  1093. {"PREDRIVEL", NULL, "PredriveL Mixer"},
  1094. {"PREDRIVER", NULL, "PredriveR Mixer"},
  1095. {"HSOL", NULL, "HeadsetL Mixer"},
  1096. {"HSOR", NULL, "HeadsetR Mixer"},
  1097. {"CARKITL", NULL, "CarkitL Mixer"},
  1098. {"CARKITR", NULL, "CarkitR Mixer"},
  1099. {"HFL", NULL, "HandsfreeL Mux"},
  1100. {"HFR", NULL, "HandsfreeR Mux"},
  1101. {"Vibra Route", "Audio", "Vibra Mux"},
  1102. {"VIBRA", NULL, "Vibra Route"},
  1103. /* Capture path */
  1104. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  1105. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  1106. {"Analog Left Capture Route", "AUXL", "AUXL"},
  1107. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  1108. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  1109. {"Analog Right Capture Route", "AUXR", "AUXR"},
  1110. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  1111. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  1112. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1113. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1114. /* TX1 Left capture path */
  1115. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1116. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1117. /* TX1 Right capture path */
  1118. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1119. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1120. /* TX2 Left capture path */
  1121. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1122. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1123. /* TX2 Right capture path */
  1124. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1125. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1126. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1127. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1128. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1129. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1130. /* Analog bypass routes */
  1131. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1132. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1133. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1134. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1135. {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
  1136. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1137. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1138. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1139. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1140. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1141. /* Digital bypass routes */
  1142. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1143. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1144. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1145. {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1146. {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1147. {"Analog Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1148. };
  1149. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1150. {
  1151. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1152. ARRAY_SIZE(twl4030_dapm_widgets));
  1153. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1154. snd_soc_dapm_new_widgets(codec);
  1155. return 0;
  1156. }
  1157. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1158. enum snd_soc_bias_level level)
  1159. {
  1160. struct twl4030_priv *twl4030 = codec->private_data;
  1161. switch (level) {
  1162. case SND_SOC_BIAS_ON:
  1163. twl4030_codec_mute(codec, 0);
  1164. break;
  1165. case SND_SOC_BIAS_PREPARE:
  1166. twl4030_power_up(codec);
  1167. if (twl4030->bypass_state)
  1168. twl4030_codec_mute(codec, 0);
  1169. else
  1170. twl4030_codec_mute(codec, 1);
  1171. break;
  1172. case SND_SOC_BIAS_STANDBY:
  1173. twl4030_power_up(codec);
  1174. if (twl4030->bypass_state)
  1175. twl4030_codec_mute(codec, 0);
  1176. else
  1177. twl4030_codec_mute(codec, 1);
  1178. break;
  1179. case SND_SOC_BIAS_OFF:
  1180. twl4030_power_down(codec);
  1181. break;
  1182. }
  1183. codec->bias_level = level;
  1184. return 0;
  1185. }
  1186. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1187. struct snd_pcm_substream *mst_substream)
  1188. {
  1189. struct snd_pcm_substream *slv_substream;
  1190. /* Pick the stream, which need to be constrained */
  1191. if (mst_substream == twl4030->master_substream)
  1192. slv_substream = twl4030->slave_substream;
  1193. else if (mst_substream == twl4030->slave_substream)
  1194. slv_substream = twl4030->master_substream;
  1195. else /* This should not happen.. */
  1196. return;
  1197. /* Set the constraints according to the already configured stream */
  1198. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1199. SNDRV_PCM_HW_PARAM_RATE,
  1200. twl4030->rate,
  1201. twl4030->rate);
  1202. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1203. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1204. twl4030->sample_bits,
  1205. twl4030->sample_bits);
  1206. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1207. SNDRV_PCM_HW_PARAM_CHANNELS,
  1208. twl4030->channels,
  1209. twl4030->channels);
  1210. }
  1211. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1212. * capture has to be enabled/disabled. */
  1213. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1214. int enable)
  1215. {
  1216. u8 reg, mask;
  1217. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1218. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1219. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1220. else
  1221. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1222. if (enable)
  1223. reg |= mask;
  1224. else
  1225. reg &= ~mask;
  1226. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1227. }
  1228. static int twl4030_startup(struct snd_pcm_substream *substream,
  1229. struct snd_soc_dai *dai)
  1230. {
  1231. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1232. struct snd_soc_device *socdev = rtd->socdev;
  1233. struct snd_soc_codec *codec = socdev->card->codec;
  1234. struct twl4030_priv *twl4030 = codec->private_data;
  1235. if (twl4030->master_substream) {
  1236. twl4030->slave_substream = substream;
  1237. /* The DAI has one configuration for playback and capture, so
  1238. * if the DAI has been already configured then constrain this
  1239. * substream to match it. */
  1240. if (twl4030->configured)
  1241. twl4030_constraints(twl4030, twl4030->master_substream);
  1242. } else {
  1243. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1244. TWL4030_OPTION_1)) {
  1245. /* In option2 4 channel is not supported, set the
  1246. * constraint for the first stream for channels, the
  1247. * second stream will 'inherit' this cosntraint */
  1248. snd_pcm_hw_constraint_minmax(substream->runtime,
  1249. SNDRV_PCM_HW_PARAM_CHANNELS,
  1250. 2, 2);
  1251. }
  1252. twl4030->master_substream = substream;
  1253. }
  1254. return 0;
  1255. }
  1256. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1257. struct snd_soc_dai *dai)
  1258. {
  1259. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1260. struct snd_soc_device *socdev = rtd->socdev;
  1261. struct snd_soc_codec *codec = socdev->card->codec;
  1262. struct twl4030_priv *twl4030 = codec->private_data;
  1263. if (twl4030->master_substream == substream)
  1264. twl4030->master_substream = twl4030->slave_substream;
  1265. twl4030->slave_substream = NULL;
  1266. /* If all streams are closed, or the remaining stream has not yet
  1267. * been configured than set the DAI as not configured. */
  1268. if (!twl4030->master_substream)
  1269. twl4030->configured = 0;
  1270. else if (!twl4030->master_substream->runtime->channels)
  1271. twl4030->configured = 0;
  1272. /* If the closing substream had 4 channel, do the necessary cleanup */
  1273. if (substream->runtime->channels == 4)
  1274. twl4030_tdm_enable(codec, substream->stream, 0);
  1275. }
  1276. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1277. struct snd_pcm_hw_params *params,
  1278. struct snd_soc_dai *dai)
  1279. {
  1280. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1281. struct snd_soc_device *socdev = rtd->socdev;
  1282. struct snd_soc_codec *codec = socdev->card->codec;
  1283. struct twl4030_priv *twl4030 = codec->private_data;
  1284. u8 mode, old_mode, format, old_format;
  1285. /* If the substream has 4 channel, do the necessary setup */
  1286. if (params_channels(params) == 4) {
  1287. /* Safety check: are we in the correct operating mode? */
  1288. if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1289. TWL4030_OPTION_1))
  1290. twl4030_tdm_enable(codec, substream->stream, 1);
  1291. else
  1292. return -EINVAL;
  1293. }
  1294. if (twl4030->configured)
  1295. /* Ignoring hw_params for already configured DAI */
  1296. return 0;
  1297. /* bit rate */
  1298. old_mode = twl4030_read_reg_cache(codec,
  1299. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1300. mode = old_mode & ~TWL4030_APLL_RATE;
  1301. switch (params_rate(params)) {
  1302. case 8000:
  1303. mode |= TWL4030_APLL_RATE_8000;
  1304. break;
  1305. case 11025:
  1306. mode |= TWL4030_APLL_RATE_11025;
  1307. break;
  1308. case 12000:
  1309. mode |= TWL4030_APLL_RATE_12000;
  1310. break;
  1311. case 16000:
  1312. mode |= TWL4030_APLL_RATE_16000;
  1313. break;
  1314. case 22050:
  1315. mode |= TWL4030_APLL_RATE_22050;
  1316. break;
  1317. case 24000:
  1318. mode |= TWL4030_APLL_RATE_24000;
  1319. break;
  1320. case 32000:
  1321. mode |= TWL4030_APLL_RATE_32000;
  1322. break;
  1323. case 44100:
  1324. mode |= TWL4030_APLL_RATE_44100;
  1325. break;
  1326. case 48000:
  1327. mode |= TWL4030_APLL_RATE_48000;
  1328. break;
  1329. case 96000:
  1330. mode |= TWL4030_APLL_RATE_96000;
  1331. break;
  1332. default:
  1333. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1334. params_rate(params));
  1335. return -EINVAL;
  1336. }
  1337. if (mode != old_mode) {
  1338. /* change rate and set CODECPDZ */
  1339. twl4030_codec_enable(codec, 0);
  1340. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1341. twl4030_codec_enable(codec, 1);
  1342. }
  1343. /* sample size */
  1344. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1345. format = old_format;
  1346. format &= ~TWL4030_DATA_WIDTH;
  1347. switch (params_format(params)) {
  1348. case SNDRV_PCM_FORMAT_S16_LE:
  1349. format |= TWL4030_DATA_WIDTH_16S_16W;
  1350. break;
  1351. case SNDRV_PCM_FORMAT_S24_LE:
  1352. format |= TWL4030_DATA_WIDTH_32S_24W;
  1353. break;
  1354. default:
  1355. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1356. params_format(params));
  1357. return -EINVAL;
  1358. }
  1359. if (format != old_format) {
  1360. /* clear CODECPDZ before changing format (codec requirement) */
  1361. twl4030_codec_enable(codec, 0);
  1362. /* change format */
  1363. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1364. /* set CODECPDZ afterwards */
  1365. twl4030_codec_enable(codec, 1);
  1366. }
  1367. /* Store the important parameters for the DAI configuration and set
  1368. * the DAI as configured */
  1369. twl4030->configured = 1;
  1370. twl4030->rate = params_rate(params);
  1371. twl4030->sample_bits = hw_param_interval(params,
  1372. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1373. twl4030->channels = params_channels(params);
  1374. /* If both playback and capture streams are open, and one of them
  1375. * is setting the hw parameters right now (since we are here), set
  1376. * constraints to the other stream to match the current one. */
  1377. if (twl4030->slave_substream)
  1378. twl4030_constraints(twl4030, substream);
  1379. return 0;
  1380. }
  1381. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1382. int clk_id, unsigned int freq, int dir)
  1383. {
  1384. struct snd_soc_codec *codec = codec_dai->codec;
  1385. u8 infreq;
  1386. switch (freq) {
  1387. case 19200000:
  1388. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1389. break;
  1390. case 26000000:
  1391. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1392. break;
  1393. case 38400000:
  1394. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1395. break;
  1396. default:
  1397. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1398. freq);
  1399. return -EINVAL;
  1400. }
  1401. infreq |= TWL4030_APLL_EN;
  1402. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1403. return 0;
  1404. }
  1405. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1406. unsigned int fmt)
  1407. {
  1408. struct snd_soc_codec *codec = codec_dai->codec;
  1409. u8 old_format, format;
  1410. /* get format */
  1411. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1412. format = old_format;
  1413. /* set master/slave audio interface */
  1414. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1415. case SND_SOC_DAIFMT_CBM_CFM:
  1416. format &= ~(TWL4030_AIF_SLAVE_EN);
  1417. format &= ~(TWL4030_CLK256FS_EN);
  1418. break;
  1419. case SND_SOC_DAIFMT_CBS_CFS:
  1420. format |= TWL4030_AIF_SLAVE_EN;
  1421. format |= TWL4030_CLK256FS_EN;
  1422. break;
  1423. default:
  1424. return -EINVAL;
  1425. }
  1426. /* interface format */
  1427. format &= ~TWL4030_AIF_FORMAT;
  1428. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1429. case SND_SOC_DAIFMT_I2S:
  1430. format |= TWL4030_AIF_FORMAT_CODEC;
  1431. break;
  1432. case SND_SOC_DAIFMT_DSP_A:
  1433. format |= TWL4030_AIF_FORMAT_TDM;
  1434. break;
  1435. default:
  1436. return -EINVAL;
  1437. }
  1438. if (format != old_format) {
  1439. /* clear CODECPDZ before changing format (codec requirement) */
  1440. twl4030_codec_enable(codec, 0);
  1441. /* change format */
  1442. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1443. /* set CODECPDZ afterwards */
  1444. twl4030_codec_enable(codec, 1);
  1445. }
  1446. return 0;
  1447. }
  1448. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1449. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1450. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1451. int enable)
  1452. {
  1453. u8 reg, mask;
  1454. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1455. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1456. mask = TWL4030_ARXL1_VRX_EN;
  1457. else
  1458. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1459. if (enable)
  1460. reg |= mask;
  1461. else
  1462. reg &= ~mask;
  1463. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1464. }
  1465. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1466. struct snd_soc_dai *dai)
  1467. {
  1468. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1469. struct snd_soc_device *socdev = rtd->socdev;
  1470. struct snd_soc_codec *codec = socdev->card->codec;
  1471. u8 infreq;
  1472. u8 mode;
  1473. /* If the system master clock is not 26MHz, the voice PCM interface is
  1474. * not avilable.
  1475. */
  1476. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1477. & TWL4030_APLL_INFREQ;
  1478. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1479. printk(KERN_ERR "TWL4030 voice startup: "
  1480. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1481. return -EINVAL;
  1482. }
  1483. /* If the codec mode is not option2, the voice PCM interface is not
  1484. * avilable.
  1485. */
  1486. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1487. & TWL4030_OPT_MODE;
  1488. if (mode != TWL4030_OPTION_2) {
  1489. printk(KERN_ERR "TWL4030 voice startup: "
  1490. "the codec mode is not option2\n");
  1491. return -EINVAL;
  1492. }
  1493. return 0;
  1494. }
  1495. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1496. struct snd_soc_dai *dai)
  1497. {
  1498. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1499. struct snd_soc_device *socdev = rtd->socdev;
  1500. struct snd_soc_codec *codec = socdev->card->codec;
  1501. /* Enable voice digital filters */
  1502. twl4030_voice_enable(codec, substream->stream, 0);
  1503. }
  1504. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1505. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1506. {
  1507. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1508. struct snd_soc_device *socdev = rtd->socdev;
  1509. struct snd_soc_codec *codec = socdev->card->codec;
  1510. u8 old_mode, mode;
  1511. /* Enable voice digital filters */
  1512. twl4030_voice_enable(codec, substream->stream, 1);
  1513. /* bit rate */
  1514. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1515. & ~(TWL4030_CODECPDZ);
  1516. mode = old_mode;
  1517. switch (params_rate(params)) {
  1518. case 8000:
  1519. mode &= ~(TWL4030_SEL_16K);
  1520. break;
  1521. case 16000:
  1522. mode |= TWL4030_SEL_16K;
  1523. break;
  1524. default:
  1525. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1526. params_rate(params));
  1527. return -EINVAL;
  1528. }
  1529. if (mode != old_mode) {
  1530. /* change rate and set CODECPDZ */
  1531. twl4030_codec_enable(codec, 0);
  1532. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1533. twl4030_codec_enable(codec, 1);
  1534. }
  1535. return 0;
  1536. }
  1537. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1538. int clk_id, unsigned int freq, int dir)
  1539. {
  1540. struct snd_soc_codec *codec = codec_dai->codec;
  1541. u8 infreq;
  1542. switch (freq) {
  1543. case 26000000:
  1544. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1545. break;
  1546. default:
  1547. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1548. freq);
  1549. return -EINVAL;
  1550. }
  1551. infreq |= TWL4030_APLL_EN;
  1552. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1553. return 0;
  1554. }
  1555. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1556. unsigned int fmt)
  1557. {
  1558. struct snd_soc_codec *codec = codec_dai->codec;
  1559. u8 old_format, format;
  1560. /* get format */
  1561. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1562. format = old_format;
  1563. /* set master/slave audio interface */
  1564. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1565. case SND_SOC_DAIFMT_CBS_CFM:
  1566. format &= ~(TWL4030_VIF_SLAVE_EN);
  1567. break;
  1568. case SND_SOC_DAIFMT_CBS_CFS:
  1569. format |= TWL4030_VIF_SLAVE_EN;
  1570. break;
  1571. default:
  1572. return -EINVAL;
  1573. }
  1574. /* clock inversion */
  1575. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1576. case SND_SOC_DAIFMT_IB_NF:
  1577. format &= ~(TWL4030_VIF_FORMAT);
  1578. break;
  1579. case SND_SOC_DAIFMT_NB_IF:
  1580. format |= TWL4030_VIF_FORMAT;
  1581. break;
  1582. default:
  1583. return -EINVAL;
  1584. }
  1585. if (format != old_format) {
  1586. /* change format and set CODECPDZ */
  1587. twl4030_codec_enable(codec, 0);
  1588. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1589. twl4030_codec_enable(codec, 1);
  1590. }
  1591. return 0;
  1592. }
  1593. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1594. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1595. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1596. .startup = twl4030_startup,
  1597. .shutdown = twl4030_shutdown,
  1598. .hw_params = twl4030_hw_params,
  1599. .set_sysclk = twl4030_set_dai_sysclk,
  1600. .set_fmt = twl4030_set_dai_fmt,
  1601. };
  1602. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1603. .startup = twl4030_voice_startup,
  1604. .shutdown = twl4030_voice_shutdown,
  1605. .hw_params = twl4030_voice_hw_params,
  1606. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1607. .set_fmt = twl4030_voice_set_dai_fmt,
  1608. };
  1609. struct snd_soc_dai twl4030_dai[] = {
  1610. {
  1611. .name = "twl4030",
  1612. .playback = {
  1613. .stream_name = "Playback",
  1614. .channels_min = 2,
  1615. .channels_max = 4,
  1616. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1617. .formats = TWL4030_FORMATS,},
  1618. .capture = {
  1619. .stream_name = "Capture",
  1620. .channels_min = 2,
  1621. .channels_max = 4,
  1622. .rates = TWL4030_RATES,
  1623. .formats = TWL4030_FORMATS,},
  1624. .ops = &twl4030_dai_ops,
  1625. },
  1626. {
  1627. .name = "twl4030 Voice",
  1628. .playback = {
  1629. .stream_name = "Playback",
  1630. .channels_min = 1,
  1631. .channels_max = 1,
  1632. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1633. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1634. .capture = {
  1635. .stream_name = "Capture",
  1636. .channels_min = 1,
  1637. .channels_max = 2,
  1638. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1639. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1640. .ops = &twl4030_dai_voice_ops,
  1641. },
  1642. };
  1643. EXPORT_SYMBOL_GPL(twl4030_dai);
  1644. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1645. {
  1646. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1647. struct snd_soc_codec *codec = socdev->card->codec;
  1648. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1649. return 0;
  1650. }
  1651. static int twl4030_resume(struct platform_device *pdev)
  1652. {
  1653. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1654. struct snd_soc_codec *codec = socdev->card->codec;
  1655. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1656. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1657. return 0;
  1658. }
  1659. /*
  1660. * initialize the driver
  1661. * register the mixer and dsp interfaces with the kernel
  1662. */
  1663. static int twl4030_init(struct snd_soc_device *socdev)
  1664. {
  1665. struct snd_soc_codec *codec = socdev->card->codec;
  1666. int ret = 0;
  1667. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1668. codec->name = "twl4030";
  1669. codec->owner = THIS_MODULE;
  1670. codec->read = twl4030_read_reg_cache;
  1671. codec->write = twl4030_write;
  1672. codec->set_bias_level = twl4030_set_bias_level;
  1673. codec->dai = twl4030_dai;
  1674. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1675. codec->reg_cache_size = sizeof(twl4030_reg);
  1676. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1677. GFP_KERNEL);
  1678. if (codec->reg_cache == NULL)
  1679. return -ENOMEM;
  1680. /* register pcms */
  1681. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1682. if (ret < 0) {
  1683. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1684. goto pcm_err;
  1685. }
  1686. twl4030_init_chip(codec);
  1687. /* power on device */
  1688. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1689. snd_soc_add_controls(codec, twl4030_snd_controls,
  1690. ARRAY_SIZE(twl4030_snd_controls));
  1691. twl4030_add_widgets(codec);
  1692. ret = snd_soc_init_card(socdev);
  1693. if (ret < 0) {
  1694. printk(KERN_ERR "twl4030: failed to register card\n");
  1695. goto card_err;
  1696. }
  1697. return ret;
  1698. card_err:
  1699. snd_soc_free_pcms(socdev);
  1700. snd_soc_dapm_free(socdev);
  1701. pcm_err:
  1702. kfree(codec->reg_cache);
  1703. return ret;
  1704. }
  1705. static struct snd_soc_device *twl4030_socdev;
  1706. static int twl4030_probe(struct platform_device *pdev)
  1707. {
  1708. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1709. struct snd_soc_codec *codec;
  1710. struct twl4030_priv *twl4030;
  1711. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1712. if (codec == NULL)
  1713. return -ENOMEM;
  1714. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1715. if (twl4030 == NULL) {
  1716. kfree(codec);
  1717. return -ENOMEM;
  1718. }
  1719. codec->private_data = twl4030;
  1720. socdev->card->codec = codec;
  1721. mutex_init(&codec->mutex);
  1722. INIT_LIST_HEAD(&codec->dapm_widgets);
  1723. INIT_LIST_HEAD(&codec->dapm_paths);
  1724. twl4030_socdev = socdev;
  1725. twl4030_init(socdev);
  1726. return 0;
  1727. }
  1728. static int twl4030_remove(struct platform_device *pdev)
  1729. {
  1730. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1731. struct snd_soc_codec *codec = socdev->card->codec;
  1732. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1733. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1734. snd_soc_free_pcms(socdev);
  1735. snd_soc_dapm_free(socdev);
  1736. kfree(codec->private_data);
  1737. kfree(codec);
  1738. return 0;
  1739. }
  1740. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1741. .probe = twl4030_probe,
  1742. .remove = twl4030_remove,
  1743. .suspend = twl4030_suspend,
  1744. .resume = twl4030_resume,
  1745. };
  1746. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1747. static int __init twl4030_modinit(void)
  1748. {
  1749. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1750. }
  1751. module_init(twl4030_modinit);
  1752. static void __exit twl4030_exit(void)
  1753. {
  1754. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1755. }
  1756. module_exit(twl4030_exit);
  1757. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1758. MODULE_AUTHOR("Steve Sakoman");
  1759. MODULE_LICENSE("GPL");