ide.h 5.0 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994-1996 Linus Torvalds & authors
  7. *
  8. * Copied from i386; many of the especially older MIPS or ISA-based platforms
  9. * are basically identical. Using this file probably implies i8259 PIC
  10. * support in a system but the very least interrupt numbers 0 - 15 need to
  11. * be put aside for legacy devices.
  12. */
  13. #ifndef __ASM_MACH_GENERIC_IDE_H
  14. #define __ASM_MACH_GENERIC_IDE_H
  15. #ifdef __KERNEL__
  16. #include <linux/pci.h>
  17. #include <linux/stddef.h>
  18. #include <asm/processor.h>
  19. #ifndef MAX_HWIFS
  20. # ifdef CONFIG_BLK_DEV_IDEPCI
  21. #define MAX_HWIFS 10
  22. # else
  23. #define MAX_HWIFS 6
  24. # endif
  25. #endif
  26. static __inline__ int ide_probe_legacy(void)
  27. {
  28. #ifdef CONFIG_PCI
  29. struct pci_dev *dev;
  30. /*
  31. * This can be called on the ide_setup() path, super-early in
  32. * boot. But the down_read() will enable local interrupts,
  33. * which can cause some machines to crash. So here we detect
  34. * and flag that situation and bail out early.
  35. */
  36. if (no_pci_devices())
  37. return 0;
  38. dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
  39. if (dev)
  40. goto found;
  41. dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  42. if (dev)
  43. goto found;
  44. return 0;
  45. found:
  46. pci_dev_put(dev);
  47. return 1;
  48. #elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
  49. return 1;
  50. #else
  51. return 0;
  52. #endif
  53. }
  54. static __inline__ int ide_default_irq(unsigned long base)
  55. {
  56. switch (base) {
  57. case 0x1f0: return 14;
  58. case 0x170: return 15;
  59. case 0x1e8: return 11;
  60. case 0x168: return 10;
  61. case 0x1e0: return 8;
  62. case 0x160: return 12;
  63. default:
  64. return 0;
  65. }
  66. }
  67. static __inline__ unsigned long ide_default_io_base(int index)
  68. {
  69. switch (index) {
  70. case 0: return 0x1f0;
  71. case 1: return 0x170;
  72. case 2: return 0x1e8;
  73. case 3: return 0x168;
  74. case 4: return 0x1e0;
  75. case 5: return 0x160;
  76. default:
  77. return 0;
  78. }
  79. }
  80. /* MIPS port and memory-mapped I/O string operations. */
  81. static inline void __ide_flush_prologue(void)
  82. {
  83. #ifdef CONFIG_SMP
  84. if (cpu_has_dc_aliases)
  85. preempt_disable();
  86. #endif
  87. }
  88. static inline void __ide_flush_epilogue(void)
  89. {
  90. #ifdef CONFIG_SMP
  91. if (cpu_has_dc_aliases)
  92. preempt_enable();
  93. #endif
  94. }
  95. static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
  96. {
  97. if (cpu_has_dc_aliases) {
  98. unsigned long end = addr + size;
  99. while (addr < end) {
  100. local_flush_data_cache_page((void *)addr);
  101. addr += PAGE_SIZE;
  102. }
  103. }
  104. }
  105. /*
  106. * insw() and gang might be called with interrupts disabled, so we can't
  107. * send IPIs for flushing due to the potencial of deadlocks, see the comment
  108. * above smp_call_function() in arch/mips/kernel/smp.c. We work around the
  109. * problem by disabling preemption so we know we actually perform the flush
  110. * on the processor that actually has the lines to be flushed which hopefully
  111. * is even better for performance anyway.
  112. */
  113. static inline void __ide_insw(unsigned long port, void *addr,
  114. unsigned int count)
  115. {
  116. __ide_flush_prologue();
  117. insw(port, addr, count);
  118. __ide_flush_dcache_range((unsigned long)addr, count * 2);
  119. __ide_flush_epilogue();
  120. }
  121. static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
  122. {
  123. __ide_flush_prologue();
  124. insl(port, addr, count);
  125. __ide_flush_dcache_range((unsigned long)addr, count * 4);
  126. __ide_flush_epilogue();
  127. }
  128. static inline void __ide_outsw(unsigned long port, const void *addr,
  129. unsigned long count)
  130. {
  131. __ide_flush_prologue();
  132. outsw(port, addr, count);
  133. __ide_flush_dcache_range((unsigned long)addr, count * 2);
  134. __ide_flush_epilogue();
  135. }
  136. static inline void __ide_outsl(unsigned long port, const void *addr,
  137. unsigned long count)
  138. {
  139. __ide_flush_prologue();
  140. outsl(port, addr, count);
  141. __ide_flush_dcache_range((unsigned long)addr, count * 4);
  142. __ide_flush_epilogue();
  143. }
  144. static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
  145. {
  146. __ide_flush_prologue();
  147. readsw(port, addr, count);
  148. __ide_flush_dcache_range((unsigned long)addr, count * 2);
  149. __ide_flush_epilogue();
  150. }
  151. static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
  152. {
  153. __ide_flush_prologue();
  154. readsl(port, addr, count);
  155. __ide_flush_dcache_range((unsigned long)addr, count * 4);
  156. __ide_flush_epilogue();
  157. }
  158. static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
  159. {
  160. __ide_flush_prologue();
  161. writesw(port, addr, count);
  162. __ide_flush_dcache_range((unsigned long)addr, count * 2);
  163. __ide_flush_epilogue();
  164. }
  165. static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
  166. {
  167. __ide_flush_prologue();
  168. writesl(port, addr, count);
  169. __ide_flush_dcache_range((unsigned long)addr, count * 4);
  170. __ide_flush_epilogue();
  171. }
  172. /* ide_insw calls insw, not __ide_insw. Why? */
  173. #undef insw
  174. #undef insl
  175. #undef outsw
  176. #undef outsl
  177. #define insw(port, addr, count) __ide_insw(port, addr, count)
  178. #define insl(port, addr, count) __ide_insl(port, addr, count)
  179. #define outsw(port, addr, count) __ide_outsw(port, addr, count)
  180. #define outsl(port, addr, count) __ide_outsl(port, addr, count)
  181. #endif /* __KERNEL__ */
  182. #endif /* __ASM_MACH_GENERIC_IDE_H */