mpc52xx_uart.c 22 KB

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  1. /*
  2. * drivers/serial/mpc52xx_uart.c
  3. *
  4. * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
  5. *
  6. * FIXME According to the usermanual the status bits in the status register
  7. * are only updated when the peripherals access the FIFO and not when the
  8. * CPU access them. So since we use this bits to know when we stop writing
  9. * and reading, they may not be updated in-time and a race condition may
  10. * exists. But I haven't be able to prove this and I don't care. But if
  11. * any problem arises, it might worth checking. The TX/RX FIFO Stats
  12. * registers should be used in addition.
  13. * Update: Actually, they seem updated ... At least the bits we use.
  14. *
  15. *
  16. * Maintainer : Sylvain Munaut <tnt@246tNt.com>
  17. *
  18. * Some of the code has been inspired/copied from the 2.4 code written
  19. * by Dale Farnsworth <dfarnsworth@mvista.com>.
  20. *
  21. * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
  22. * Copyright (C) 2003 MontaVista, Software, Inc.
  23. *
  24. * This file is licensed under the terms of the GNU General Public License
  25. * version 2. This program is licensed "as is" without any warranty of any
  26. * kind, whether express or implied.
  27. */
  28. /* Platform device Usage :
  29. *
  30. * Since PSCs can have multiple function, the correct driver for each one
  31. * is selected by calling mpc52xx_match_psc_function(...). The function
  32. * handled by this driver is "uart".
  33. *
  34. * The driver init all necessary registers to place the PSC in uart mode without
  35. * DCD. However, the pin multiplexing aren't changed and should be set either
  36. * by the bootloader or in the platform init code.
  37. *
  38. * The idx field must be equal to the PSC index ( e.g. 0 for PSC1, 1 for PSC2,
  39. * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and
  40. * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly
  41. * fpr the console code : without this 1:1 mapping, at early boot time, when we
  42. * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it
  43. * will be mapped to.
  44. */
  45. #include <linux/platform_device.h>
  46. #include <linux/module.h>
  47. #include <linux/tty.h>
  48. #include <linux/serial.h>
  49. #include <linux/sysrq.h>
  50. #include <linux/console.h>
  51. #include <asm/delay.h>
  52. #include <asm/io.h>
  53. #include <asm/mpc52xx.h>
  54. #include <asm/mpc52xx_psc.h>
  55. #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  56. #define SUPPORT_SYSRQ
  57. #endif
  58. #include <linux/serial_core.h>
  59. /* We've been assigned a range on the "Low-density serial ports" major */
  60. #define SERIAL_PSC_MAJOR 204
  61. #define SERIAL_PSC_MINOR 148
  62. #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
  63. static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
  64. /* Rem: - We use the read_status_mask as a shadow of
  65. * psc->mpc52xx_psc_imr
  66. * - It's important that is array is all zero on start as we
  67. * use it to know if it's initialized or not ! If it's not sure
  68. * it's cleared, then a memset(...,0,...) should be added to
  69. * the console_init
  70. */
  71. #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
  72. /* Forward declaration of the interruption handling routine */
  73. static irqreturn_t mpc52xx_uart_int(int irq,void *dev_id,struct pt_regs *regs);
  74. /* Simple macro to test if a port is console or not. This one is taken
  75. * for serial_core.c and maybe should be moved to serial_core.h ? */
  76. #ifdef CONFIG_SERIAL_CORE_CONSOLE
  77. #define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
  78. #else
  79. #define uart_console(port) (0)
  80. #endif
  81. /* ======================================================================== */
  82. /* UART operations */
  83. /* ======================================================================== */
  84. static unsigned int
  85. mpc52xx_uart_tx_empty(struct uart_port *port)
  86. {
  87. int status = in_be16(&PSC(port)->mpc52xx_psc_status);
  88. return (status & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
  89. }
  90. static void
  91. mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  92. {
  93. /* Not implemented */
  94. }
  95. static unsigned int
  96. mpc52xx_uart_get_mctrl(struct uart_port *port)
  97. {
  98. /* Not implemented */
  99. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  100. }
  101. static void
  102. mpc52xx_uart_stop_tx(struct uart_port *port)
  103. {
  104. /* port->lock taken by caller */
  105. port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
  106. out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
  107. }
  108. static void
  109. mpc52xx_uart_start_tx(struct uart_port *port)
  110. {
  111. /* port->lock taken by caller */
  112. port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
  113. out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
  114. }
  115. static void
  116. mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
  117. {
  118. unsigned long flags;
  119. spin_lock_irqsave(&port->lock, flags);
  120. port->x_char = ch;
  121. if (ch) {
  122. /* Make sure tx interrupts are on */
  123. /* Truly necessary ??? They should be anyway */
  124. port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
  125. out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
  126. }
  127. spin_unlock_irqrestore(&port->lock, flags);
  128. }
  129. static void
  130. mpc52xx_uart_stop_rx(struct uart_port *port)
  131. {
  132. /* port->lock taken by caller */
  133. port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
  134. out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask);
  135. }
  136. static void
  137. mpc52xx_uart_enable_ms(struct uart_port *port)
  138. {
  139. /* Not implemented */
  140. }
  141. static void
  142. mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
  143. {
  144. unsigned long flags;
  145. spin_lock_irqsave(&port->lock, flags);
  146. if ( ctl == -1 )
  147. out_8(&PSC(port)->command,MPC52xx_PSC_START_BRK);
  148. else
  149. out_8(&PSC(port)->command,MPC52xx_PSC_STOP_BRK);
  150. spin_unlock_irqrestore(&port->lock, flags);
  151. }
  152. static int
  153. mpc52xx_uart_startup(struct uart_port *port)
  154. {
  155. struct mpc52xx_psc __iomem *psc = PSC(port);
  156. int ret;
  157. /* Request IRQ */
  158. ret = request_irq(port->irq, mpc52xx_uart_int,
  159. IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "mpc52xx_psc_uart", port);
  160. if (ret)
  161. return ret;
  162. /* Reset/activate the port, clear and enable interrupts */
  163. out_8(&psc->command,MPC52xx_PSC_RST_RX);
  164. out_8(&psc->command,MPC52xx_PSC_RST_TX);
  165. out_be32(&psc->sicr,0); /* UART mode DCD ignored */
  166. out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); /* /16 prescaler on */
  167. out_8(&psc->rfcntl, 0x00);
  168. out_be16(&psc->rfalarm, 0x1ff);
  169. out_8(&psc->tfcntl, 0x07);
  170. out_be16(&psc->tfalarm, 0x80);
  171. port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
  172. out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask);
  173. out_8(&psc->command,MPC52xx_PSC_TX_ENABLE);
  174. out_8(&psc->command,MPC52xx_PSC_RX_ENABLE);
  175. return 0;
  176. }
  177. static void
  178. mpc52xx_uart_shutdown(struct uart_port *port)
  179. {
  180. struct mpc52xx_psc __iomem *psc = PSC(port);
  181. /* Shut down the port, interrupt and all */
  182. out_8(&psc->command,MPC52xx_PSC_RST_RX);
  183. out_8(&psc->command,MPC52xx_PSC_RST_TX);
  184. port->read_status_mask = 0;
  185. out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask);
  186. /* Release interrupt */
  187. free_irq(port->irq, port);
  188. }
  189. static void
  190. mpc52xx_uart_set_termios(struct uart_port *port, struct termios *new,
  191. struct termios *old)
  192. {
  193. struct mpc52xx_psc __iomem *psc = PSC(port);
  194. unsigned long flags;
  195. unsigned char mr1, mr2;
  196. unsigned short ctr;
  197. unsigned int j, baud, quot;
  198. /* Prepare what we're gonna write */
  199. mr1 = 0;
  200. switch (new->c_cflag & CSIZE) {
  201. case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
  202. break;
  203. case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
  204. break;
  205. case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
  206. break;
  207. case CS8:
  208. default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
  209. }
  210. if (new->c_cflag & PARENB) {
  211. mr1 |= (new->c_cflag & PARODD) ?
  212. MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
  213. } else
  214. mr1 |= MPC52xx_PSC_MODE_PARNONE;
  215. mr2 = 0;
  216. if (new->c_cflag & CSTOPB)
  217. mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
  218. else
  219. mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
  220. MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
  221. MPC52xx_PSC_MODE_ONE_STOP;
  222. baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
  223. quot = uart_get_divisor(port, baud);
  224. ctr = quot & 0xffff;
  225. /* Get the lock */
  226. spin_lock_irqsave(&port->lock, flags);
  227. /* Update the per-port timeout */
  228. uart_update_timeout(port, new->c_cflag, baud);
  229. /* Do our best to flush TX & RX, so we don't loose anything */
  230. /* But we don't wait indefinitly ! */
  231. j = 5000000; /* Maximum wait */
  232. /* FIXME Can't receive chars since set_termios might be called at early
  233. * boot for the console, all stuff is not yet ready to receive at that
  234. * time and that just makes the kernel oops */
  235. /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
  236. while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) &&
  237. --j)
  238. udelay(1);
  239. if (!j)
  240. printk( KERN_ERR "mpc52xx_uart.c: "
  241. "Unable to flush RX & TX fifos in-time in set_termios."
  242. "Some chars may have been lost.\n" );
  243. /* Reset the TX & RX */
  244. out_8(&psc->command,MPC52xx_PSC_RST_RX);
  245. out_8(&psc->command,MPC52xx_PSC_RST_TX);
  246. /* Send new mode settings */
  247. out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1);
  248. out_8(&psc->mode,mr1);
  249. out_8(&psc->mode,mr2);
  250. out_8(&psc->ctur,ctr >> 8);
  251. out_8(&psc->ctlr,ctr & 0xff);
  252. /* Reenable TX & RX */
  253. out_8(&psc->command,MPC52xx_PSC_TX_ENABLE);
  254. out_8(&psc->command,MPC52xx_PSC_RX_ENABLE);
  255. /* We're all set, release the lock */
  256. spin_unlock_irqrestore(&port->lock, flags);
  257. }
  258. static const char *
  259. mpc52xx_uart_type(struct uart_port *port)
  260. {
  261. return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
  262. }
  263. static void
  264. mpc52xx_uart_release_port(struct uart_port *port)
  265. {
  266. if (port->flags & UPF_IOREMAP) { /* remapped by us ? */
  267. iounmap(port->membase);
  268. port->membase = NULL;
  269. }
  270. release_mem_region(port->mapbase, MPC52xx_PSC_SIZE);
  271. }
  272. static int
  273. mpc52xx_uart_request_port(struct uart_port *port)
  274. {
  275. int err;
  276. if (port->flags & UPF_IOREMAP) /* Need to remap ? */
  277. port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
  278. if (!port->membase)
  279. return -EINVAL;
  280. err = request_mem_region(port->mapbase, MPC52xx_PSC_SIZE,
  281. "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
  282. if (err && (port->flags & UPF_IOREMAP)) {
  283. iounmap(port->membase);
  284. port->membase = NULL;
  285. }
  286. return err;
  287. }
  288. static void
  289. mpc52xx_uart_config_port(struct uart_port *port, int flags)
  290. {
  291. if ( (flags & UART_CONFIG_TYPE) &&
  292. (mpc52xx_uart_request_port(port) == 0) )
  293. port->type = PORT_MPC52xx;
  294. }
  295. static int
  296. mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
  297. {
  298. if ( ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx )
  299. return -EINVAL;
  300. if ( (ser->irq != port->irq) ||
  301. (ser->io_type != SERIAL_IO_MEM) ||
  302. (ser->baud_base != port->uartclk) ||
  303. (ser->iomem_base != (void*)port->mapbase) ||
  304. (ser->hub6 != 0 ) )
  305. return -EINVAL;
  306. return 0;
  307. }
  308. static struct uart_ops mpc52xx_uart_ops = {
  309. .tx_empty = mpc52xx_uart_tx_empty,
  310. .set_mctrl = mpc52xx_uart_set_mctrl,
  311. .get_mctrl = mpc52xx_uart_get_mctrl,
  312. .stop_tx = mpc52xx_uart_stop_tx,
  313. .start_tx = mpc52xx_uart_start_tx,
  314. .send_xchar = mpc52xx_uart_send_xchar,
  315. .stop_rx = mpc52xx_uart_stop_rx,
  316. .enable_ms = mpc52xx_uart_enable_ms,
  317. .break_ctl = mpc52xx_uart_break_ctl,
  318. .startup = mpc52xx_uart_startup,
  319. .shutdown = mpc52xx_uart_shutdown,
  320. .set_termios = mpc52xx_uart_set_termios,
  321. /* .pm = mpc52xx_uart_pm, Not supported yet */
  322. /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
  323. .type = mpc52xx_uart_type,
  324. .release_port = mpc52xx_uart_release_port,
  325. .request_port = mpc52xx_uart_request_port,
  326. .config_port = mpc52xx_uart_config_port,
  327. .verify_port = mpc52xx_uart_verify_port
  328. };
  329. /* ======================================================================== */
  330. /* Interrupt handling */
  331. /* ======================================================================== */
  332. static inline int
  333. mpc52xx_uart_int_rx_chars(struct uart_port *port, struct pt_regs *regs)
  334. {
  335. struct tty_struct *tty = port->info->tty;
  336. unsigned char ch, flag;
  337. unsigned short status;
  338. /* While we can read, do so ! */
  339. while ( (status = in_be16(&PSC(port)->mpc52xx_psc_status)) &
  340. MPC52xx_PSC_SR_RXRDY) {
  341. /* Get the char */
  342. ch = in_8(&PSC(port)->mpc52xx_psc_buffer_8);
  343. /* Handle sysreq char */
  344. #ifdef SUPPORT_SYSRQ
  345. if (uart_handle_sysrq_char(port, ch, regs)) {
  346. port->sysrq = 0;
  347. continue;
  348. }
  349. #endif
  350. /* Store it */
  351. flag = TTY_NORMAL;
  352. port->icount.rx++;
  353. if ( status & (MPC52xx_PSC_SR_PE |
  354. MPC52xx_PSC_SR_FE |
  355. MPC52xx_PSC_SR_RB) ) {
  356. if (status & MPC52xx_PSC_SR_RB) {
  357. flag = TTY_BREAK;
  358. uart_handle_break(port);
  359. } else if (status & MPC52xx_PSC_SR_PE)
  360. flag = TTY_PARITY;
  361. else if (status & MPC52xx_PSC_SR_FE)
  362. flag = TTY_FRAME;
  363. /* Clear error condition */
  364. out_8(&PSC(port)->command,MPC52xx_PSC_RST_ERR_STAT);
  365. }
  366. tty_insert_flip_char(tty, ch, flag);
  367. if (status & MPC52xx_PSC_SR_OE) {
  368. /*
  369. * Overrun is special, since it's
  370. * reported immediately, and doesn't
  371. * affect the current character
  372. */
  373. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  374. }
  375. }
  376. tty_flip_buffer_push(tty);
  377. return in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY;
  378. }
  379. static inline int
  380. mpc52xx_uart_int_tx_chars(struct uart_port *port)
  381. {
  382. struct circ_buf *xmit = &port->info->xmit;
  383. /* Process out of band chars */
  384. if (port->x_char) {
  385. out_8(&PSC(port)->mpc52xx_psc_buffer_8, port->x_char);
  386. port->icount.tx++;
  387. port->x_char = 0;
  388. return 1;
  389. }
  390. /* Nothing to do ? */
  391. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  392. mpc52xx_uart_stop_tx(port);
  393. return 0;
  394. }
  395. /* Send chars */
  396. while (in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXRDY) {
  397. out_8(&PSC(port)->mpc52xx_psc_buffer_8, xmit->buf[xmit->tail]);
  398. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  399. port->icount.tx++;
  400. if (uart_circ_empty(xmit))
  401. break;
  402. }
  403. /* Wake up */
  404. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  405. uart_write_wakeup(port);
  406. /* Maybe we're done after all */
  407. if (uart_circ_empty(xmit)) {
  408. mpc52xx_uart_stop_tx(port);
  409. return 0;
  410. }
  411. return 1;
  412. }
  413. static irqreturn_t
  414. mpc52xx_uart_int(int irq, void *dev_id, struct pt_regs *regs)
  415. {
  416. struct uart_port *port = (struct uart_port *) dev_id;
  417. unsigned long pass = ISR_PASS_LIMIT;
  418. unsigned int keepgoing;
  419. unsigned short status;
  420. if ( irq != port->irq ) {
  421. printk( KERN_WARNING
  422. "mpc52xx_uart_int : " \
  423. "Received wrong int %d. Waiting for %d\n",
  424. irq, port->irq);
  425. return IRQ_NONE;
  426. }
  427. spin_lock(&port->lock);
  428. /* While we have stuff to do, we continue */
  429. do {
  430. /* If we don't find anything to do, we stop */
  431. keepgoing = 0;
  432. /* Read status */
  433. status = in_be16(&PSC(port)->mpc52xx_psc_isr);
  434. status &= port->read_status_mask;
  435. /* Do we need to receive chars ? */
  436. /* For this RX interrupts must be on and some chars waiting */
  437. if ( status & MPC52xx_PSC_IMR_RXRDY )
  438. keepgoing |= mpc52xx_uart_int_rx_chars(port, regs);
  439. /* Do we need to send chars ? */
  440. /* For this, TX must be ready and TX interrupt enabled */
  441. if ( status & MPC52xx_PSC_IMR_TXRDY )
  442. keepgoing |= mpc52xx_uart_int_tx_chars(port);
  443. /* Limit number of iteration */
  444. if ( !(--pass) )
  445. keepgoing = 0;
  446. } while (keepgoing);
  447. spin_unlock(&port->lock);
  448. return IRQ_HANDLED;
  449. }
  450. /* ======================================================================== */
  451. /* Console ( if applicable ) */
  452. /* ======================================================================== */
  453. #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
  454. static void __init
  455. mpc52xx_console_get_options(struct uart_port *port,
  456. int *baud, int *parity, int *bits, int *flow)
  457. {
  458. struct mpc52xx_psc __iomem *psc = PSC(port);
  459. unsigned char mr1;
  460. /* Read the mode registers */
  461. out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1);
  462. mr1 = in_8(&psc->mode);
  463. /* CT{U,L}R are write-only ! */
  464. *baud = __res.bi_baudrate ?
  465. __res.bi_baudrate : CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
  466. /* Parse them */
  467. switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
  468. case MPC52xx_PSC_MODE_5_BITS: *bits = 5; break;
  469. case MPC52xx_PSC_MODE_6_BITS: *bits = 6; break;
  470. case MPC52xx_PSC_MODE_7_BITS: *bits = 7; break;
  471. case MPC52xx_PSC_MODE_8_BITS:
  472. default: *bits = 8;
  473. }
  474. if (mr1 & MPC52xx_PSC_MODE_PARNONE)
  475. *parity = 'n';
  476. else
  477. *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
  478. }
  479. static void
  480. mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
  481. {
  482. struct uart_port *port = &mpc52xx_uart_ports[co->index];
  483. struct mpc52xx_psc __iomem *psc = PSC(port);
  484. unsigned int i, j;
  485. /* Disable interrupts */
  486. out_be16(&psc->mpc52xx_psc_imr, 0);
  487. /* Wait the TX buffer to be empty */
  488. j = 5000000; /* Maximum wait */
  489. while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) &&
  490. --j)
  491. udelay(1);
  492. /* Write all the chars */
  493. for (i = 0; i < count; i++, s++) {
  494. /* Line return handling */
  495. if (*s == '\n')
  496. out_8(&psc->mpc52xx_psc_buffer_8, '\r');
  497. /* Send the char */
  498. out_8(&psc->mpc52xx_psc_buffer_8, *s);
  499. /* Wait the TX buffer to be empty */
  500. j = 20000; /* Maximum wait */
  501. while (!(in_be16(&psc->mpc52xx_psc_status) &
  502. MPC52xx_PSC_SR_TXEMP) && --j)
  503. udelay(1);
  504. }
  505. /* Restore interrupt state */
  506. out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
  507. }
  508. static int __init
  509. mpc52xx_console_setup(struct console *co, char *options)
  510. {
  511. struct uart_port *port = &mpc52xx_uart_ports[co->index];
  512. int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
  513. int bits = 8;
  514. int parity = 'n';
  515. int flow = 'n';
  516. if (co->index < 0 || co->index >= MPC52xx_PSC_MAXNUM)
  517. return -EINVAL;
  518. /* Basic port init. Needed since we use some uart_??? func before
  519. * real init for early access */
  520. spin_lock_init(&port->lock);
  521. port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
  522. port->ops = &mpc52xx_uart_ops;
  523. port->mapbase = MPC52xx_PA(MPC52xx_PSCx_OFFSET(co->index+1));
  524. /* We ioremap ourself */
  525. port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE);
  526. if (port->membase == NULL)
  527. return -EINVAL;
  528. /* Setup the port parameters accoding to options */
  529. if (options)
  530. uart_parse_options(options, &baud, &parity, &bits, &flow);
  531. else
  532. mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
  533. return uart_set_options(port, co, baud, parity, bits, flow);
  534. }
  535. static struct uart_driver mpc52xx_uart_driver;
  536. static struct console mpc52xx_console = {
  537. .name = "ttyPSC",
  538. .write = mpc52xx_console_write,
  539. .device = uart_console_device,
  540. .setup = mpc52xx_console_setup,
  541. .flags = CON_PRINTBUFFER,
  542. .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0 ) */
  543. .data = &mpc52xx_uart_driver,
  544. };
  545. static int __init
  546. mpc52xx_console_init(void)
  547. {
  548. register_console(&mpc52xx_console);
  549. return 0;
  550. }
  551. console_initcall(mpc52xx_console_init);
  552. #define MPC52xx_PSC_CONSOLE &mpc52xx_console
  553. #else
  554. #define MPC52xx_PSC_CONSOLE NULL
  555. #endif
  556. /* ======================================================================== */
  557. /* UART Driver */
  558. /* ======================================================================== */
  559. static struct uart_driver mpc52xx_uart_driver = {
  560. .owner = THIS_MODULE,
  561. .driver_name = "mpc52xx_psc_uart",
  562. .dev_name = "ttyPSC",
  563. .major = SERIAL_PSC_MAJOR,
  564. .minor = SERIAL_PSC_MINOR,
  565. .nr = MPC52xx_PSC_MAXNUM,
  566. .cons = MPC52xx_PSC_CONSOLE,
  567. };
  568. /* ======================================================================== */
  569. /* Platform Driver */
  570. /* ======================================================================== */
  571. static int __devinit
  572. mpc52xx_uart_probe(struct platform_device *dev)
  573. {
  574. struct resource *res = dev->resource;
  575. struct uart_port *port = NULL;
  576. int i, idx, ret;
  577. /* Check validity & presence */
  578. idx = dev->id;
  579. if (idx < 0 || idx >= MPC52xx_PSC_MAXNUM)
  580. return -EINVAL;
  581. if (!mpc52xx_match_psc_function(idx,"uart"))
  582. return -ENODEV;
  583. /* Init the port structure */
  584. port = &mpc52xx_uart_ports[idx];
  585. memset(port, 0x00, sizeof(struct uart_port));
  586. spin_lock_init(&port->lock);
  587. port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */
  588. port->fifosize = 512;
  589. port->iotype = UPIO_MEM;
  590. port->flags = UPF_BOOT_AUTOCONF |
  591. ( uart_console(port) ? 0 : UPF_IOREMAP );
  592. port->line = idx;
  593. port->ops = &mpc52xx_uart_ops;
  594. /* Search for IRQ and mapbase */
  595. for (i=0 ; i<dev->num_resources ; i++, res++) {
  596. if (res->flags & IORESOURCE_MEM)
  597. port->mapbase = res->start;
  598. else if (res->flags & IORESOURCE_IRQ)
  599. port->irq = res->start;
  600. }
  601. if (!port->irq || !port->mapbase)
  602. return -EINVAL;
  603. /* Add the port to the uart sub-system */
  604. ret = uart_add_one_port(&mpc52xx_uart_driver, port);
  605. if (!ret)
  606. platform_set_drvdata(dev, (void*)port);
  607. return ret;
  608. }
  609. static int
  610. mpc52xx_uart_remove(struct platform_device *dev)
  611. {
  612. struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev);
  613. platform_set_drvdata(dev, NULL);
  614. if (port)
  615. uart_remove_one_port(&mpc52xx_uart_driver, port);
  616. return 0;
  617. }
  618. #ifdef CONFIG_PM
  619. static int
  620. mpc52xx_uart_suspend(struct platform_device *dev, pm_message_t state)
  621. {
  622. struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev);
  623. if (sport)
  624. uart_suspend_port(&mpc52xx_uart_driver, port);
  625. return 0;
  626. }
  627. static int
  628. mpc52xx_uart_resume(struct platform_device *dev)
  629. {
  630. struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev);
  631. if (port)
  632. uart_resume_port(&mpc52xx_uart_driver, port);
  633. return 0;
  634. }
  635. #endif
  636. static struct platform_driver mpc52xx_uart_platform_driver = {
  637. .probe = mpc52xx_uart_probe,
  638. .remove = mpc52xx_uart_remove,
  639. #ifdef CONFIG_PM
  640. .suspend = mpc52xx_uart_suspend,
  641. .resume = mpc52xx_uart_resume,
  642. #endif
  643. .driver = {
  644. .name = "mpc52xx-psc",
  645. },
  646. };
  647. /* ======================================================================== */
  648. /* Module */
  649. /* ======================================================================== */
  650. static int __init
  651. mpc52xx_uart_init(void)
  652. {
  653. int ret;
  654. printk(KERN_INFO "Serial: MPC52xx PSC driver\n");
  655. ret = uart_register_driver(&mpc52xx_uart_driver);
  656. if (ret == 0) {
  657. ret = platform_driver_register(&mpc52xx_uart_platform_driver);
  658. if (ret)
  659. uart_unregister_driver(&mpc52xx_uart_driver);
  660. }
  661. return ret;
  662. }
  663. static void __exit
  664. mpc52xx_uart_exit(void)
  665. {
  666. platform_driver_unregister(&mpc52xx_uart_platform_driver);
  667. uart_unregister_driver(&mpc52xx_uart_driver);
  668. }
  669. module_init(mpc52xx_uart_init);
  670. module_exit(mpc52xx_uart_exit);
  671. MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
  672. MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
  673. MODULE_LICENSE("GPL");