solos-pci.c 39 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #include <linux/slab.h>
  42. #define VERSION "1.04"
  43. #define DRIVER_VERSION 0x01
  44. #define PTAG "solos-pci"
  45. #define CONFIG_RAM_SIZE 128
  46. #define FLAGS_ADDR 0x7C
  47. #define IRQ_EN_ADDR 0x78
  48. #define FPGA_VER 0x74
  49. #define IRQ_CLEAR 0x70
  50. #define WRITE_FLASH 0x6C
  51. #define PORTS 0x68
  52. #define FLASH_BLOCK 0x64
  53. #define FLASH_BUSY 0x60
  54. #define FPGA_MODE 0x5C
  55. #define FLASH_MODE 0x58
  56. #define GPIO_STATUS 0x54
  57. #define DRIVER_VER 0x50
  58. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  59. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  60. #define DATA_RAM_SIZE 32768
  61. #define BUF_SIZE 2048
  62. #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
  63. /* Old boards use ATMEL AD45DB161D flash */
  64. #define ATMEL_FPGA_PAGE 528 /* FPGA flash page size*/
  65. #define ATMEL_SOLOS_PAGE 512 /* Solos flash page size*/
  66. #define ATMEL_FPGA_BLOCK (ATMEL_FPGA_PAGE * 8) /* FPGA block size*/
  67. #define ATMEL_SOLOS_BLOCK (ATMEL_SOLOS_PAGE * 8) /* Solos block size*/
  68. /* Current boards use M25P/M25PE SPI flash */
  69. #define SPI_FLASH_BLOCK (256 * 64)
  70. #define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
  71. #define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
  72. #define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
  73. #define RX_DMA_SIZE 2048
  74. #define FPGA_VERSION(a,b) (((a) << 8) + (b))
  75. #define LEGACY_BUFFERS 2
  76. #define DMA_SUPPORTED 4
  77. static int reset = 0;
  78. static int atmdebug = 0;
  79. static int firmware_upgrade = 0;
  80. static int fpga_upgrade = 0;
  81. static int db_firmware_upgrade = 0;
  82. static int db_fpga_upgrade = 0;
  83. struct pkt_hdr {
  84. __le16 size;
  85. __le16 vpi;
  86. __le16 vci;
  87. __le16 type;
  88. };
  89. struct solos_skb_cb {
  90. struct atm_vcc *vcc;
  91. uint32_t dma_addr;
  92. };
  93. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  94. #define PKT_DATA 0
  95. #define PKT_COMMAND 1
  96. #define PKT_POPEN 3
  97. #define PKT_PCLOSE 4
  98. #define PKT_STATUS 5
  99. struct solos_card {
  100. void __iomem *config_regs;
  101. void __iomem *buffers;
  102. int nr_ports;
  103. int tx_mask;
  104. struct pci_dev *dev;
  105. struct atm_dev *atmdev[4];
  106. struct tasklet_struct tlet;
  107. spinlock_t tx_lock;
  108. spinlock_t tx_queue_lock;
  109. spinlock_t cli_queue_lock;
  110. spinlock_t param_queue_lock;
  111. struct list_head param_queue;
  112. struct sk_buff_head tx_queue[4];
  113. struct sk_buff_head cli_queue[4];
  114. struct sk_buff *tx_skb[4];
  115. struct sk_buff *rx_skb[4];
  116. unsigned char *dma_bounce;
  117. wait_queue_head_t param_wq;
  118. wait_queue_head_t fw_wq;
  119. int using_dma;
  120. int dma_alignment;
  121. int fpga_version;
  122. int buffer_size;
  123. int atmel_flash;
  124. };
  125. struct solos_param {
  126. struct list_head list;
  127. pid_t pid;
  128. int port;
  129. struct sk_buff *response;
  130. };
  131. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  132. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  133. MODULE_DESCRIPTION("Solos PCI driver");
  134. MODULE_VERSION(VERSION);
  135. MODULE_LICENSE("GPL");
  136. MODULE_FIRMWARE("solos-FPGA.bin");
  137. MODULE_FIRMWARE("solos-Firmware.bin");
  138. MODULE_FIRMWARE("solos-db-FPGA.bin");
  139. MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
  140. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  141. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  142. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  143. MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
  144. MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
  145. module_param(reset, int, 0444);
  146. module_param(atmdebug, int, 0644);
  147. module_param(firmware_upgrade, int, 0444);
  148. module_param(fpga_upgrade, int, 0444);
  149. module_param(db_firmware_upgrade, int, 0444);
  150. module_param(db_fpga_upgrade, int, 0444);
  151. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  152. struct atm_vcc *vcc);
  153. static uint32_t fpga_tx(struct solos_card *);
  154. static irqreturn_t solos_irq(int irq, void *dev_id);
  155. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  156. static int atm_init(struct solos_card *, struct device *);
  157. static void atm_remove(struct solos_card *);
  158. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  159. static void solos_bh(unsigned long);
  160. static int print_buffer(struct sk_buff *buf);
  161. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  162. {
  163. if (vcc->pop)
  164. vcc->pop(vcc, skb);
  165. else
  166. dev_kfree_skb_any(skb);
  167. }
  168. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  169. char *buf)
  170. {
  171. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  172. struct solos_card *card = atmdev->dev_data;
  173. struct solos_param prm;
  174. struct sk_buff *skb;
  175. struct pkt_hdr *header;
  176. int buflen;
  177. buflen = strlen(attr->attr.name) + 10;
  178. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  179. if (!skb) {
  180. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  181. return -ENOMEM;
  182. }
  183. header = (void *)skb_put(skb, sizeof(*header));
  184. buflen = snprintf((void *)&header[1], buflen - 1,
  185. "L%05d\n%s\n", current->pid, attr->attr.name);
  186. skb_put(skb, buflen);
  187. header->size = cpu_to_le16(buflen);
  188. header->vpi = cpu_to_le16(0);
  189. header->vci = cpu_to_le16(0);
  190. header->type = cpu_to_le16(PKT_COMMAND);
  191. prm.pid = current->pid;
  192. prm.response = NULL;
  193. prm.port = SOLOS_CHAN(atmdev);
  194. spin_lock_irq(&card->param_queue_lock);
  195. list_add(&prm.list, &card->param_queue);
  196. spin_unlock_irq(&card->param_queue_lock);
  197. fpga_queue(card, prm.port, skb, NULL);
  198. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  199. spin_lock_irq(&card->param_queue_lock);
  200. list_del(&prm.list);
  201. spin_unlock_irq(&card->param_queue_lock);
  202. if (!prm.response)
  203. return -EIO;
  204. buflen = prm.response->len;
  205. memcpy(buf, prm.response->data, buflen);
  206. kfree_skb(prm.response);
  207. return buflen;
  208. }
  209. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  210. const char *buf, size_t count)
  211. {
  212. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  213. struct solos_card *card = atmdev->dev_data;
  214. struct solos_param prm;
  215. struct sk_buff *skb;
  216. struct pkt_hdr *header;
  217. int buflen;
  218. ssize_t ret;
  219. buflen = strlen(attr->attr.name) + 11 + count;
  220. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  221. if (!skb) {
  222. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  223. return -ENOMEM;
  224. }
  225. header = (void *)skb_put(skb, sizeof(*header));
  226. buflen = snprintf((void *)&header[1], buflen - 1,
  227. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  228. skb_put(skb, buflen);
  229. header->size = cpu_to_le16(buflen);
  230. header->vpi = cpu_to_le16(0);
  231. header->vci = cpu_to_le16(0);
  232. header->type = cpu_to_le16(PKT_COMMAND);
  233. prm.pid = current->pid;
  234. prm.response = NULL;
  235. prm.port = SOLOS_CHAN(atmdev);
  236. spin_lock_irq(&card->param_queue_lock);
  237. list_add(&prm.list, &card->param_queue);
  238. spin_unlock_irq(&card->param_queue_lock);
  239. fpga_queue(card, prm.port, skb, NULL);
  240. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  241. spin_lock_irq(&card->param_queue_lock);
  242. list_del(&prm.list);
  243. spin_unlock_irq(&card->param_queue_lock);
  244. skb = prm.response;
  245. if (!skb)
  246. return -EIO;
  247. buflen = skb->len;
  248. /* Sometimes it has a newline, sometimes it doesn't. */
  249. if (skb->data[buflen - 1] == '\n')
  250. buflen--;
  251. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  252. ret = count;
  253. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  254. ret = -EIO;
  255. else {
  256. /* We know we have enough space allocated for this; we allocated
  257. it ourselves */
  258. skb->data[buflen] = 0;
  259. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  260. skb->data);
  261. ret = -EIO;
  262. }
  263. kfree_skb(skb);
  264. return ret;
  265. }
  266. static char *next_string(struct sk_buff *skb)
  267. {
  268. int i = 0;
  269. char *this = skb->data;
  270. for (i = 0; i < skb->len; i++) {
  271. if (this[i] == '\n') {
  272. this[i] = 0;
  273. skb_pull(skb, i + 1);
  274. return this;
  275. }
  276. if (!isprint(this[i]))
  277. return NULL;
  278. }
  279. return NULL;
  280. }
  281. /*
  282. * Status packet has fields separated by \n, starting with a version number
  283. * for the information therein. Fields are....
  284. *
  285. * packet version
  286. * RxBitRate (version >= 1)
  287. * TxBitRate (version >= 1)
  288. * State (version >= 1)
  289. * LocalSNRMargin (version >= 1)
  290. * LocalLineAttn (version >= 1)
  291. */
  292. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  293. {
  294. char *str, *end, *state_str, *snr, *attn;
  295. int ver, rate_up, rate_down;
  296. if (!card->atmdev[port])
  297. return -ENODEV;
  298. str = next_string(skb);
  299. if (!str)
  300. return -EIO;
  301. ver = simple_strtol(str, NULL, 10);
  302. if (ver < 1) {
  303. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  304. ver);
  305. return -EIO;
  306. }
  307. str = next_string(skb);
  308. if (!str)
  309. return -EIO;
  310. if (!strcmp(str, "ERROR")) {
  311. dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
  312. port);
  313. return 0;
  314. }
  315. rate_down = simple_strtol(str, &end, 10);
  316. if (*end)
  317. return -EIO;
  318. str = next_string(skb);
  319. if (!str)
  320. return -EIO;
  321. rate_up = simple_strtol(str, &end, 10);
  322. if (*end)
  323. return -EIO;
  324. state_str = next_string(skb);
  325. if (!state_str)
  326. return -EIO;
  327. /* Anything but 'Showtime' is down */
  328. if (strcmp(state_str, "Showtime")) {
  329. atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_LOST);
  330. dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
  331. return 0;
  332. }
  333. snr = next_string(skb);
  334. if (!snr)
  335. return -EIO;
  336. attn = next_string(skb);
  337. if (!attn)
  338. return -EIO;
  339. dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
  340. port, state_str, rate_down/1000, rate_up/1000,
  341. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  342. card->atmdev[port]->link_rate = rate_down / 424;
  343. atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_FOUND);
  344. return 0;
  345. }
  346. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  347. {
  348. struct solos_param *prm;
  349. unsigned long flags;
  350. int cmdpid;
  351. int found = 0;
  352. if (skb->len < 7)
  353. return 0;
  354. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  355. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  356. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  357. skb->data[6] != '\n')
  358. return 0;
  359. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  360. spin_lock_irqsave(&card->param_queue_lock, flags);
  361. list_for_each_entry(prm, &card->param_queue, list) {
  362. if (prm->port == port && prm->pid == cmdpid) {
  363. prm->response = skb;
  364. skb_pull(skb, 7);
  365. wake_up(&card->param_wq);
  366. found = 1;
  367. break;
  368. }
  369. }
  370. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  371. return found;
  372. }
  373. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  374. char *buf)
  375. {
  376. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  377. struct solos_card *card = atmdev->dev_data;
  378. struct sk_buff *skb;
  379. unsigned int len;
  380. spin_lock(&card->cli_queue_lock);
  381. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  382. spin_unlock(&card->cli_queue_lock);
  383. if(skb == NULL)
  384. return sprintf(buf, "No data.\n");
  385. len = skb->len;
  386. memcpy(buf, skb->data, len);
  387. kfree_skb(skb);
  388. return len;
  389. }
  390. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  391. {
  392. struct sk_buff *skb;
  393. struct pkt_hdr *header;
  394. if (size > (BUF_SIZE - sizeof(*header))) {
  395. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  396. return 0;
  397. }
  398. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  399. if (!skb) {
  400. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  401. return 0;
  402. }
  403. header = (void *)skb_put(skb, sizeof(*header));
  404. header->size = cpu_to_le16(size);
  405. header->vpi = cpu_to_le16(0);
  406. header->vci = cpu_to_le16(0);
  407. header->type = cpu_to_le16(PKT_COMMAND);
  408. memcpy(skb_put(skb, size), buf, size);
  409. fpga_queue(card, dev, skb, NULL);
  410. return 0;
  411. }
  412. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  413. const char *buf, size_t count)
  414. {
  415. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  416. struct solos_card *card = atmdev->dev_data;
  417. int err;
  418. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  419. return err?:count;
  420. }
  421. struct geos_gpio_attr {
  422. struct device_attribute attr;
  423. int offset;
  424. };
  425. #define SOLOS_GPIO_ATTR(_name, _mode, _show, _store, _offset) \
  426. struct geos_gpio_attr gpio_attr_##_name = { \
  427. .attr = __ATTR(_name, _mode, _show, _store), \
  428. .offset = _offset }
  429. static ssize_t geos_gpio_store(struct device *dev, struct device_attribute *attr,
  430. const char *buf, size_t count)
  431. {
  432. struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
  433. struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
  434. struct solos_card *card = pci_get_drvdata(pdev);
  435. uint32_t data32;
  436. if (count != 1 && (count != 2 || buf[1] != '\n'))
  437. return -EINVAL;
  438. spin_lock_irq(&card->param_queue_lock);
  439. data32 = ioread32(card->config_regs + GPIO_STATUS);
  440. if (buf[0] == '1') {
  441. data32 |= 1 << gattr->offset;
  442. iowrite32(data32, card->config_regs + GPIO_STATUS);
  443. } else if (buf[0] == '0') {
  444. data32 &= ~(1 << gattr->offset);
  445. iowrite32(data32, card->config_regs + GPIO_STATUS);
  446. } else {
  447. count = -EINVAL;
  448. }
  449. spin_unlock_irq(&card->param_queue_lock);
  450. return count;
  451. }
  452. static ssize_t geos_gpio_show(struct device *dev, struct device_attribute *attr,
  453. char *buf)
  454. {
  455. struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
  456. struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
  457. struct solos_card *card = pci_get_drvdata(pdev);
  458. uint32_t data32;
  459. data32 = ioread32(card->config_regs + GPIO_STATUS);
  460. data32 = (data32 >> gattr->offset) & 1;
  461. return sprintf(buf, "%d\n", data32);
  462. }
  463. static ssize_t hardware_show(struct device *dev, struct device_attribute *attr,
  464. char *buf)
  465. {
  466. struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
  467. struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
  468. struct solos_card *card = pci_get_drvdata(pdev);
  469. uint32_t data32;
  470. data32 = ioread32(card->config_regs + GPIO_STATUS);
  471. switch (gattr->offset) {
  472. case 0:
  473. /* HardwareVersion */
  474. data32 = data32 & 0x1F;
  475. break;
  476. case 1:
  477. /* HardwareVariant */
  478. data32 = (data32 >> 5) & 0x0F;
  479. break;
  480. }
  481. return sprintf(buf, "%d\n", data32);
  482. }
  483. static DEVICE_ATTR(console, 0644, console_show, console_store);
  484. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  485. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  486. #include "solos-attrlist.c"
  487. static SOLOS_GPIO_ATTR(GPIO1, 0644, geos_gpio_show, geos_gpio_store, 9);
  488. static SOLOS_GPIO_ATTR(GPIO2, 0644, geos_gpio_show, geos_gpio_store, 10);
  489. static SOLOS_GPIO_ATTR(GPIO3, 0644, geos_gpio_show, geos_gpio_store, 11);
  490. static SOLOS_GPIO_ATTR(GPIO4, 0644, geos_gpio_show, geos_gpio_store, 12);
  491. static SOLOS_GPIO_ATTR(GPIO5, 0644, geos_gpio_show, geos_gpio_store, 13);
  492. static SOLOS_GPIO_ATTR(PushButton, 0444, geos_gpio_show, NULL, 14);
  493. static SOLOS_GPIO_ATTR(HardwareVersion, 0444, hardware_show, NULL, 0);
  494. static SOLOS_GPIO_ATTR(HardwareVariant, 0444, hardware_show, NULL, 1);
  495. #undef SOLOS_ATTR_RO
  496. #undef SOLOS_ATTR_RW
  497. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  498. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  499. static struct attribute *solos_attrs[] = {
  500. #include "solos-attrlist.c"
  501. NULL
  502. };
  503. static struct attribute_group solos_attr_group = {
  504. .attrs = solos_attrs,
  505. .name = "parameters",
  506. };
  507. static struct attribute *gpio_attrs[] = {
  508. &gpio_attr_GPIO1.attr.attr,
  509. &gpio_attr_GPIO2.attr.attr,
  510. &gpio_attr_GPIO3.attr.attr,
  511. &gpio_attr_GPIO4.attr.attr,
  512. &gpio_attr_GPIO5.attr.attr,
  513. &gpio_attr_PushButton.attr.attr,
  514. &gpio_attr_HardwareVersion.attr.attr,
  515. &gpio_attr_HardwareVariant.attr.attr,
  516. NULL
  517. };
  518. static struct attribute_group gpio_attr_group = {
  519. .attrs = gpio_attrs,
  520. .name = "gpio",
  521. };
  522. static int flash_upgrade(struct solos_card *card, int chip)
  523. {
  524. const struct firmware *fw;
  525. const char *fw_name;
  526. int blocksize = 0;
  527. int numblocks = 0;
  528. int offset;
  529. switch (chip) {
  530. case 0:
  531. fw_name = "solos-FPGA.bin";
  532. if (card->atmel_flash)
  533. blocksize = ATMEL_FPGA_BLOCK;
  534. else
  535. blocksize = SPI_FLASH_BLOCK;
  536. break;
  537. case 1:
  538. fw_name = "solos-Firmware.bin";
  539. if (card->atmel_flash)
  540. blocksize = ATMEL_SOLOS_BLOCK;
  541. else
  542. blocksize = SPI_FLASH_BLOCK;
  543. break;
  544. case 2:
  545. if (card->fpga_version > LEGACY_BUFFERS){
  546. fw_name = "solos-db-FPGA.bin";
  547. if (card->atmel_flash)
  548. blocksize = ATMEL_FPGA_BLOCK;
  549. else
  550. blocksize = SPI_FLASH_BLOCK;
  551. } else {
  552. dev_info(&card->dev->dev, "FPGA version doesn't support"
  553. " daughter board upgrades\n");
  554. return -EPERM;
  555. }
  556. break;
  557. case 3:
  558. if (card->fpga_version > LEGACY_BUFFERS){
  559. fw_name = "solos-Firmware.bin";
  560. if (card->atmel_flash)
  561. blocksize = ATMEL_SOLOS_BLOCK;
  562. else
  563. blocksize = SPI_FLASH_BLOCK;
  564. } else {
  565. dev_info(&card->dev->dev, "FPGA version doesn't support"
  566. " daughter board upgrades\n");
  567. return -EPERM;
  568. }
  569. break;
  570. default:
  571. return -ENODEV;
  572. }
  573. if (request_firmware(&fw, fw_name, &card->dev->dev))
  574. return -ENOENT;
  575. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  576. /* New FPGAs require driver version before permitting flash upgrades */
  577. iowrite32(DRIVER_VERSION, card->config_regs + DRIVER_VER);
  578. numblocks = fw->size / blocksize;
  579. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  580. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  581. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  582. iowrite32(1, card->config_regs + FPGA_MODE);
  583. (void) ioread32(card->config_regs + FPGA_MODE);
  584. /* Set mode to Chip Erase */
  585. if(chip == 0 || chip == 2)
  586. dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
  587. if(chip == 1 || chip == 3)
  588. dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
  589. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  590. iowrite32(1, card->config_regs + WRITE_FLASH);
  591. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  592. for (offset = 0; offset < fw->size; offset += blocksize) {
  593. int i;
  594. /* Clear write flag */
  595. iowrite32(0, card->config_regs + WRITE_FLASH);
  596. /* Set mode to Block Write */
  597. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  598. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  599. /* Copy block to buffer, swapping each 16 bits for Atmel flash */
  600. for(i = 0; i < blocksize; i += 4) {
  601. uint32_t word;
  602. if (card->atmel_flash)
  603. word = swahb32p((uint32_t *)(fw->data + offset + i));
  604. else
  605. word = *(uint32_t *)(fw->data + offset + i);
  606. if(card->fpga_version > LEGACY_BUFFERS)
  607. iowrite32(word, FLASH_BUF + i);
  608. else
  609. iowrite32(word, RX_BUF(card, 3) + i);
  610. }
  611. /* Specify block number and then trigger flash write */
  612. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  613. iowrite32(1, card->config_regs + WRITE_FLASH);
  614. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  615. }
  616. release_firmware(fw);
  617. iowrite32(0, card->config_regs + WRITE_FLASH);
  618. iowrite32(0, card->config_regs + FPGA_MODE);
  619. iowrite32(0, card->config_regs + FLASH_MODE);
  620. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  621. return 0;
  622. }
  623. static irqreturn_t solos_irq(int irq, void *dev_id)
  624. {
  625. struct solos_card *card = dev_id;
  626. int handled = 1;
  627. iowrite32(0, card->config_regs + IRQ_CLEAR);
  628. /* If we're up and running, just kick the tasklet to process TX/RX */
  629. if (card->atmdev[0])
  630. tasklet_schedule(&card->tlet);
  631. else
  632. wake_up(&card->fw_wq);
  633. return IRQ_RETVAL(handled);
  634. }
  635. void solos_bh(unsigned long card_arg)
  636. {
  637. struct solos_card *card = (void *)card_arg;
  638. uint32_t card_flags;
  639. uint32_t rx_done = 0;
  640. int port;
  641. /*
  642. * Since fpga_tx() is going to need to read the flags under its lock,
  643. * it can return them to us so that we don't have to hit PCI MMIO
  644. * again for the same information
  645. */
  646. card_flags = fpga_tx(card);
  647. for (port = 0; port < card->nr_ports; port++) {
  648. if (card_flags & (0x10 << port)) {
  649. struct pkt_hdr _hdr, *header;
  650. struct sk_buff *skb;
  651. struct atm_vcc *vcc;
  652. int size;
  653. if (card->using_dma) {
  654. skb = card->rx_skb[port];
  655. card->rx_skb[port] = NULL;
  656. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  657. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  658. header = (void *)skb->data;
  659. size = le16_to_cpu(header->size);
  660. skb_put(skb, size + sizeof(*header));
  661. skb_pull(skb, sizeof(*header));
  662. } else {
  663. header = &_hdr;
  664. rx_done |= 0x10 << port;
  665. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  666. size = le16_to_cpu(header->size);
  667. if (size > (card->buffer_size - sizeof(*header))){
  668. dev_warn(&card->dev->dev, "Invalid buffer size\n");
  669. continue;
  670. }
  671. skb = alloc_skb(size + 1, GFP_ATOMIC);
  672. if (!skb) {
  673. if (net_ratelimit())
  674. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  675. continue;
  676. }
  677. memcpy_fromio(skb_put(skb, size),
  678. RX_BUF(card, port) + sizeof(*header),
  679. size);
  680. }
  681. if (atmdebug) {
  682. dev_info(&card->dev->dev, "Received: port %d\n", port);
  683. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  684. size, le16_to_cpu(header->vpi),
  685. le16_to_cpu(header->vci));
  686. print_buffer(skb);
  687. }
  688. switch (le16_to_cpu(header->type)) {
  689. case PKT_DATA:
  690. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  691. le16_to_cpu(header->vci));
  692. if (!vcc) {
  693. if (net_ratelimit())
  694. dev_warn(&card->dev->dev, "Received packet for unknown VPI.VCI %d.%d on port %d\n",
  695. le16_to_cpu(header->vpi), le16_to_cpu(header->vci),
  696. port);
  697. dev_kfree_skb_any(skb);
  698. break;
  699. }
  700. atm_charge(vcc, skb->truesize);
  701. vcc->push(vcc, skb);
  702. atomic_inc(&vcc->stats->rx);
  703. break;
  704. case PKT_STATUS:
  705. if (process_status(card, port, skb) &&
  706. net_ratelimit()) {
  707. dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
  708. print_buffer(skb);
  709. }
  710. dev_kfree_skb_any(skb);
  711. break;
  712. case PKT_COMMAND:
  713. default: /* FIXME: Not really, surely? */
  714. if (process_command(card, port, skb))
  715. break;
  716. spin_lock(&card->cli_queue_lock);
  717. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  718. if (net_ratelimit())
  719. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  720. port);
  721. dev_kfree_skb_any(skb);
  722. } else
  723. skb_queue_tail(&card->cli_queue[port], skb);
  724. spin_unlock(&card->cli_queue_lock);
  725. break;
  726. }
  727. }
  728. /* Allocate RX skbs for any ports which need them */
  729. if (card->using_dma && card->atmdev[port] &&
  730. !card->rx_skb[port]) {
  731. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  732. if (skb) {
  733. SKB_CB(skb)->dma_addr =
  734. pci_map_single(card->dev, skb->data,
  735. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  736. iowrite32(SKB_CB(skb)->dma_addr,
  737. card->config_regs + RX_DMA_ADDR(port));
  738. card->rx_skb[port] = skb;
  739. } else {
  740. if (net_ratelimit())
  741. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  742. /* We'll have to try again later */
  743. tasklet_schedule(&card->tlet);
  744. }
  745. }
  746. }
  747. if (rx_done)
  748. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  749. return;
  750. }
  751. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  752. {
  753. struct hlist_head *head;
  754. struct atm_vcc *vcc = NULL;
  755. struct sock *s;
  756. read_lock(&vcc_sklist_lock);
  757. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  758. sk_for_each(s, head) {
  759. vcc = atm_sk(s);
  760. if (vcc->dev == dev && vcc->vci == vci &&
  761. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE &&
  762. test_bit(ATM_VF_READY, &vcc->flags))
  763. goto out;
  764. }
  765. vcc = NULL;
  766. out:
  767. read_unlock(&vcc_sklist_lock);
  768. return vcc;
  769. }
  770. static int popen(struct atm_vcc *vcc)
  771. {
  772. struct solos_card *card = vcc->dev->dev_data;
  773. struct sk_buff *skb;
  774. struct pkt_hdr *header;
  775. if (vcc->qos.aal != ATM_AAL5) {
  776. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  777. vcc->qos.aal);
  778. return -EINVAL;
  779. }
  780. skb = alloc_skb(sizeof(*header), GFP_KERNEL);
  781. if (!skb) {
  782. if (net_ratelimit())
  783. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  784. return -ENOMEM;
  785. }
  786. header = (void *)skb_put(skb, sizeof(*header));
  787. header->size = cpu_to_le16(0);
  788. header->vpi = cpu_to_le16(vcc->vpi);
  789. header->vci = cpu_to_le16(vcc->vci);
  790. header->type = cpu_to_le16(PKT_POPEN);
  791. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  792. set_bit(ATM_VF_ADDR, &vcc->flags);
  793. set_bit(ATM_VF_READY, &vcc->flags);
  794. return 0;
  795. }
  796. static void pclose(struct atm_vcc *vcc)
  797. {
  798. struct solos_card *card = vcc->dev->dev_data;
  799. unsigned char port = SOLOS_CHAN(vcc->dev);
  800. struct sk_buff *skb, *tmpskb;
  801. struct pkt_hdr *header;
  802. /* Remove any yet-to-be-transmitted packets from the pending queue */
  803. spin_lock(&card->tx_queue_lock);
  804. skb_queue_walk_safe(&card->tx_queue[port], skb, tmpskb) {
  805. if (SKB_CB(skb)->vcc == vcc) {
  806. skb_unlink(skb, &card->tx_queue[port]);
  807. solos_pop(vcc, skb);
  808. }
  809. }
  810. spin_unlock(&card->tx_queue_lock);
  811. skb = alloc_skb(sizeof(*header), GFP_KERNEL);
  812. if (!skb) {
  813. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  814. return;
  815. }
  816. header = (void *)skb_put(skb, sizeof(*header));
  817. header->size = cpu_to_le16(0);
  818. header->vpi = cpu_to_le16(vcc->vpi);
  819. header->vci = cpu_to_le16(vcc->vci);
  820. header->type = cpu_to_le16(PKT_PCLOSE);
  821. skb_get(skb);
  822. fpga_queue(card, port, skb, NULL);
  823. if (!wait_event_timeout(card->param_wq, !skb_shared(skb), 5 * HZ))
  824. dev_warn(&card->dev->dev,
  825. "Timeout waiting for VCC close on port %d\n", port);
  826. dev_kfree_skb(skb);
  827. /* Hold up vcc_destroy_socket() (our caller) until solos_bh() in the
  828. tasklet has finished processing any incoming packets (and, more to
  829. the point, using the vcc pointer). */
  830. tasklet_unlock_wait(&card->tlet);
  831. clear_bit(ATM_VF_ADDR, &vcc->flags);
  832. return;
  833. }
  834. static int print_buffer(struct sk_buff *buf)
  835. {
  836. int len,i;
  837. char msg[500];
  838. char item[10];
  839. len = buf->len;
  840. for (i = 0; i < len; i++){
  841. if(i % 8 == 0)
  842. sprintf(msg, "%02X: ", i);
  843. sprintf(item,"%02X ",*(buf->data + i));
  844. strcat(msg, item);
  845. if(i % 8 == 7) {
  846. sprintf(item, "\n");
  847. strcat(msg, item);
  848. printk(KERN_DEBUG "%s", msg);
  849. }
  850. }
  851. if (i % 8 != 0) {
  852. sprintf(item, "\n");
  853. strcat(msg, item);
  854. printk(KERN_DEBUG "%s", msg);
  855. }
  856. printk(KERN_DEBUG "\n");
  857. return 0;
  858. }
  859. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  860. struct atm_vcc *vcc)
  861. {
  862. int old_len;
  863. unsigned long flags;
  864. SKB_CB(skb)->vcc = vcc;
  865. spin_lock_irqsave(&card->tx_queue_lock, flags);
  866. old_len = skb_queue_len(&card->tx_queue[port]);
  867. skb_queue_tail(&card->tx_queue[port], skb);
  868. if (!old_len)
  869. card->tx_mask |= (1 << port);
  870. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  871. /* Theoretically we could just schedule the tasklet here, but
  872. that introduces latency we don't want -- it's noticeable */
  873. if (!old_len)
  874. fpga_tx(card);
  875. }
  876. static uint32_t fpga_tx(struct solos_card *card)
  877. {
  878. uint32_t tx_pending, card_flags;
  879. uint32_t tx_started = 0;
  880. struct sk_buff *skb;
  881. struct atm_vcc *vcc;
  882. unsigned char port;
  883. unsigned long flags;
  884. spin_lock_irqsave(&card->tx_lock, flags);
  885. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  886. /*
  887. * The queue lock is required for _writing_ to tx_mask, but we're
  888. * OK to read it here without locking. The only potential update
  889. * that we could race with is in fpga_queue() where it sets a bit
  890. * for a new port... but it's going to call this function again if
  891. * it's doing that, anyway.
  892. */
  893. tx_pending = card->tx_mask & ~card_flags;
  894. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  895. if (tx_pending & 1) {
  896. struct sk_buff *oldskb = card->tx_skb[port];
  897. if (oldskb) {
  898. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  899. oldskb->len, PCI_DMA_TODEVICE);
  900. card->tx_skb[port] = NULL;
  901. }
  902. spin_lock(&card->tx_queue_lock);
  903. skb = skb_dequeue(&card->tx_queue[port]);
  904. if (!skb)
  905. card->tx_mask &= ~(1 << port);
  906. spin_unlock(&card->tx_queue_lock);
  907. if (skb && !card->using_dma) {
  908. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  909. tx_started |= 1 << port;
  910. oldskb = skb; /* We're done with this skb already */
  911. } else if (skb && card->using_dma) {
  912. unsigned char *data = skb->data;
  913. if ((unsigned long)data & card->dma_alignment) {
  914. data = card->dma_bounce + (BUF_SIZE * port);
  915. memcpy(data, skb->data, skb->len);
  916. }
  917. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, data,
  918. skb->len, PCI_DMA_TODEVICE);
  919. card->tx_skb[port] = skb;
  920. iowrite32(SKB_CB(skb)->dma_addr,
  921. card->config_regs + TX_DMA_ADDR(port));
  922. }
  923. if (!oldskb)
  924. continue;
  925. /* Clean up and free oldskb now it's gone */
  926. if (atmdebug) {
  927. struct pkt_hdr *header = (void *)oldskb->data;
  928. int size = le16_to_cpu(header->size);
  929. skb_pull(oldskb, sizeof(*header));
  930. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  931. port);
  932. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  933. size, le16_to_cpu(header->vpi),
  934. le16_to_cpu(header->vci));
  935. print_buffer(oldskb);
  936. }
  937. vcc = SKB_CB(oldskb)->vcc;
  938. if (vcc) {
  939. atomic_inc(&vcc->stats->tx);
  940. solos_pop(vcc, oldskb);
  941. } else {
  942. dev_kfree_skb_irq(oldskb);
  943. wake_up(&card->param_wq);
  944. }
  945. }
  946. }
  947. /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
  948. if (tx_started)
  949. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  950. spin_unlock_irqrestore(&card->tx_lock, flags);
  951. return card_flags;
  952. }
  953. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  954. {
  955. struct solos_card *card = vcc->dev->dev_data;
  956. struct pkt_hdr *header;
  957. int pktlen;
  958. pktlen = skb->len;
  959. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  960. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  961. solos_pop(vcc, skb);
  962. return 0;
  963. }
  964. if (!skb_clone_writable(skb, sizeof(*header))) {
  965. int expand_by = 0;
  966. int ret;
  967. if (skb_headroom(skb) < sizeof(*header))
  968. expand_by = sizeof(*header) - skb_headroom(skb);
  969. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  970. if (ret) {
  971. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  972. solos_pop(vcc, skb);
  973. return ret;
  974. }
  975. }
  976. header = (void *)skb_push(skb, sizeof(*header));
  977. /* This does _not_ include the size of the header */
  978. header->size = cpu_to_le16(pktlen);
  979. header->vpi = cpu_to_le16(vcc->vpi);
  980. header->vci = cpu_to_le16(vcc->vci);
  981. header->type = cpu_to_le16(PKT_DATA);
  982. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  983. return 0;
  984. }
  985. static struct atmdev_ops fpga_ops = {
  986. .open = popen,
  987. .close = pclose,
  988. .ioctl = NULL,
  989. .getsockopt = NULL,
  990. .setsockopt = NULL,
  991. .send = psend,
  992. .send_oam = NULL,
  993. .phy_put = NULL,
  994. .phy_get = NULL,
  995. .change_qos = NULL,
  996. .proc_read = NULL,
  997. .owner = THIS_MODULE
  998. };
  999. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  1000. {
  1001. int err;
  1002. uint16_t fpga_ver;
  1003. uint8_t major_ver, minor_ver;
  1004. uint32_t data32;
  1005. struct solos_card *card;
  1006. card = kzalloc(sizeof(*card), GFP_KERNEL);
  1007. if (!card)
  1008. return -ENOMEM;
  1009. card->dev = dev;
  1010. init_waitqueue_head(&card->fw_wq);
  1011. init_waitqueue_head(&card->param_wq);
  1012. err = pci_enable_device(dev);
  1013. if (err) {
  1014. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  1015. goto out;
  1016. }
  1017. err = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
  1018. if (err) {
  1019. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  1020. goto out;
  1021. }
  1022. err = pci_request_regions(dev, "solos");
  1023. if (err) {
  1024. dev_warn(&dev->dev, "Failed to request regions\n");
  1025. goto out;
  1026. }
  1027. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  1028. if (!card->config_regs) {
  1029. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  1030. goto out_release_regions;
  1031. }
  1032. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  1033. if (!card->buffers) {
  1034. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  1035. goto out_unmap_config;
  1036. }
  1037. if (reset) {
  1038. iowrite32(1, card->config_regs + FPGA_MODE);
  1039. data32 = ioread32(card->config_regs + FPGA_MODE);
  1040. iowrite32(0, card->config_regs + FPGA_MODE);
  1041. data32 = ioread32(card->config_regs + FPGA_MODE);
  1042. }
  1043. data32 = ioread32(card->config_regs + FPGA_VER);
  1044. fpga_ver = (data32 & 0x0000FFFF);
  1045. major_ver = ((data32 & 0xFF000000) >> 24);
  1046. minor_ver = ((data32 & 0x00FF0000) >> 16);
  1047. card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
  1048. if (card->fpga_version > LEGACY_BUFFERS)
  1049. card->buffer_size = BUF_SIZE;
  1050. else
  1051. card->buffer_size = OLD_BUF_SIZE;
  1052. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  1053. major_ver, minor_ver, fpga_ver);
  1054. if (fpga_ver < 37 && (fpga_upgrade || firmware_upgrade ||
  1055. db_fpga_upgrade || db_firmware_upgrade)) {
  1056. dev_warn(&dev->dev,
  1057. "FPGA too old; cannot upgrade flash. Use JTAG.\n");
  1058. fpga_upgrade = firmware_upgrade = 0;
  1059. db_fpga_upgrade = db_firmware_upgrade = 0;
  1060. }
  1061. /* Stopped using Atmel flash after 0.03-38 */
  1062. if (fpga_ver < 39)
  1063. card->atmel_flash = 1;
  1064. else
  1065. card->atmel_flash = 0;
  1066. data32 = ioread32(card->config_regs + PORTS);
  1067. card->nr_ports = (data32 & 0x000000FF);
  1068. if (card->fpga_version >= DMA_SUPPORTED) {
  1069. pci_set_master(dev);
  1070. card->using_dma = 1;
  1071. if (1) { /* All known FPGA versions so far */
  1072. card->dma_alignment = 3;
  1073. card->dma_bounce = kmalloc(card->nr_ports * BUF_SIZE, GFP_KERNEL);
  1074. if (!card->dma_bounce) {
  1075. dev_warn(&card->dev->dev, "Failed to allocate DMA bounce buffers\n");
  1076. /* Fallback to MMIO doesn't work */
  1077. goto out_unmap_both;
  1078. }
  1079. }
  1080. } else {
  1081. card->using_dma = 0;
  1082. /* Set RX empty flag for all ports */
  1083. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  1084. }
  1085. pci_set_drvdata(dev, card);
  1086. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  1087. spin_lock_init(&card->tx_lock);
  1088. spin_lock_init(&card->tx_queue_lock);
  1089. spin_lock_init(&card->cli_queue_lock);
  1090. spin_lock_init(&card->param_queue_lock);
  1091. INIT_LIST_HEAD(&card->param_queue);
  1092. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  1093. "solos-pci", card);
  1094. if (err) {
  1095. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  1096. goto out_unmap_both;
  1097. }
  1098. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  1099. if (fpga_upgrade)
  1100. flash_upgrade(card, 0);
  1101. if (firmware_upgrade)
  1102. flash_upgrade(card, 1);
  1103. if (db_fpga_upgrade)
  1104. flash_upgrade(card, 2);
  1105. if (db_firmware_upgrade)
  1106. flash_upgrade(card, 3);
  1107. err = atm_init(card, &dev->dev);
  1108. if (err)
  1109. goto out_free_irq;
  1110. if (card->fpga_version >= DMA_SUPPORTED &&
  1111. sysfs_create_group(&card->dev->dev.kobj, &gpio_attr_group))
  1112. dev_err(&card->dev->dev, "Could not register parameter group for GPIOs\n");
  1113. return 0;
  1114. out_free_irq:
  1115. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1116. free_irq(dev->irq, card);
  1117. tasklet_kill(&card->tlet);
  1118. out_unmap_both:
  1119. kfree(card->dma_bounce);
  1120. pci_set_drvdata(dev, NULL);
  1121. pci_iounmap(dev, card->buffers);
  1122. out_unmap_config:
  1123. pci_iounmap(dev, card->config_regs);
  1124. out_release_regions:
  1125. pci_release_regions(dev);
  1126. out:
  1127. kfree(card);
  1128. return err;
  1129. }
  1130. static int atm_init(struct solos_card *card, struct device *parent)
  1131. {
  1132. int i;
  1133. for (i = 0; i < card->nr_ports; i++) {
  1134. struct sk_buff *skb;
  1135. struct pkt_hdr *header;
  1136. skb_queue_head_init(&card->tx_queue[i]);
  1137. skb_queue_head_init(&card->cli_queue[i]);
  1138. card->atmdev[i] = atm_dev_register("solos-pci", parent, &fpga_ops, -1, NULL);
  1139. if (!card->atmdev[i]) {
  1140. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  1141. atm_remove(card);
  1142. return -ENODEV;
  1143. }
  1144. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  1145. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  1146. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  1147. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  1148. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  1149. card->atmdev[i]->ci_range.vpi_bits = 8;
  1150. card->atmdev[i]->ci_range.vci_bits = 16;
  1151. card->atmdev[i]->dev_data = card;
  1152. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  1153. atm_dev_signal_change(card->atmdev[i], ATM_PHY_SIG_FOUND);
  1154. skb = alloc_skb(sizeof(*header), GFP_KERNEL);
  1155. if (!skb) {
  1156. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  1157. continue;
  1158. }
  1159. header = (void *)skb_put(skb, sizeof(*header));
  1160. header->size = cpu_to_le16(0);
  1161. header->vpi = cpu_to_le16(0);
  1162. header->vci = cpu_to_le16(0);
  1163. header->type = cpu_to_le16(PKT_STATUS);
  1164. fpga_queue(card, i, skb, NULL);
  1165. }
  1166. return 0;
  1167. }
  1168. static void atm_remove(struct solos_card *card)
  1169. {
  1170. int i;
  1171. for (i = 0; i < card->nr_ports; i++) {
  1172. if (card->atmdev[i]) {
  1173. struct sk_buff *skb;
  1174. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1175. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1176. atm_dev_deregister(card->atmdev[i]);
  1177. skb = card->rx_skb[i];
  1178. if (skb) {
  1179. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1180. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  1181. dev_kfree_skb(skb);
  1182. }
  1183. skb = card->tx_skb[i];
  1184. if (skb) {
  1185. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1186. skb->len, PCI_DMA_TODEVICE);
  1187. dev_kfree_skb(skb);
  1188. }
  1189. while ((skb = skb_dequeue(&card->tx_queue[i])))
  1190. dev_kfree_skb(skb);
  1191. }
  1192. }
  1193. }
  1194. static void fpga_remove(struct pci_dev *dev)
  1195. {
  1196. struct solos_card *card = pci_get_drvdata(dev);
  1197. /* Disable IRQs */
  1198. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1199. /* Reset FPGA */
  1200. iowrite32(1, card->config_regs + FPGA_MODE);
  1201. (void)ioread32(card->config_regs + FPGA_MODE);
  1202. if (card->fpga_version >= DMA_SUPPORTED)
  1203. sysfs_remove_group(&card->dev->dev.kobj, &gpio_attr_group);
  1204. atm_remove(card);
  1205. free_irq(dev->irq, card);
  1206. tasklet_kill(&card->tlet);
  1207. kfree(card->dma_bounce);
  1208. /* Release device from reset */
  1209. iowrite32(0, card->config_regs + FPGA_MODE);
  1210. (void)ioread32(card->config_regs + FPGA_MODE);
  1211. pci_iounmap(dev, card->buffers);
  1212. pci_iounmap(dev, card->config_regs);
  1213. pci_release_regions(dev);
  1214. pci_disable_device(dev);
  1215. pci_set_drvdata(dev, NULL);
  1216. kfree(card);
  1217. }
  1218. static struct pci_device_id fpga_pci_tbl[] = {
  1219. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1220. { 0, }
  1221. };
  1222. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1223. static struct pci_driver fpga_driver = {
  1224. .name = "solos",
  1225. .id_table = fpga_pci_tbl,
  1226. .probe = fpga_probe,
  1227. .remove = fpga_remove,
  1228. };
  1229. static int __init solos_pci_init(void)
  1230. {
  1231. BUILD_BUG_ON(sizeof(struct solos_skb_cb) > sizeof(((struct sk_buff *)0)->cb));
  1232. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1233. return pci_register_driver(&fpga_driver);
  1234. }
  1235. static void __exit solos_pci_exit(void)
  1236. {
  1237. pci_unregister_driver(&fpga_driver);
  1238. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1239. }
  1240. module_init(solos_pci_init);
  1241. module_exit(solos_pci_exit);