ath.h 4.3 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef ATH_H
  17. #define ATH_H
  18. #include <linux/skbuff.h>
  19. #include <linux/if_ether.h>
  20. #include <net/mac80211.h>
  21. /*
  22. * The key cache is used for h/w cipher state and also for
  23. * tracking station state such as the current tx antenna.
  24. * We also setup a mapping table between key cache slot indices
  25. * and station state to short-circuit node lookups on rx.
  26. * Different parts have different size key caches. We handle
  27. * up to ATH_KEYMAX entries (could dynamically allocate state).
  28. */
  29. #define ATH_KEYMAX 128 /* max key cache size we handle */
  30. static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  31. struct ath_ani {
  32. bool caldone;
  33. int16_t noise_floor;
  34. unsigned int longcal_timer;
  35. unsigned int shortcal_timer;
  36. unsigned int resetcal_timer;
  37. unsigned int checkani_timer;
  38. struct timer_list timer;
  39. };
  40. enum ath_device_state {
  41. ATH_HW_UNAVAILABLE,
  42. ATH_HW_INITIALIZED,
  43. };
  44. enum ath_bus_type {
  45. ATH_PCI,
  46. ATH_AHB,
  47. ATH_USB,
  48. };
  49. struct reg_dmn_pair_mapping {
  50. u16 regDmnEnum;
  51. u16 reg_5ghz_ctl;
  52. u16 reg_2ghz_ctl;
  53. };
  54. struct ath_regulatory {
  55. char alpha2[2];
  56. u16 country_code;
  57. u16 max_power_level;
  58. u32 tp_scale;
  59. u16 current_rd;
  60. u16 current_rd_ext;
  61. int16_t power_limit;
  62. struct reg_dmn_pair_mapping *regpair;
  63. };
  64. enum ath_crypt_caps {
  65. ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
  66. ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
  67. };
  68. struct ath_keyval {
  69. u8 kv_type;
  70. u8 kv_pad;
  71. u16 kv_len;
  72. u8 kv_val[16]; /* TK */
  73. u8 kv_mic[8]; /* Michael MIC key */
  74. u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
  75. * supports both MIC keys in the same key cache entry;
  76. * in that case, kv_mic is the RX key) */
  77. };
  78. enum ath_cipher {
  79. ATH_CIPHER_WEP = 0,
  80. ATH_CIPHER_AES_OCB = 1,
  81. ATH_CIPHER_AES_CCM = 2,
  82. ATH_CIPHER_CKIP = 3,
  83. ATH_CIPHER_TKIP = 4,
  84. ATH_CIPHER_CLR = 5,
  85. ATH_CIPHER_MIC = 127
  86. };
  87. /**
  88. * struct ath_ops - Register read/write operations
  89. *
  90. * @read: Register read
  91. * @write: Register write
  92. * @enable_write_buffer: Enable multiple register writes
  93. * @disable_write_buffer: Disable multiple register writes
  94. * @write_flush: Flush buffered register writes
  95. */
  96. struct ath_ops {
  97. unsigned int (*read)(void *, u32 reg_offset);
  98. void (*write)(void *, u32 val, u32 reg_offset);
  99. void (*enable_write_buffer)(void *);
  100. void (*disable_write_buffer)(void *);
  101. void (*write_flush) (void *);
  102. };
  103. struct ath_common;
  104. struct ath_bus_ops {
  105. enum ath_bus_type ath_bus_type;
  106. void (*read_cachesize)(struct ath_common *common, int *csz);
  107. bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
  108. void (*bt_coex_prep)(struct ath_common *common);
  109. };
  110. struct ath_common {
  111. void *ah;
  112. void *priv;
  113. struct ieee80211_hw *hw;
  114. int debug_mask;
  115. enum ath_device_state state;
  116. struct ath_ani ani;
  117. u16 cachelsz;
  118. u16 curaid;
  119. u8 macaddr[ETH_ALEN];
  120. u8 curbssid[ETH_ALEN];
  121. u8 bssidmask[ETH_ALEN];
  122. u8 tx_chainmask;
  123. u8 rx_chainmask;
  124. u32 rx_bufsize;
  125. u32 keymax;
  126. DECLARE_BITMAP(keymap, ATH_KEYMAX);
  127. DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
  128. enum ath_crypt_caps crypt_caps;
  129. struct ath_regulatory regulatory;
  130. const struct ath_ops *ops;
  131. const struct ath_bus_ops *bus_ops;
  132. };
  133. struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
  134. u32 len,
  135. gfp_t gfp_mask);
  136. void ath_hw_setbssidmask(struct ath_common *common);
  137. void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
  138. int ath_key_config(struct ath_common *common,
  139. struct ieee80211_vif *vif,
  140. struct ieee80211_sta *sta,
  141. struct ieee80211_key_conf *key);
  142. bool ath_hw_keyreset(struct ath_common *common, u16 entry);
  143. #endif /* ATH_H */