Kconfig 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229
  1. menu "Memory management options"
  2. config QUICKLIST
  3. def_bool y
  4. config MMU
  5. bool "Support for memory management hardware"
  6. depends on !CPU_SH2
  7. default y
  8. help
  9. Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
  10. boot on these systems, this option must not be set.
  11. On other systems (such as the SH-3 and 4) where an MMU exists,
  12. turning this off will boot the kernel on these machines with the
  13. MMU implicitly switched off.
  14. config PAGE_OFFSET
  15. hex
  16. default "0x80000000" if MMU
  17. default "0x00000000"
  18. config MEMORY_START
  19. hex "Physical memory start address"
  20. default "0x08000000"
  21. ---help---
  22. Computers built with Hitachi SuperH processors always
  23. map the ROM starting at address zero. But the processor
  24. does not specify the range that RAM takes.
  25. The physical memory (RAM) start address will be automatically
  26. set to 08000000. Other platforms, such as the Solution Engine
  27. boards typically map RAM at 0C000000.
  28. Tweak this only when porting to a new machine which does not
  29. already have a defconfig. Changing it from the known correct
  30. value on any of the known systems will only lead to disaster.
  31. config MEMORY_SIZE
  32. hex "Physical memory size"
  33. default "0x00400000"
  34. help
  35. This sets the default memory size assumed by your SH kernel. It can
  36. be overridden as normal by the 'mem=' argument on the kernel command
  37. line. If unsure, consult your board specifications or just leave it
  38. as 0x00400000 which was the default value before this became
  39. configurable.
  40. config 32BIT
  41. bool "Support 32-bit physical addressing through PMB"
  42. depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
  43. default y
  44. help
  45. If you say Y here, physical addressing will be extended to
  46. 32-bits through the SH-4A PMB. If this is not set, legacy
  47. 29-bit physical addressing will be used.
  48. config X2TLB
  49. bool "Enable extended TLB mode"
  50. depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
  51. help
  52. Selecting this option will enable the extended mode of the SH-X2
  53. TLB. For legacy SH-X behaviour and interoperability, say N. For
  54. all of the fun new features and a willingless to submit bug reports,
  55. say Y.
  56. config VSYSCALL
  57. bool "Support vsyscall page"
  58. depends on MMU
  59. default y
  60. help
  61. This will enable support for the kernel mapping a vDSO page
  62. in process space, and subsequently handing down the entry point
  63. to the libc through the ELF auxiliary vector.
  64. From the kernel side this is used for the signal trampoline.
  65. For systems with an MMU that can afford to give up a page,
  66. (the default value) say Y.
  67. config NUMA
  68. bool "Non Uniform Memory Access (NUMA) Support"
  69. depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
  70. default n
  71. help
  72. Some SH systems have many various memories scattered around
  73. the address space, each with varying latencies. This enables
  74. support for these blocks by binding them to nodes and allowing
  75. memory policies to be used for prioritizing and controlling
  76. allocation behaviour.
  77. config NODES_SHIFT
  78. int
  79. default "3" if CPU_SUBTYPE_SHX3
  80. default "1"
  81. depends on NEED_MULTIPLE_NODES
  82. config ARCH_FLATMEM_ENABLE
  83. def_bool y
  84. depends on !NUMA
  85. config ARCH_SPARSEMEM_ENABLE
  86. def_bool y
  87. select SPARSEMEM_STATIC
  88. config ARCH_SPARSEMEM_DEFAULT
  89. def_bool y
  90. config MAX_ACTIVE_REGIONS
  91. int
  92. default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
  93. default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
  94. CPU_SUBTYPE_SH7785)
  95. default "1"
  96. config ARCH_POPULATES_NODE_MAP
  97. def_bool y
  98. config ARCH_SELECT_MEMORY_MODEL
  99. def_bool y
  100. config ARCH_ENABLE_MEMORY_HOTPLUG
  101. def_bool y
  102. depends on SPARSEMEM
  103. config ARCH_MEMORY_PROBE
  104. def_bool y
  105. depends on MEMORY_HOTPLUG
  106. choice
  107. prompt "Kernel page size"
  108. default PAGE_SIZE_8KB if X2TLB
  109. default PAGE_SIZE_4KB
  110. config PAGE_SIZE_4KB
  111. bool "4kB"
  112. depends on !X2TLB
  113. help
  114. This is the default page size used by all SuperH CPUs.
  115. config PAGE_SIZE_8KB
  116. bool "8kB"
  117. depends on X2TLB
  118. help
  119. This enables 8kB pages as supported by SH-X2 and later MMUs.
  120. config PAGE_SIZE_64KB
  121. bool "64kB"
  122. depends on CPU_SH4
  123. help
  124. This enables support for 64kB pages, possible on all SH-4
  125. CPUs and later.
  126. endchoice
  127. choice
  128. prompt "HugeTLB page size"
  129. depends on HUGETLB_PAGE && CPU_SH4 && MMU
  130. default HUGETLB_PAGE_SIZE_64K
  131. config HUGETLB_PAGE_SIZE_64K
  132. bool "64kB"
  133. config HUGETLB_PAGE_SIZE_256K
  134. bool "256kB"
  135. depends on X2TLB
  136. config HUGETLB_PAGE_SIZE_1MB
  137. bool "1MB"
  138. config HUGETLB_PAGE_SIZE_4MB
  139. bool "4MB"
  140. depends on X2TLB
  141. config HUGETLB_PAGE_SIZE_64MB
  142. bool "64MB"
  143. depends on X2TLB
  144. endchoice
  145. source "mm/Kconfig"
  146. endmenu
  147. menu "Cache configuration"
  148. config SH7705_CACHE_32KB
  149. bool "Enable 32KB cache size for SH7705"
  150. depends on CPU_SUBTYPE_SH7705
  151. default y
  152. config SH_DIRECT_MAPPED
  153. bool "Use direct-mapped caching"
  154. default n
  155. help
  156. Selecting this option will configure the caches to be direct-mapped,
  157. even if the cache supports a 2 or 4-way mode. This is useful primarily
  158. for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
  159. SH4-202, SH4-501, etc.)
  160. Turn this option off for platforms that do not have a direct-mapped
  161. cache, and you have no need to run the caches in such a configuration.
  162. choice
  163. prompt "Cache mode"
  164. default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
  165. default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
  166. config CACHE_WRITEBACK
  167. bool "Write-back"
  168. depends on CPU_SH2A || CPU_SH3 || CPU_SH4
  169. config CACHE_WRITETHROUGH
  170. bool "Write-through"
  171. help
  172. Selecting this option will configure the caches in write-through
  173. mode, as opposed to the default write-back configuration.
  174. Since there's sill some aliasing issues on SH-4, this option will
  175. unfortunately still require the majority of flushing functions to
  176. be implemented to deal with aliasing.
  177. If unsure, say N.
  178. config CACHE_OFF
  179. bool "Off"
  180. endchoice
  181. endmenu