i915_debugfs.c 19 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #define DRM_I915_RING_DEBUG 1
  35. #if defined(CONFIG_DEBUG_FS)
  36. #define ACTIVE_LIST 1
  37. #define FLUSHING_LIST 2
  38. #define INACTIVE_LIST 3
  39. static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
  40. {
  41. if (obj_priv->user_pin_count > 0)
  42. return "P";
  43. else if (obj_priv->pin_count > 0)
  44. return "p";
  45. else
  46. return " ";
  47. }
  48. static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
  49. {
  50. switch (obj_priv->tiling_mode) {
  51. default:
  52. case I915_TILING_NONE: return " ";
  53. case I915_TILING_X: return "X";
  54. case I915_TILING_Y: return "Y";
  55. }
  56. }
  57. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  58. {
  59. struct drm_info_node *node = (struct drm_info_node *) m->private;
  60. uintptr_t list = (uintptr_t) node->info_ent->data;
  61. struct list_head *head;
  62. struct drm_device *dev = node->minor->dev;
  63. drm_i915_private_t *dev_priv = dev->dev_private;
  64. struct drm_i915_gem_object *obj_priv;
  65. spinlock_t *lock = NULL;
  66. switch (list) {
  67. case ACTIVE_LIST:
  68. seq_printf(m, "Active:\n");
  69. lock = &dev_priv->mm.active_list_lock;
  70. head = &dev_priv->mm.active_list;
  71. break;
  72. case INACTIVE_LIST:
  73. seq_printf(m, "Inactive:\n");
  74. head = &dev_priv->mm.inactive_list;
  75. break;
  76. case FLUSHING_LIST:
  77. seq_printf(m, "Flushing:\n");
  78. head = &dev_priv->mm.flushing_list;
  79. break;
  80. default:
  81. DRM_INFO("Ooops, unexpected list\n");
  82. return 0;
  83. }
  84. if (lock)
  85. spin_lock(lock);
  86. list_for_each_entry(obj_priv, head, list)
  87. {
  88. struct drm_gem_object *obj = obj_priv->obj;
  89. seq_printf(m, " %p: %s %8zd %08x %08x %d%s%s",
  90. obj,
  91. get_pin_flag(obj_priv),
  92. obj->size,
  93. obj->read_domains, obj->write_domain,
  94. obj_priv->last_rendering_seqno,
  95. obj_priv->dirty ? " dirty" : "",
  96. obj_priv->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  97. if (obj->name)
  98. seq_printf(m, " (name: %d)", obj->name);
  99. if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
  100. seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
  101. if (obj_priv->gtt_space != NULL)
  102. seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
  103. seq_printf(m, "\n");
  104. }
  105. if (lock)
  106. spin_unlock(lock);
  107. return 0;
  108. }
  109. static int i915_gem_request_info(struct seq_file *m, void *data)
  110. {
  111. struct drm_info_node *node = (struct drm_info_node *) m->private;
  112. struct drm_device *dev = node->minor->dev;
  113. drm_i915_private_t *dev_priv = dev->dev_private;
  114. struct drm_i915_gem_request *gem_request;
  115. seq_printf(m, "Request:\n");
  116. list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
  117. seq_printf(m, " %d @ %d\n",
  118. gem_request->seqno,
  119. (int) (jiffies - gem_request->emitted_jiffies));
  120. }
  121. return 0;
  122. }
  123. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  124. {
  125. struct drm_info_node *node = (struct drm_info_node *) m->private;
  126. struct drm_device *dev = node->minor->dev;
  127. drm_i915_private_t *dev_priv = dev->dev_private;
  128. if (dev_priv->hw_status_page != NULL) {
  129. seq_printf(m, "Current sequence: %d\n",
  130. i915_get_gem_seqno(dev));
  131. } else {
  132. seq_printf(m, "Current sequence: hws uninitialized\n");
  133. }
  134. seq_printf(m, "Waiter sequence: %d\n",
  135. dev_priv->mm.waiting_gem_seqno);
  136. seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
  137. return 0;
  138. }
  139. static int i915_interrupt_info(struct seq_file *m, void *data)
  140. {
  141. struct drm_info_node *node = (struct drm_info_node *) m->private;
  142. struct drm_device *dev = node->minor->dev;
  143. drm_i915_private_t *dev_priv = dev->dev_private;
  144. if (!IS_IRONLAKE(dev)) {
  145. seq_printf(m, "Interrupt enable: %08x\n",
  146. I915_READ(IER));
  147. seq_printf(m, "Interrupt identity: %08x\n",
  148. I915_READ(IIR));
  149. seq_printf(m, "Interrupt mask: %08x\n",
  150. I915_READ(IMR));
  151. seq_printf(m, "Pipe A stat: %08x\n",
  152. I915_READ(PIPEASTAT));
  153. seq_printf(m, "Pipe B stat: %08x\n",
  154. I915_READ(PIPEBSTAT));
  155. } else {
  156. seq_printf(m, "North Display Interrupt enable: %08x\n",
  157. I915_READ(DEIER));
  158. seq_printf(m, "North Display Interrupt identity: %08x\n",
  159. I915_READ(DEIIR));
  160. seq_printf(m, "North Display Interrupt mask: %08x\n",
  161. I915_READ(DEIMR));
  162. seq_printf(m, "South Display Interrupt enable: %08x\n",
  163. I915_READ(SDEIER));
  164. seq_printf(m, "South Display Interrupt identity: %08x\n",
  165. I915_READ(SDEIIR));
  166. seq_printf(m, "South Display Interrupt mask: %08x\n",
  167. I915_READ(SDEIMR));
  168. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  169. I915_READ(GTIER));
  170. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  171. I915_READ(GTIIR));
  172. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  173. I915_READ(GTIMR));
  174. }
  175. seq_printf(m, "Interrupts received: %d\n",
  176. atomic_read(&dev_priv->irq_received));
  177. if (dev_priv->hw_status_page != NULL) {
  178. seq_printf(m, "Current sequence: %d\n",
  179. i915_get_gem_seqno(dev));
  180. } else {
  181. seq_printf(m, "Current sequence: hws uninitialized\n");
  182. }
  183. seq_printf(m, "Waiter sequence: %d\n",
  184. dev_priv->mm.waiting_gem_seqno);
  185. seq_printf(m, "IRQ sequence: %d\n",
  186. dev_priv->mm.irq_gem_seqno);
  187. return 0;
  188. }
  189. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  190. {
  191. struct drm_info_node *node = (struct drm_info_node *) m->private;
  192. struct drm_device *dev = node->minor->dev;
  193. drm_i915_private_t *dev_priv = dev->dev_private;
  194. int i;
  195. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  196. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  197. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  198. struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
  199. if (obj == NULL) {
  200. seq_printf(m, "Fenced object[%2d] = unused\n", i);
  201. } else {
  202. struct drm_i915_gem_object *obj_priv;
  203. obj_priv = obj->driver_private;
  204. seq_printf(m, "Fenced object[%2d] = %p: %s "
  205. "%08x %08zx %08x %s %08x %08x %d",
  206. i, obj, get_pin_flag(obj_priv),
  207. obj_priv->gtt_offset,
  208. obj->size, obj_priv->stride,
  209. get_tiling_flag(obj_priv),
  210. obj->read_domains, obj->write_domain,
  211. obj_priv->last_rendering_seqno);
  212. if (obj->name)
  213. seq_printf(m, " (name: %d)", obj->name);
  214. seq_printf(m, "\n");
  215. }
  216. }
  217. return 0;
  218. }
  219. static int i915_hws_info(struct seq_file *m, void *data)
  220. {
  221. struct drm_info_node *node = (struct drm_info_node *) m->private;
  222. struct drm_device *dev = node->minor->dev;
  223. drm_i915_private_t *dev_priv = dev->dev_private;
  224. int i;
  225. volatile u32 *hws;
  226. hws = (volatile u32 *)dev_priv->hw_status_page;
  227. if (hws == NULL)
  228. return 0;
  229. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  230. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  231. i * 4,
  232. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  233. }
  234. return 0;
  235. }
  236. static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
  237. {
  238. int page, i;
  239. uint32_t *mem;
  240. for (page = 0; page < page_count; page++) {
  241. mem = kmap_atomic(pages[page], KM_USER0);
  242. for (i = 0; i < PAGE_SIZE; i += 4)
  243. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  244. kunmap_atomic(mem, KM_USER0);
  245. }
  246. }
  247. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  248. {
  249. struct drm_info_node *node = (struct drm_info_node *) m->private;
  250. struct drm_device *dev = node->minor->dev;
  251. drm_i915_private_t *dev_priv = dev->dev_private;
  252. struct drm_gem_object *obj;
  253. struct drm_i915_gem_object *obj_priv;
  254. int ret;
  255. spin_lock(&dev_priv->mm.active_list_lock);
  256. list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
  257. obj = obj_priv->obj;
  258. if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
  259. ret = i915_gem_object_get_pages(obj, 0);
  260. if (ret) {
  261. DRM_ERROR("Failed to get pages: %d\n", ret);
  262. spin_unlock(&dev_priv->mm.active_list_lock);
  263. return ret;
  264. }
  265. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
  266. i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
  267. i915_gem_object_put_pages(obj);
  268. }
  269. }
  270. spin_unlock(&dev_priv->mm.active_list_lock);
  271. return 0;
  272. }
  273. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  274. {
  275. struct drm_info_node *node = (struct drm_info_node *) m->private;
  276. struct drm_device *dev = node->minor->dev;
  277. drm_i915_private_t *dev_priv = dev->dev_private;
  278. u8 *virt;
  279. uint32_t *ptr, off;
  280. if (!dev_priv->ring.ring_obj) {
  281. seq_printf(m, "No ringbuffer setup\n");
  282. return 0;
  283. }
  284. virt = dev_priv->ring.virtual_start;
  285. for (off = 0; off < dev_priv->ring.Size; off += 4) {
  286. ptr = (uint32_t *)(virt + off);
  287. seq_printf(m, "%08x : %08x\n", off, *ptr);
  288. }
  289. return 0;
  290. }
  291. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  292. {
  293. struct drm_info_node *node = (struct drm_info_node *) m->private;
  294. struct drm_device *dev = node->minor->dev;
  295. drm_i915_private_t *dev_priv = dev->dev_private;
  296. unsigned int head, tail;
  297. head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  298. tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  299. seq_printf(m, "RingHead : %08x\n", head);
  300. seq_printf(m, "RingTail : %08x\n", tail);
  301. seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size);
  302. seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
  303. return 0;
  304. }
  305. static int i915_error_state(struct seq_file *m, void *unused)
  306. {
  307. struct drm_info_node *node = (struct drm_info_node *) m->private;
  308. struct drm_device *dev = node->minor->dev;
  309. drm_i915_private_t *dev_priv = dev->dev_private;
  310. struct drm_i915_error_state *error;
  311. unsigned long flags;
  312. spin_lock_irqsave(&dev_priv->error_lock, flags);
  313. if (!dev_priv->first_error) {
  314. seq_printf(m, "no error state collected\n");
  315. goto out;
  316. }
  317. error = dev_priv->first_error;
  318. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  319. error->time.tv_usec);
  320. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  321. seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  322. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  323. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  324. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  325. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  326. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  327. if (IS_I965G(dev)) {
  328. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  329. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  330. }
  331. out:
  332. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  333. return 0;
  334. }
  335. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  336. {
  337. struct drm_info_node *node = (struct drm_info_node *) m->private;
  338. struct drm_device *dev = node->minor->dev;
  339. drm_i915_private_t *dev_priv = dev->dev_private;
  340. u16 crstanddelay = I915_READ16(CRSTANDVID);
  341. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  342. return 0;
  343. }
  344. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  345. {
  346. struct drm_info_node *node = (struct drm_info_node *) m->private;
  347. struct drm_device *dev = node->minor->dev;
  348. drm_i915_private_t *dev_priv = dev->dev_private;
  349. u16 rgvswctl = I915_READ16(MEMSWCTL);
  350. seq_printf(m, "Last command: 0x%01x\n", (rgvswctl >> 13) & 0x3);
  351. seq_printf(m, "Command status: %d\n", (rgvswctl >> 12) & 1);
  352. seq_printf(m, "P%d DELAY 0x%02x\n", (rgvswctl >> 8) & 0xf,
  353. rgvswctl & 0x3f);
  354. return 0;
  355. }
  356. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  357. {
  358. struct drm_info_node *node = (struct drm_info_node *) m->private;
  359. struct drm_device *dev = node->minor->dev;
  360. drm_i915_private_t *dev_priv = dev->dev_private;
  361. u32 delayfreq;
  362. int i;
  363. for (i = 0; i < 16; i++) {
  364. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  365. seq_printf(m, "P%02dVIDFREQ: 0x%08x\n", i, delayfreq);
  366. }
  367. return 0;
  368. }
  369. static inline int MAP_TO_MV(int map)
  370. {
  371. return 1250 - (map * 25);
  372. }
  373. static int i915_inttoext_table(struct seq_file *m, void *unused)
  374. {
  375. struct drm_info_node *node = (struct drm_info_node *) m->private;
  376. struct drm_device *dev = node->minor->dev;
  377. drm_i915_private_t *dev_priv = dev->dev_private;
  378. u32 inttoext;
  379. int i;
  380. for (i = 1; i <= 32; i++) {
  381. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  382. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  383. }
  384. return 0;
  385. }
  386. static int i915_drpc_info(struct seq_file *m, void *unused)
  387. {
  388. struct drm_info_node *node = (struct drm_info_node *) m->private;
  389. struct drm_device *dev = node->minor->dev;
  390. drm_i915_private_t *dev_priv = dev->dev_private;
  391. u32 rgvmodectl = I915_READ(MEMMODECTL);
  392. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  393. "yes" : "no");
  394. seq_printf(m, "Boost freq: %d\n",
  395. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  396. MEMMODE_BOOST_FREQ_SHIFT);
  397. seq_printf(m, "HW control enabled: %s\n",
  398. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  399. seq_printf(m, "SW control enabled: %s\n",
  400. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  401. seq_printf(m, "Gated voltage change: %s\n",
  402. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  403. seq_printf(m, "Starting frequency: P%d\n",
  404. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  405. seq_printf(m, "Max frequency: P%d\n",
  406. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  407. seq_printf(m, "Min frequency: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  408. return 0;
  409. }
  410. static int i915_fbc_status(struct seq_file *m, void *unused)
  411. {
  412. struct drm_info_node *node = (struct drm_info_node *) m->private;
  413. struct drm_device *dev = node->minor->dev;
  414. struct drm_crtc *crtc;
  415. drm_i915_private_t *dev_priv = dev->dev_private;
  416. bool fbc_enabled = false;
  417. if (!dev_priv->display.fbc_enabled) {
  418. seq_printf(m, "FBC unsupported on this chipset\n");
  419. return 0;
  420. }
  421. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  422. if (!crtc->enabled)
  423. continue;
  424. if (dev_priv->display.fbc_enabled(crtc))
  425. fbc_enabled = true;
  426. }
  427. if (fbc_enabled) {
  428. seq_printf(m, "FBC enabled\n");
  429. } else {
  430. seq_printf(m, "FBC disabled: ");
  431. switch (dev_priv->no_fbc_reason) {
  432. case FBC_STOLEN_TOO_SMALL:
  433. seq_printf(m, "not enough stolen memory");
  434. break;
  435. case FBC_UNSUPPORTED_MODE:
  436. seq_printf(m, "mode not supported");
  437. break;
  438. case FBC_MODE_TOO_LARGE:
  439. seq_printf(m, "mode too large");
  440. break;
  441. case FBC_BAD_PLANE:
  442. seq_printf(m, "FBC unsupported on plane");
  443. break;
  444. case FBC_NOT_TILED:
  445. seq_printf(m, "scanout buffer not tiled");
  446. break;
  447. default:
  448. seq_printf(m, "unknown reason");
  449. }
  450. seq_printf(m, "\n");
  451. }
  452. return 0;
  453. }
  454. static int
  455. i915_wedged_open(struct inode *inode,
  456. struct file *filp)
  457. {
  458. filp->private_data = inode->i_private;
  459. return 0;
  460. }
  461. static ssize_t
  462. i915_wedged_read(struct file *filp,
  463. char __user *ubuf,
  464. size_t max,
  465. loff_t *ppos)
  466. {
  467. struct drm_device *dev = filp->private_data;
  468. drm_i915_private_t *dev_priv = dev->dev_private;
  469. char buf[80];
  470. int len;
  471. len = snprintf(buf, sizeof (buf),
  472. "wedged : %d\n",
  473. atomic_read(&dev_priv->mm.wedged));
  474. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  475. }
  476. static ssize_t
  477. i915_wedged_write(struct file *filp,
  478. const char __user *ubuf,
  479. size_t cnt,
  480. loff_t *ppos)
  481. {
  482. struct drm_device *dev = filp->private_data;
  483. drm_i915_private_t *dev_priv = dev->dev_private;
  484. char buf[20];
  485. int val = 1;
  486. if (cnt > 0) {
  487. if (cnt > sizeof (buf) - 1)
  488. return -EINVAL;
  489. if (copy_from_user(buf, ubuf, cnt))
  490. return -EFAULT;
  491. buf[cnt] = 0;
  492. val = simple_strtoul(buf, NULL, 0);
  493. }
  494. DRM_INFO("Manually setting wedged to %d\n", val);
  495. atomic_set(&dev_priv->mm.wedged, val);
  496. if (val) {
  497. DRM_WAKEUP(&dev_priv->irq_queue);
  498. queue_work(dev_priv->wq, &dev_priv->error_work);
  499. }
  500. return cnt;
  501. }
  502. static const struct file_operations i915_wedged_fops = {
  503. .owner = THIS_MODULE,
  504. .open = i915_wedged_open,
  505. .read = i915_wedged_read,
  506. .write = i915_wedged_write,
  507. };
  508. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  509. * allocated we need to hook into the minor for release. */
  510. static int
  511. drm_add_fake_info_node(struct drm_minor *minor,
  512. struct dentry *ent,
  513. const void *key)
  514. {
  515. struct drm_info_node *node;
  516. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  517. if (node == NULL) {
  518. debugfs_remove(ent);
  519. return -ENOMEM;
  520. }
  521. node->minor = minor;
  522. node->dent = ent;
  523. node->info_ent = (void *) key;
  524. list_add(&node->list, &minor->debugfs_nodes.list);
  525. return 0;
  526. }
  527. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  528. {
  529. struct drm_device *dev = minor->dev;
  530. struct dentry *ent;
  531. ent = debugfs_create_file("i915_wedged",
  532. S_IRUGO | S_IWUSR,
  533. root, dev,
  534. &i915_wedged_fops);
  535. if (IS_ERR(ent))
  536. return PTR_ERR(ent);
  537. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  538. }
  539. static struct drm_info_list i915_debugfs_list[] = {
  540. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  541. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  542. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  543. {"i915_gem_request", i915_gem_request_info, 0},
  544. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  545. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  546. {"i915_gem_interrupt", i915_interrupt_info, 0},
  547. {"i915_gem_hws", i915_hws_info, 0},
  548. {"i915_ringbuffer_data", i915_ringbuffer_data, 0},
  549. {"i915_ringbuffer_info", i915_ringbuffer_info, 0},
  550. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  551. {"i915_error_state", i915_error_state, 0},
  552. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  553. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  554. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  555. {"i915_inttoext_table", i915_inttoext_table, 0},
  556. {"i915_drpc_info", i915_drpc_info, 0},
  557. {"i915_fbc_status", i915_fbc_status, 0},
  558. };
  559. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  560. int i915_debugfs_init(struct drm_minor *minor)
  561. {
  562. int ret;
  563. ret = i915_wedged_create(minor->debugfs_root, minor);
  564. if (ret)
  565. return ret;
  566. return drm_debugfs_create_files(i915_debugfs_list,
  567. I915_DEBUGFS_ENTRIES,
  568. minor->debugfs_root, minor);
  569. }
  570. void i915_debugfs_cleanup(struct drm_minor *minor)
  571. {
  572. drm_debugfs_remove_files(i915_debugfs_list,
  573. I915_DEBUGFS_ENTRIES, minor);
  574. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  575. 1, minor);
  576. }
  577. #endif /* CONFIG_DEBUG_FS */