iwl3945-base.c 122 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/ieee80211_radiotap.h>
  46. #include <net/mac80211.h>
  47. #include <asm/div64.h>
  48. #define DRV_NAME "iwl3945"
  49. #include "iwl-fh.h"
  50. #include "iwl-3945-fh.h"
  51. #include "iwl-commands.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-3945.h"
  54. #include "iwl-core.h"
  55. #include "iwl-helpers.h"
  56. #include "iwl-dev.h"
  57. #include "iwl-spectrum.h"
  58. #include "iwl-legacy.h"
  59. /*
  60. * module name, copyright, version, etc.
  61. */
  62. #define DRV_DESCRIPTION \
  63. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  64. #ifdef CONFIG_IWLWIFI_DEBUG
  65. #define VD "d"
  66. #else
  67. #define VD
  68. #endif
  69. /*
  70. * add "s" to indicate spectrum measurement included.
  71. * we add it here to be consistent with previous releases in which
  72. * this was configurable.
  73. */
  74. #define DRV_VERSION IWLWIFI_VERSION VD "s"
  75. #define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
  76. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  77. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  78. MODULE_VERSION(DRV_VERSION);
  79. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  80. MODULE_LICENSE("GPL");
  81. /* module parameters */
  82. struct iwl_mod_params iwl3945_mod_params = {
  83. .sw_crypto = 1,
  84. .restart_fw = 1,
  85. /* the rest are 0 by default */
  86. };
  87. /**
  88. * iwl3945_get_antenna_flags - Get antenna flags for RXON command
  89. * @priv: eeprom and antenna fields are used to determine antenna flags
  90. *
  91. * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
  92. * iwl3945_mod_params.antenna specifies the antenna diversity mode:
  93. *
  94. * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
  95. * IWL_ANTENNA_MAIN - Force MAIN antenna
  96. * IWL_ANTENNA_AUX - Force AUX antenna
  97. */
  98. __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
  99. {
  100. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  101. switch (iwl3945_mod_params.antenna) {
  102. case IWL_ANTENNA_DIVERSITY:
  103. return 0;
  104. case IWL_ANTENNA_MAIN:
  105. if (eeprom->antenna_switch_type)
  106. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  107. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  108. case IWL_ANTENNA_AUX:
  109. if (eeprom->antenna_switch_type)
  110. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  111. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  112. }
  113. /* bad antenna selector value */
  114. IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
  115. iwl3945_mod_params.antenna);
  116. return 0; /* "diversity" is default if error */
  117. }
  118. static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
  119. struct ieee80211_key_conf *keyconf,
  120. u8 sta_id)
  121. {
  122. unsigned long flags;
  123. __le16 key_flags = 0;
  124. int ret;
  125. key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
  126. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  127. if (sta_id == priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id)
  128. key_flags |= STA_KEY_MULTICAST_MSK;
  129. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  130. keyconf->hw_key_idx = keyconf->keyidx;
  131. key_flags &= ~STA_KEY_FLG_INVALID;
  132. spin_lock_irqsave(&priv->sta_lock, flags);
  133. priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  134. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  135. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  136. keyconf->keylen);
  137. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  138. keyconf->keylen);
  139. if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  140. == STA_KEY_FLG_NO_ENC)
  141. priv->stations[sta_id].sta.key.key_offset =
  142. iwl_get_free_ucode_key_index(priv);
  143. /* else, we are overriding an existing key => no need to allocated room
  144. * in uCode. */
  145. WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  146. "no space for a new key");
  147. priv->stations[sta_id].sta.key.key_flags = key_flags;
  148. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  149. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  150. IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
  151. ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  152. spin_unlock_irqrestore(&priv->sta_lock, flags);
  153. return ret;
  154. }
  155. static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
  156. struct ieee80211_key_conf *keyconf,
  157. u8 sta_id)
  158. {
  159. return -EOPNOTSUPP;
  160. }
  161. static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
  162. struct ieee80211_key_conf *keyconf,
  163. u8 sta_id)
  164. {
  165. return -EOPNOTSUPP;
  166. }
  167. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  168. {
  169. unsigned long flags;
  170. struct iwl_addsta_cmd sta_cmd;
  171. spin_lock_irqsave(&priv->sta_lock, flags);
  172. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
  173. memset(&priv->stations[sta_id].sta.key, 0,
  174. sizeof(struct iwl4965_keyinfo));
  175. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  176. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  177. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  178. memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd));
  179. spin_unlock_irqrestore(&priv->sta_lock, flags);
  180. IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
  181. return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
  182. }
  183. static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
  184. struct ieee80211_key_conf *keyconf, u8 sta_id)
  185. {
  186. int ret = 0;
  187. keyconf->hw_key_idx = HW_KEY_DYNAMIC;
  188. switch (keyconf->cipher) {
  189. case WLAN_CIPHER_SUITE_CCMP:
  190. ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
  191. break;
  192. case WLAN_CIPHER_SUITE_TKIP:
  193. ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
  194. break;
  195. case WLAN_CIPHER_SUITE_WEP40:
  196. case WLAN_CIPHER_SUITE_WEP104:
  197. ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
  198. break;
  199. default:
  200. IWL_ERR(priv, "Unknown alg: %s alg=%x\n", __func__,
  201. keyconf->cipher);
  202. ret = -EINVAL;
  203. }
  204. IWL_DEBUG_WEP(priv, "Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
  205. keyconf->cipher, keyconf->keylen, keyconf->keyidx,
  206. sta_id, ret);
  207. return ret;
  208. }
  209. static int iwl3945_remove_static_key(struct iwl_priv *priv)
  210. {
  211. int ret = -EOPNOTSUPP;
  212. return ret;
  213. }
  214. static int iwl3945_set_static_key(struct iwl_priv *priv,
  215. struct ieee80211_key_conf *key)
  216. {
  217. if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  218. key->cipher == WLAN_CIPHER_SUITE_WEP104)
  219. return -EOPNOTSUPP;
  220. IWL_ERR(priv, "Static key invalid: cipher %x\n", key->cipher);
  221. return -EINVAL;
  222. }
  223. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  224. {
  225. struct list_head *element;
  226. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  227. priv->frames_count);
  228. while (!list_empty(&priv->free_frames)) {
  229. element = priv->free_frames.next;
  230. list_del(element);
  231. kfree(list_entry(element, struct iwl3945_frame, list));
  232. priv->frames_count--;
  233. }
  234. if (priv->frames_count) {
  235. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  236. priv->frames_count);
  237. priv->frames_count = 0;
  238. }
  239. }
  240. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  241. {
  242. struct iwl3945_frame *frame;
  243. struct list_head *element;
  244. if (list_empty(&priv->free_frames)) {
  245. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  246. if (!frame) {
  247. IWL_ERR(priv, "Could not allocate frame!\n");
  248. return NULL;
  249. }
  250. priv->frames_count++;
  251. return frame;
  252. }
  253. element = priv->free_frames.next;
  254. list_del(element);
  255. return list_entry(element, struct iwl3945_frame, list);
  256. }
  257. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  258. {
  259. memset(frame, 0, sizeof(*frame));
  260. list_add(&frame->list, &priv->free_frames);
  261. }
  262. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  263. struct ieee80211_hdr *hdr,
  264. int left)
  265. {
  266. if (!iwl_is_associated(priv, IWL_RXON_CTX_BSS) || !priv->beacon_skb)
  267. return 0;
  268. if (priv->beacon_skb->len > left)
  269. return 0;
  270. memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
  271. return priv->beacon_skb->len;
  272. }
  273. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  274. {
  275. struct iwl3945_frame *frame;
  276. unsigned int frame_size;
  277. int rc;
  278. u8 rate;
  279. frame = iwl3945_get_free_frame(priv);
  280. if (!frame) {
  281. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  282. "command.\n");
  283. return -ENOMEM;
  284. }
  285. rate = iwl_rate_get_lowest_plcp(priv,
  286. &priv->contexts[IWL_RXON_CTX_BSS]);
  287. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  288. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  289. &frame->u.cmd[0]);
  290. iwl3945_free_frame(priv, frame);
  291. return rc;
  292. }
  293. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  294. {
  295. if (priv->_3945.shared_virt)
  296. dma_free_coherent(&priv->pci_dev->dev,
  297. sizeof(struct iwl3945_shared),
  298. priv->_3945.shared_virt,
  299. priv->_3945.shared_phys);
  300. }
  301. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  302. struct ieee80211_tx_info *info,
  303. struct iwl_device_cmd *cmd,
  304. struct sk_buff *skb_frag,
  305. int sta_id)
  306. {
  307. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  308. struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
  309. tx_cmd->sec_ctl = 0;
  310. switch (keyinfo->cipher) {
  311. case WLAN_CIPHER_SUITE_CCMP:
  312. tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
  313. memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
  314. IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
  315. break;
  316. case WLAN_CIPHER_SUITE_TKIP:
  317. break;
  318. case WLAN_CIPHER_SUITE_WEP104:
  319. tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
  320. /* fall through */
  321. case WLAN_CIPHER_SUITE_WEP40:
  322. tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
  323. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  324. memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
  325. IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
  326. "with key %d\n", info->control.hw_key->hw_key_idx);
  327. break;
  328. default:
  329. IWL_ERR(priv, "Unknown encode cipher %x\n", keyinfo->cipher);
  330. break;
  331. }
  332. }
  333. /*
  334. * handle build REPLY_TX command notification.
  335. */
  336. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  337. struct iwl_device_cmd *cmd,
  338. struct ieee80211_tx_info *info,
  339. struct ieee80211_hdr *hdr, u8 std_id)
  340. {
  341. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  342. __le32 tx_flags = tx_cmd->tx_flags;
  343. __le16 fc = hdr->frame_control;
  344. tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  345. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  346. tx_flags |= TX_CMD_FLG_ACK_MSK;
  347. if (ieee80211_is_mgmt(fc))
  348. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  349. if (ieee80211_is_probe_resp(fc) &&
  350. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  351. tx_flags |= TX_CMD_FLG_TSF_MSK;
  352. } else {
  353. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  354. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  355. }
  356. tx_cmd->sta_id = std_id;
  357. if (ieee80211_has_morefrags(fc))
  358. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  359. if (ieee80211_is_data_qos(fc)) {
  360. u8 *qc = ieee80211_get_qos_ctl(hdr);
  361. tx_cmd->tid_tspec = qc[0] & 0xf;
  362. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  363. } else {
  364. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  365. }
  366. priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
  367. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  368. if (ieee80211_is_mgmt(fc)) {
  369. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  370. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
  371. else
  372. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
  373. } else {
  374. tx_cmd->timeout.pm_frame_timeout = 0;
  375. }
  376. tx_cmd->driver_txop = 0;
  377. tx_cmd->tx_flags = tx_flags;
  378. tx_cmd->next_frame_len = 0;
  379. }
  380. /*
  381. * start REPLY_TX command process
  382. */
  383. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  384. {
  385. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  386. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  387. struct iwl3945_tx_cmd *tx_cmd;
  388. struct iwl_tx_queue *txq = NULL;
  389. struct iwl_queue *q = NULL;
  390. struct iwl_device_cmd *out_cmd;
  391. struct iwl_cmd_meta *out_meta;
  392. dma_addr_t phys_addr;
  393. dma_addr_t txcmd_phys;
  394. int txq_id = skb_get_queue_mapping(skb);
  395. u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
  396. u8 id;
  397. u8 unicast;
  398. u8 sta_id;
  399. u8 tid = 0;
  400. __le16 fc;
  401. u8 wait_write_ptr = 0;
  402. unsigned long flags;
  403. spin_lock_irqsave(&priv->lock, flags);
  404. if (iwl_is_rfkill(priv)) {
  405. IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
  406. goto drop_unlock;
  407. }
  408. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  409. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  410. goto drop_unlock;
  411. }
  412. unicast = !is_multicast_ether_addr(hdr->addr1);
  413. id = 0;
  414. fc = hdr->frame_control;
  415. #ifdef CONFIG_IWLWIFI_DEBUG
  416. if (ieee80211_is_auth(fc))
  417. IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
  418. else if (ieee80211_is_assoc_req(fc))
  419. IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
  420. else if (ieee80211_is_reassoc_req(fc))
  421. IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
  422. #endif
  423. spin_unlock_irqrestore(&priv->lock, flags);
  424. hdr_len = ieee80211_hdrlen(fc);
  425. /* Find index into station table for destination station */
  426. sta_id = iwl_sta_id_or_broadcast(
  427. priv, &priv->contexts[IWL_RXON_CTX_BSS],
  428. info->control.sta);
  429. if (sta_id == IWL_INVALID_STATION) {
  430. IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
  431. hdr->addr1);
  432. goto drop;
  433. }
  434. IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
  435. if (ieee80211_is_data_qos(fc)) {
  436. u8 *qc = ieee80211_get_qos_ctl(hdr);
  437. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  438. if (unlikely(tid >= MAX_TID_COUNT))
  439. goto drop;
  440. }
  441. /* Descriptor for chosen Tx queue */
  442. txq = &priv->txq[txq_id];
  443. q = &txq->q;
  444. if ((iwl_queue_space(q) < q->high_mark))
  445. goto drop;
  446. spin_lock_irqsave(&priv->lock, flags);
  447. idx = get_cmd_index(q, q->write_ptr, 0);
  448. /* Set up driver data for this TFD */
  449. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  450. txq->txb[q->write_ptr].skb = skb;
  451. txq->txb[q->write_ptr].ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  452. /* Init first empty entry in queue's array of Tx/cmd buffers */
  453. out_cmd = txq->cmd[idx];
  454. out_meta = &txq->meta[idx];
  455. tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  456. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  457. memset(tx_cmd, 0, sizeof(*tx_cmd));
  458. /*
  459. * Set up the Tx-command (not MAC!) header.
  460. * Store the chosen Tx queue and TFD index within the sequence field;
  461. * after Tx, uCode's Tx response will return this value so driver can
  462. * locate the frame within the tx queue and do post-tx processing.
  463. */
  464. out_cmd->hdr.cmd = REPLY_TX;
  465. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  466. INDEX_TO_SEQ(q->write_ptr)));
  467. /* Copy MAC header from skb into command buffer */
  468. memcpy(tx_cmd->hdr, hdr, hdr_len);
  469. if (info->control.hw_key)
  470. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
  471. /* TODO need this for burst mode later on */
  472. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  473. /* set is_hcca to 0; it probably will never be implemented */
  474. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  475. /* Total # bytes to be transmitted */
  476. len = (u16)skb->len;
  477. tx_cmd->len = cpu_to_le16(len);
  478. iwl_dbg_log_tx_data_frame(priv, len, hdr);
  479. iwl_update_stats(priv, true, fc, len);
  480. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  481. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  482. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  483. txq->need_update = 1;
  484. } else {
  485. wait_write_ptr = 1;
  486. txq->need_update = 0;
  487. }
  488. IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
  489. le16_to_cpu(out_cmd->hdr.sequence));
  490. IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
  491. iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
  492. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
  493. ieee80211_hdrlen(fc));
  494. /*
  495. * Use the first empty entry in this queue's command buffer array
  496. * to contain the Tx command and MAC header concatenated together
  497. * (payload data will be in another buffer).
  498. * Size of this varies, due to varying MAC header length.
  499. * If end is not dword aligned, we'll have 2 extra bytes at the end
  500. * of the MAC header (device reads on dword boundaries).
  501. * We'll tell device about this padding later.
  502. */
  503. len = sizeof(struct iwl3945_tx_cmd) +
  504. sizeof(struct iwl_cmd_header) + hdr_len;
  505. len_org = len;
  506. len = (len + 3) & ~3;
  507. if (len_org != len)
  508. len_org = 1;
  509. else
  510. len_org = 0;
  511. /* Physical address of this Tx command's header (not MAC header!),
  512. * within command buffer array. */
  513. txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  514. len, PCI_DMA_TODEVICE);
  515. /* we do not map meta data ... so we can safely access address to
  516. * provide to unmap command*/
  517. dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
  518. dma_unmap_len_set(out_meta, len, len);
  519. /* Add buffer containing Tx command and MAC(!) header to TFD's
  520. * first entry */
  521. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  522. txcmd_phys, len, 1, 0);
  523. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  524. * if any (802.11 null frames have no payload). */
  525. len = skb->len - hdr_len;
  526. if (len) {
  527. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  528. len, PCI_DMA_TODEVICE);
  529. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  530. phys_addr, len,
  531. 0, U32_PAD(len));
  532. }
  533. /* Tell device the write index *just past* this latest filled TFD */
  534. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  535. iwl_txq_update_write_ptr(priv, txq);
  536. spin_unlock_irqrestore(&priv->lock, flags);
  537. if ((iwl_queue_space(q) < q->high_mark)
  538. && priv->mac80211_registered) {
  539. if (wait_write_ptr) {
  540. spin_lock_irqsave(&priv->lock, flags);
  541. txq->need_update = 1;
  542. iwl_txq_update_write_ptr(priv, txq);
  543. spin_unlock_irqrestore(&priv->lock, flags);
  544. }
  545. iwl_stop_queue(priv, skb_get_queue_mapping(skb));
  546. }
  547. return 0;
  548. drop_unlock:
  549. spin_unlock_irqrestore(&priv->lock, flags);
  550. drop:
  551. return -1;
  552. }
  553. static int iwl3945_get_measurement(struct iwl_priv *priv,
  554. struct ieee80211_measurement_params *params,
  555. u8 type)
  556. {
  557. struct iwl_spectrum_cmd spectrum;
  558. struct iwl_rx_packet *pkt;
  559. struct iwl_host_cmd cmd = {
  560. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  561. .data = (void *)&spectrum,
  562. .flags = CMD_WANT_SKB,
  563. };
  564. u32 add_time = le64_to_cpu(params->start_time);
  565. int rc;
  566. int spectrum_resp_status;
  567. int duration = le16_to_cpu(params->duration);
  568. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  569. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  570. add_time = iwl_usecs_to_beacons(priv,
  571. le64_to_cpu(params->start_time) - priv->_3945.last_tsf,
  572. le16_to_cpu(ctx->timing.beacon_interval));
  573. memset(&spectrum, 0, sizeof(spectrum));
  574. spectrum.channel_count = cpu_to_le16(1);
  575. spectrum.flags =
  576. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  577. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  578. cmd.len = sizeof(spectrum);
  579. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  580. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  581. spectrum.start_time =
  582. iwl_add_beacon_time(priv,
  583. priv->_3945.last_beacon_time, add_time,
  584. le16_to_cpu(ctx->timing.beacon_interval));
  585. else
  586. spectrum.start_time = 0;
  587. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  588. spectrum.channels[0].channel = params->channel;
  589. spectrum.channels[0].type = type;
  590. if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
  591. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  592. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  593. rc = iwl_send_cmd_sync(priv, &cmd);
  594. if (rc)
  595. return rc;
  596. pkt = (struct iwl_rx_packet *)cmd.reply_page;
  597. if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
  598. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  599. rc = -EIO;
  600. }
  601. spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
  602. switch (spectrum_resp_status) {
  603. case 0: /* Command will be handled */
  604. if (pkt->u.spectrum.id != 0xff) {
  605. IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
  606. pkt->u.spectrum.id);
  607. priv->measurement_status &= ~MEASUREMENT_READY;
  608. }
  609. priv->measurement_status |= MEASUREMENT_ACTIVE;
  610. rc = 0;
  611. break;
  612. case 1: /* Command will not be handled */
  613. rc = -EAGAIN;
  614. break;
  615. }
  616. iwl_free_pages(priv, cmd.reply_page);
  617. return rc;
  618. }
  619. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  620. struct iwl_rx_mem_buffer *rxb)
  621. {
  622. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  623. struct iwl_alive_resp *palive;
  624. struct delayed_work *pwork;
  625. palive = &pkt->u.alive_frame;
  626. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  627. "0x%01X 0x%01X\n",
  628. palive->is_valid, palive->ver_type,
  629. palive->ver_subtype);
  630. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  631. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  632. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  633. sizeof(struct iwl_alive_resp));
  634. pwork = &priv->init_alive_start;
  635. } else {
  636. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  637. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  638. sizeof(struct iwl_alive_resp));
  639. pwork = &priv->alive_start;
  640. iwl3945_disable_events(priv);
  641. }
  642. /* We delay the ALIVE response by 5ms to
  643. * give the HW RF Kill time to activate... */
  644. if (palive->is_valid == UCODE_VALID_OK)
  645. queue_delayed_work(priv->workqueue, pwork,
  646. msecs_to_jiffies(5));
  647. else
  648. IWL_WARN(priv, "uCode did not respond OK.\n");
  649. }
  650. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  651. struct iwl_rx_mem_buffer *rxb)
  652. {
  653. #ifdef CONFIG_IWLWIFI_DEBUG
  654. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  655. #endif
  656. IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  657. }
  658. static void iwl3945_bg_beacon_update(struct work_struct *work)
  659. {
  660. struct iwl_priv *priv =
  661. container_of(work, struct iwl_priv, beacon_update);
  662. struct sk_buff *beacon;
  663. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  664. beacon = ieee80211_beacon_get(priv->hw,
  665. priv->contexts[IWL_RXON_CTX_BSS].vif);
  666. if (!beacon) {
  667. IWL_ERR(priv, "update beacon failed\n");
  668. return;
  669. }
  670. mutex_lock(&priv->mutex);
  671. /* new beacon skb is allocated every time; dispose previous.*/
  672. if (priv->beacon_skb)
  673. dev_kfree_skb(priv->beacon_skb);
  674. priv->beacon_skb = beacon;
  675. mutex_unlock(&priv->mutex);
  676. iwl3945_send_beacon_cmd(priv);
  677. }
  678. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  679. struct iwl_rx_mem_buffer *rxb)
  680. {
  681. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  682. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  683. #ifdef CONFIG_IWLWIFI_DEBUG
  684. u8 rate = beacon->beacon_notify_hdr.rate;
  685. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  686. "tsf %d %d rate %d\n",
  687. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  688. beacon->beacon_notify_hdr.failure_frame,
  689. le32_to_cpu(beacon->ibss_mgr_status),
  690. le32_to_cpu(beacon->high_tsf),
  691. le32_to_cpu(beacon->low_tsf), rate);
  692. #endif
  693. priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  694. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  695. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  696. queue_work(priv->workqueue, &priv->beacon_update);
  697. }
  698. /* Handle notification from uCode that card's power state is changing
  699. * due to software, hardware, or critical temperature RFKILL */
  700. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  701. struct iwl_rx_mem_buffer *rxb)
  702. {
  703. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  704. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  705. unsigned long status = priv->status;
  706. IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
  707. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  708. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  709. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  710. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  711. if (flags & HW_CARD_DISABLED)
  712. set_bit(STATUS_RF_KILL_HW, &priv->status);
  713. else
  714. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  715. iwl_scan_cancel(priv);
  716. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  717. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  718. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  719. test_bit(STATUS_RF_KILL_HW, &priv->status));
  720. else
  721. wake_up_interruptible(&priv->wait_command_queue);
  722. }
  723. /**
  724. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  725. *
  726. * Setup the RX handlers for each of the reply types sent from the uCode
  727. * to the host.
  728. *
  729. * This function chains into the hardware specific files for them to setup
  730. * any hardware specific handlers as well.
  731. */
  732. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  733. {
  734. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  735. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  736. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  737. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  738. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  739. iwl_rx_spectrum_measure_notif;
  740. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  741. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  742. iwl_rx_pm_debug_statistics_notif;
  743. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  744. /*
  745. * The same handler is used for both the REPLY to a discrete
  746. * statistics request from the host as well as for the periodic
  747. * statistics notifications (after received beacons) from the uCode.
  748. */
  749. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics;
  750. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  751. iwl_setup_rx_scan_handlers(priv);
  752. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  753. /* Set up hardware specific Rx handlers */
  754. iwl3945_hw_rx_handler_setup(priv);
  755. }
  756. /************************** RX-FUNCTIONS ****************************/
  757. /*
  758. * Rx theory of operation
  759. *
  760. * The host allocates 32 DMA target addresses and passes the host address
  761. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  762. * 0 to 31
  763. *
  764. * Rx Queue Indexes
  765. * The host/firmware share two index registers for managing the Rx buffers.
  766. *
  767. * The READ index maps to the first position that the firmware may be writing
  768. * to -- the driver can read up to (but not including) this position and get
  769. * good data.
  770. * The READ index is managed by the firmware once the card is enabled.
  771. *
  772. * The WRITE index maps to the last position the driver has read from -- the
  773. * position preceding WRITE is the last slot the firmware can place a packet.
  774. *
  775. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  776. * WRITE = READ.
  777. *
  778. * During initialization, the host sets up the READ queue position to the first
  779. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  780. *
  781. * When the firmware places a packet in a buffer, it will advance the READ index
  782. * and fire the RX interrupt. The driver can then query the READ index and
  783. * process as many packets as possible, moving the WRITE index forward as it
  784. * resets the Rx queue buffers with new memory.
  785. *
  786. * The management in the driver is as follows:
  787. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  788. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  789. * to replenish the iwl->rxq->rx_free.
  790. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  791. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  792. * 'processed' and 'read' driver indexes as well)
  793. * + A received packet is processed and handed to the kernel network stack,
  794. * detached from the iwl->rxq. The driver 'processed' index is updated.
  795. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  796. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  797. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  798. * were enough free buffers and RX_STALLED is set it is cleared.
  799. *
  800. *
  801. * Driver sequence:
  802. *
  803. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  804. * iwl3945_rx_queue_restock
  805. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  806. * queue, updates firmware pointers, and updates
  807. * the WRITE index. If insufficient rx_free buffers
  808. * are available, schedules iwl3945_rx_replenish
  809. *
  810. * -- enable interrupts --
  811. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  812. * READ INDEX, detaching the SKB from the pool.
  813. * Moves the packet buffer from queue to rx_used.
  814. * Calls iwl3945_rx_queue_restock to refill any empty
  815. * slots.
  816. * ...
  817. *
  818. */
  819. /**
  820. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  821. */
  822. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  823. dma_addr_t dma_addr)
  824. {
  825. return cpu_to_le32((u32)dma_addr);
  826. }
  827. /**
  828. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  829. *
  830. * If there are slots in the RX queue that need to be restocked,
  831. * and we have free pre-allocated buffers, fill the ranks as much
  832. * as we can, pulling from rx_free.
  833. *
  834. * This moves the 'write' index forward to catch up with 'processed', and
  835. * also updates the memory address in the firmware to reference the new
  836. * target buffer.
  837. */
  838. static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
  839. {
  840. struct iwl_rx_queue *rxq = &priv->rxq;
  841. struct list_head *element;
  842. struct iwl_rx_mem_buffer *rxb;
  843. unsigned long flags;
  844. int write;
  845. spin_lock_irqsave(&rxq->lock, flags);
  846. write = rxq->write & ~0x7;
  847. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  848. /* Get next free Rx buffer, remove from free list */
  849. element = rxq->rx_free.next;
  850. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  851. list_del(element);
  852. /* Point to Rx buffer via next RBD in circular buffer */
  853. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
  854. rxq->queue[rxq->write] = rxb;
  855. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  856. rxq->free_count--;
  857. }
  858. spin_unlock_irqrestore(&rxq->lock, flags);
  859. /* If the pre-allocated buffer pool is dropping low, schedule to
  860. * refill it */
  861. if (rxq->free_count <= RX_LOW_WATERMARK)
  862. queue_work(priv->workqueue, &priv->rx_replenish);
  863. /* If we've added more space for the firmware to place data, tell it.
  864. * Increment device's write pointer in multiples of 8. */
  865. if ((rxq->write_actual != (rxq->write & ~0x7))
  866. || (abs(rxq->write - rxq->read) > 7)) {
  867. spin_lock_irqsave(&rxq->lock, flags);
  868. rxq->need_update = 1;
  869. spin_unlock_irqrestore(&rxq->lock, flags);
  870. iwl_rx_queue_update_write_ptr(priv, rxq);
  871. }
  872. }
  873. /**
  874. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  875. *
  876. * When moving to rx_free an SKB is allocated for the slot.
  877. *
  878. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  879. * This is called as a scheduled work item (except for during initialization)
  880. */
  881. static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  882. {
  883. struct iwl_rx_queue *rxq = &priv->rxq;
  884. struct list_head *element;
  885. struct iwl_rx_mem_buffer *rxb;
  886. struct page *page;
  887. unsigned long flags;
  888. gfp_t gfp_mask = priority;
  889. while (1) {
  890. spin_lock_irqsave(&rxq->lock, flags);
  891. if (list_empty(&rxq->rx_used)) {
  892. spin_unlock_irqrestore(&rxq->lock, flags);
  893. return;
  894. }
  895. spin_unlock_irqrestore(&rxq->lock, flags);
  896. if (rxq->free_count > RX_LOW_WATERMARK)
  897. gfp_mask |= __GFP_NOWARN;
  898. if (priv->hw_params.rx_page_order > 0)
  899. gfp_mask |= __GFP_COMP;
  900. /* Alloc a new receive buffer */
  901. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  902. if (!page) {
  903. if (net_ratelimit())
  904. IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
  905. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  906. net_ratelimit())
  907. IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
  908. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  909. rxq->free_count);
  910. /* We don't reschedule replenish work here -- we will
  911. * call the restock method and if it still needs
  912. * more buffers it will schedule replenish */
  913. break;
  914. }
  915. spin_lock_irqsave(&rxq->lock, flags);
  916. if (list_empty(&rxq->rx_used)) {
  917. spin_unlock_irqrestore(&rxq->lock, flags);
  918. __free_pages(page, priv->hw_params.rx_page_order);
  919. return;
  920. }
  921. element = rxq->rx_used.next;
  922. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  923. list_del(element);
  924. spin_unlock_irqrestore(&rxq->lock, flags);
  925. rxb->page = page;
  926. /* Get physical address of RB/SKB */
  927. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  928. PAGE_SIZE << priv->hw_params.rx_page_order,
  929. PCI_DMA_FROMDEVICE);
  930. spin_lock_irqsave(&rxq->lock, flags);
  931. list_add_tail(&rxb->list, &rxq->rx_free);
  932. rxq->free_count++;
  933. priv->alloc_rxb_page++;
  934. spin_unlock_irqrestore(&rxq->lock, flags);
  935. }
  936. }
  937. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  938. {
  939. unsigned long flags;
  940. int i;
  941. spin_lock_irqsave(&rxq->lock, flags);
  942. INIT_LIST_HEAD(&rxq->rx_free);
  943. INIT_LIST_HEAD(&rxq->rx_used);
  944. /* Fill the rx_used queue with _all_ of the Rx buffers */
  945. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  946. /* In the reset function, these buffers may have been allocated
  947. * to an SKB, so we need to unmap and free potential storage */
  948. if (rxq->pool[i].page != NULL) {
  949. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  950. PAGE_SIZE << priv->hw_params.rx_page_order,
  951. PCI_DMA_FROMDEVICE);
  952. __iwl_free_pages(priv, rxq->pool[i].page);
  953. rxq->pool[i].page = NULL;
  954. }
  955. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  956. }
  957. /* Set us so that we have processed and used all buffers, but have
  958. * not restocked the Rx queue with fresh buffers */
  959. rxq->read = rxq->write = 0;
  960. rxq->write_actual = 0;
  961. rxq->free_count = 0;
  962. spin_unlock_irqrestore(&rxq->lock, flags);
  963. }
  964. void iwl3945_rx_replenish(void *data)
  965. {
  966. struct iwl_priv *priv = data;
  967. unsigned long flags;
  968. iwl3945_rx_allocate(priv, GFP_KERNEL);
  969. spin_lock_irqsave(&priv->lock, flags);
  970. iwl3945_rx_queue_restock(priv);
  971. spin_unlock_irqrestore(&priv->lock, flags);
  972. }
  973. static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
  974. {
  975. iwl3945_rx_allocate(priv, GFP_ATOMIC);
  976. iwl3945_rx_queue_restock(priv);
  977. }
  978. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  979. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  980. * This free routine walks the list of POOL entries and if SKB is set to
  981. * non NULL it is unmapped and freed
  982. */
  983. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  984. {
  985. int i;
  986. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  987. if (rxq->pool[i].page != NULL) {
  988. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  989. PAGE_SIZE << priv->hw_params.rx_page_order,
  990. PCI_DMA_FROMDEVICE);
  991. __iwl_free_pages(priv, rxq->pool[i].page);
  992. rxq->pool[i].page = NULL;
  993. }
  994. }
  995. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  996. rxq->bd_dma);
  997. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  998. rxq->rb_stts, rxq->rb_stts_dma);
  999. rxq->bd = NULL;
  1000. rxq->rb_stts = NULL;
  1001. }
  1002. /* Convert linear signal-to-noise ratio into dB */
  1003. static u8 ratio2dB[100] = {
  1004. /* 0 1 2 3 4 5 6 7 8 9 */
  1005. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  1006. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  1007. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  1008. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  1009. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  1010. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  1011. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  1012. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  1013. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  1014. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  1015. };
  1016. /* Calculates a relative dB value from a ratio of linear
  1017. * (i.e. not dB) signal levels.
  1018. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  1019. int iwl3945_calc_db_from_ratio(int sig_ratio)
  1020. {
  1021. /* 1000:1 or higher just report as 60 dB */
  1022. if (sig_ratio >= 1000)
  1023. return 60;
  1024. /* 100:1 or higher, divide by 10 and use table,
  1025. * add 20 dB to make up for divide by 10 */
  1026. if (sig_ratio >= 100)
  1027. return 20 + (int)ratio2dB[sig_ratio/10];
  1028. /* We shouldn't see this */
  1029. if (sig_ratio < 1)
  1030. return 0;
  1031. /* Use table for ratios 1:1 - 99:1 */
  1032. return (int)ratio2dB[sig_ratio];
  1033. }
  1034. /**
  1035. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  1036. *
  1037. * Uses the priv->rx_handlers callback function array to invoke
  1038. * the appropriate handlers, including command responses,
  1039. * frame-received notifications, and other notifications.
  1040. */
  1041. static void iwl3945_rx_handle(struct iwl_priv *priv)
  1042. {
  1043. struct iwl_rx_mem_buffer *rxb;
  1044. struct iwl_rx_packet *pkt;
  1045. struct iwl_rx_queue *rxq = &priv->rxq;
  1046. u32 r, i;
  1047. int reclaim;
  1048. unsigned long flags;
  1049. u8 fill_rx = 0;
  1050. u32 count = 8;
  1051. int total_empty = 0;
  1052. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  1053. * buffer that the driver may process (last buffer filled by ucode). */
  1054. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  1055. i = rxq->read;
  1056. /* calculate total frames need to be restock after handling RX */
  1057. total_empty = r - rxq->write_actual;
  1058. if (total_empty < 0)
  1059. total_empty += RX_QUEUE_SIZE;
  1060. if (total_empty > (RX_QUEUE_SIZE / 2))
  1061. fill_rx = 1;
  1062. /* Rx interrupt, but nothing sent from uCode */
  1063. if (i == r)
  1064. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  1065. while (i != r) {
  1066. int len;
  1067. rxb = rxq->queue[i];
  1068. /* If an RXB doesn't have a Rx queue slot associated with it,
  1069. * then a bug has been introduced in the queue refilling
  1070. * routines -- catch it here */
  1071. BUG_ON(rxb == NULL);
  1072. rxq->queue[i] = NULL;
  1073. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  1074. PAGE_SIZE << priv->hw_params.rx_page_order,
  1075. PCI_DMA_FROMDEVICE);
  1076. pkt = rxb_addr(rxb);
  1077. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1078. len += sizeof(u32); /* account for status word */
  1079. trace_iwlwifi_dev_rx(priv, pkt, len);
  1080. /* Reclaim a command buffer only if this packet is a response
  1081. * to a (driver-originated) command.
  1082. * If the packet (e.g. Rx frame) originated from uCode,
  1083. * there is no command buffer to reclaim.
  1084. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  1085. * but apparently a few don't get set; catch them here. */
  1086. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  1087. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  1088. (pkt->hdr.cmd != REPLY_TX);
  1089. /* Based on type of command response or notification,
  1090. * handle those that need handling via function in
  1091. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  1092. if (priv->rx_handlers[pkt->hdr.cmd]) {
  1093. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
  1094. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  1095. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  1096. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  1097. } else {
  1098. /* No handling needed */
  1099. IWL_DEBUG_RX(priv,
  1100. "r %d i %d No handler needed for %s, 0x%02x\n",
  1101. r, i, get_cmd_string(pkt->hdr.cmd),
  1102. pkt->hdr.cmd);
  1103. }
  1104. /*
  1105. * XXX: After here, we should always check rxb->page
  1106. * against NULL before touching it or its virtual
  1107. * memory (pkt). Because some rx_handler might have
  1108. * already taken or freed the pages.
  1109. */
  1110. if (reclaim) {
  1111. /* Invoke any callbacks, transfer the buffer to caller,
  1112. * and fire off the (possibly) blocking iwl_send_cmd()
  1113. * as we reclaim the driver command queue */
  1114. if (rxb->page)
  1115. iwl_tx_cmd_complete(priv, rxb);
  1116. else
  1117. IWL_WARN(priv, "Claim null rxb?\n");
  1118. }
  1119. /* Reuse the page if possible. For notification packets and
  1120. * SKBs that fail to Rx correctly, add them back into the
  1121. * rx_free list for reuse later. */
  1122. spin_lock_irqsave(&rxq->lock, flags);
  1123. if (rxb->page != NULL) {
  1124. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  1125. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  1126. PCI_DMA_FROMDEVICE);
  1127. list_add_tail(&rxb->list, &rxq->rx_free);
  1128. rxq->free_count++;
  1129. } else
  1130. list_add_tail(&rxb->list, &rxq->rx_used);
  1131. spin_unlock_irqrestore(&rxq->lock, flags);
  1132. i = (i + 1) & RX_QUEUE_MASK;
  1133. /* If there are a lot of unused frames,
  1134. * restock the Rx queue so ucode won't assert. */
  1135. if (fill_rx) {
  1136. count++;
  1137. if (count >= 8) {
  1138. rxq->read = i;
  1139. iwl3945_rx_replenish_now(priv);
  1140. count = 0;
  1141. }
  1142. }
  1143. }
  1144. /* Backtrack one entry */
  1145. rxq->read = i;
  1146. if (fill_rx)
  1147. iwl3945_rx_replenish_now(priv);
  1148. else
  1149. iwl3945_rx_queue_restock(priv);
  1150. }
  1151. /* call this function to flush any scheduled tasklet */
  1152. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  1153. {
  1154. /* wait to make sure we flush pending tasklet*/
  1155. synchronize_irq(priv->pci_dev->irq);
  1156. tasklet_kill(&priv->irq_tasklet);
  1157. }
  1158. static const char *desc_lookup(int i)
  1159. {
  1160. switch (i) {
  1161. case 1:
  1162. return "FAIL";
  1163. case 2:
  1164. return "BAD_PARAM";
  1165. case 3:
  1166. return "BAD_CHECKSUM";
  1167. case 4:
  1168. return "NMI_INTERRUPT";
  1169. case 5:
  1170. return "SYSASSERT";
  1171. case 6:
  1172. return "FATAL_ERROR";
  1173. }
  1174. return "UNKNOWN";
  1175. }
  1176. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1177. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1178. void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  1179. {
  1180. u32 i;
  1181. u32 desc, time, count, base, data1;
  1182. u32 blink1, blink2, ilink1, ilink2;
  1183. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1184. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1185. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1186. return;
  1187. }
  1188. count = iwl_read_targ_mem(priv, base);
  1189. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1190. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1191. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1192. priv->status, count);
  1193. }
  1194. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  1195. "ilink1 nmiPC Line\n");
  1196. for (i = ERROR_START_OFFSET;
  1197. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  1198. i += ERROR_ELEM_SIZE) {
  1199. desc = iwl_read_targ_mem(priv, base + i);
  1200. time =
  1201. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  1202. blink1 =
  1203. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  1204. blink2 =
  1205. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  1206. ilink1 =
  1207. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  1208. ilink2 =
  1209. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  1210. data1 =
  1211. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  1212. IWL_ERR(priv,
  1213. "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  1214. desc_lookup(desc), desc, time, blink1, blink2,
  1215. ilink1, ilink2, data1);
  1216. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
  1217. 0, blink1, blink2, ilink1, ilink2);
  1218. }
  1219. }
  1220. #define EVENT_START_OFFSET (6 * sizeof(u32))
  1221. /**
  1222. * iwl3945_print_event_log - Dump error event log to syslog
  1223. *
  1224. */
  1225. static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1226. u32 num_events, u32 mode,
  1227. int pos, char **buf, size_t bufsz)
  1228. {
  1229. u32 i;
  1230. u32 base; /* SRAM byte address of event log header */
  1231. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1232. u32 ptr; /* SRAM byte address of log data */
  1233. u32 ev, time, data; /* event log data */
  1234. unsigned long reg_flags;
  1235. if (num_events == 0)
  1236. return pos;
  1237. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1238. if (mode == 0)
  1239. event_size = 2 * sizeof(u32);
  1240. else
  1241. event_size = 3 * sizeof(u32);
  1242. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1243. /* Make sure device is powered up for SRAM reads */
  1244. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1245. iwl_grab_nic_access(priv);
  1246. /* Set starting address; reads will auto-increment */
  1247. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1248. rmb();
  1249. /* "time" is actually "data" for mode 0 (no timestamp).
  1250. * place event id # at far right for easier visual parsing. */
  1251. for (i = 0; i < num_events; i++) {
  1252. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1253. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1254. if (mode == 0) {
  1255. /* data, ev */
  1256. if (bufsz) {
  1257. pos += scnprintf(*buf + pos, bufsz - pos,
  1258. "0x%08x:%04u\n",
  1259. time, ev);
  1260. } else {
  1261. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  1262. trace_iwlwifi_dev_ucode_event(priv, 0,
  1263. time, ev);
  1264. }
  1265. } else {
  1266. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1267. if (bufsz) {
  1268. pos += scnprintf(*buf + pos, bufsz - pos,
  1269. "%010u:0x%08x:%04u\n",
  1270. time, data, ev);
  1271. } else {
  1272. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
  1273. time, data, ev);
  1274. trace_iwlwifi_dev_ucode_event(priv, time,
  1275. data, ev);
  1276. }
  1277. }
  1278. }
  1279. /* Allow device to power down */
  1280. iwl_release_nic_access(priv);
  1281. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1282. return pos;
  1283. }
  1284. /**
  1285. * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
  1286. */
  1287. static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1288. u32 num_wraps, u32 next_entry,
  1289. u32 size, u32 mode,
  1290. int pos, char **buf, size_t bufsz)
  1291. {
  1292. /*
  1293. * display the newest DEFAULT_LOG_ENTRIES entries
  1294. * i.e the entries just before the next ont that uCode would fill.
  1295. */
  1296. if (num_wraps) {
  1297. if (next_entry < size) {
  1298. pos = iwl3945_print_event_log(priv,
  1299. capacity - (size - next_entry),
  1300. size - next_entry, mode,
  1301. pos, buf, bufsz);
  1302. pos = iwl3945_print_event_log(priv, 0,
  1303. next_entry, mode,
  1304. pos, buf, bufsz);
  1305. } else
  1306. pos = iwl3945_print_event_log(priv, next_entry - size,
  1307. size, mode,
  1308. pos, buf, bufsz);
  1309. } else {
  1310. if (next_entry < size)
  1311. pos = iwl3945_print_event_log(priv, 0,
  1312. next_entry, mode,
  1313. pos, buf, bufsz);
  1314. else
  1315. pos = iwl3945_print_event_log(priv, next_entry - size,
  1316. size, mode,
  1317. pos, buf, bufsz);
  1318. }
  1319. return pos;
  1320. }
  1321. #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
  1322. int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1323. char **buf, bool display)
  1324. {
  1325. u32 base; /* SRAM byte address of event log header */
  1326. u32 capacity; /* event log capacity in # entries */
  1327. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1328. u32 num_wraps; /* # times uCode wrapped to top of log */
  1329. u32 next_entry; /* index of next entry to be written by uCode */
  1330. u32 size; /* # entries that we'll print */
  1331. int pos = 0;
  1332. size_t bufsz = 0;
  1333. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1334. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1335. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1336. return -EINVAL;
  1337. }
  1338. /* event log header */
  1339. capacity = iwl_read_targ_mem(priv, base);
  1340. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1341. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1342. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1343. if (capacity > priv->cfg->base_params->max_event_log_size) {
  1344. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1345. capacity, priv->cfg->base_params->max_event_log_size);
  1346. capacity = priv->cfg->base_params->max_event_log_size;
  1347. }
  1348. if (next_entry > priv->cfg->base_params->max_event_log_size) {
  1349. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1350. next_entry, priv->cfg->base_params->max_event_log_size);
  1351. next_entry = priv->cfg->base_params->max_event_log_size;
  1352. }
  1353. size = num_wraps ? capacity : next_entry;
  1354. /* bail out if nothing in log */
  1355. if (size == 0) {
  1356. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1357. return pos;
  1358. }
  1359. #ifdef CONFIG_IWLWIFI_DEBUG
  1360. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1361. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1362. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1363. #else
  1364. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1365. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1366. #endif
  1367. IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
  1368. size);
  1369. #ifdef CONFIG_IWLWIFI_DEBUG
  1370. if (display) {
  1371. if (full_log)
  1372. bufsz = capacity * 48;
  1373. else
  1374. bufsz = size * 48;
  1375. *buf = kmalloc(bufsz, GFP_KERNEL);
  1376. if (!*buf)
  1377. return -ENOMEM;
  1378. }
  1379. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1380. /* if uCode has wrapped back to top of log,
  1381. * start at the oldest entry,
  1382. * i.e the next one that uCode would fill.
  1383. */
  1384. if (num_wraps)
  1385. pos = iwl3945_print_event_log(priv, next_entry,
  1386. capacity - next_entry, mode,
  1387. pos, buf, bufsz);
  1388. /* (then/else) start at top of log */
  1389. pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
  1390. pos, buf, bufsz);
  1391. } else
  1392. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1393. next_entry, size, mode,
  1394. pos, buf, bufsz);
  1395. #else
  1396. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1397. next_entry, size, mode,
  1398. pos, buf, bufsz);
  1399. #endif
  1400. return pos;
  1401. }
  1402. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  1403. {
  1404. u32 inta, handled = 0;
  1405. u32 inta_fh;
  1406. unsigned long flags;
  1407. #ifdef CONFIG_IWLWIFI_DEBUG
  1408. u32 inta_mask;
  1409. #endif
  1410. spin_lock_irqsave(&priv->lock, flags);
  1411. /* Ack/clear/reset pending uCode interrupts.
  1412. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1413. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  1414. inta = iwl_read32(priv, CSR_INT);
  1415. iwl_write32(priv, CSR_INT, inta);
  1416. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  1417. * Any new interrupts that happen after this, either while we're
  1418. * in this tasklet, or later, will show up in next ISR/tasklet. */
  1419. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1420. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  1421. #ifdef CONFIG_IWLWIFI_DEBUG
  1422. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1423. /* just for debug */
  1424. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1425. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1426. inta, inta_mask, inta_fh);
  1427. }
  1428. #endif
  1429. spin_unlock_irqrestore(&priv->lock, flags);
  1430. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  1431. * atomic, make sure that inta covers all the interrupts that
  1432. * we've discovered, even if FH interrupt came in just after
  1433. * reading CSR_INT. */
  1434. if (inta_fh & CSR39_FH_INT_RX_MASK)
  1435. inta |= CSR_INT_BIT_FH_RX;
  1436. if (inta_fh & CSR39_FH_INT_TX_MASK)
  1437. inta |= CSR_INT_BIT_FH_TX;
  1438. /* Now service all interrupt bits discovered above. */
  1439. if (inta & CSR_INT_BIT_HW_ERR) {
  1440. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1441. /* Tell the device to stop sending interrupts */
  1442. iwl_disable_interrupts(priv);
  1443. priv->isr_stats.hw++;
  1444. iwl_irq_handle_error(priv);
  1445. handled |= CSR_INT_BIT_HW_ERR;
  1446. return;
  1447. }
  1448. #ifdef CONFIG_IWLWIFI_DEBUG
  1449. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1450. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1451. if (inta & CSR_INT_BIT_SCD) {
  1452. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1453. "the frame/frames.\n");
  1454. priv->isr_stats.sch++;
  1455. }
  1456. /* Alive notification via Rx interrupt will do the real work */
  1457. if (inta & CSR_INT_BIT_ALIVE) {
  1458. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1459. priv->isr_stats.alive++;
  1460. }
  1461. }
  1462. #endif
  1463. /* Safely ignore these bits for debug checks below */
  1464. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1465. /* Error detected by uCode */
  1466. if (inta & CSR_INT_BIT_SW_ERR) {
  1467. IWL_ERR(priv, "Microcode SW error detected. "
  1468. "Restarting 0x%X.\n", inta);
  1469. priv->isr_stats.sw++;
  1470. iwl_irq_handle_error(priv);
  1471. handled |= CSR_INT_BIT_SW_ERR;
  1472. }
  1473. /* uCode wakes up after power-down sleep */
  1474. if (inta & CSR_INT_BIT_WAKEUP) {
  1475. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1476. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1477. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  1478. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  1479. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  1480. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  1481. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  1482. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  1483. priv->isr_stats.wakeup++;
  1484. handled |= CSR_INT_BIT_WAKEUP;
  1485. }
  1486. /* All uCode command responses, including Tx command responses,
  1487. * Rx "responses" (frame-received notification), and other
  1488. * notifications from uCode come through here*/
  1489. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1490. iwl3945_rx_handle(priv);
  1491. priv->isr_stats.rx++;
  1492. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1493. }
  1494. if (inta & CSR_INT_BIT_FH_TX) {
  1495. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1496. priv->isr_stats.tx++;
  1497. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  1498. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  1499. (FH39_SRVC_CHNL), 0x0);
  1500. handled |= CSR_INT_BIT_FH_TX;
  1501. }
  1502. if (inta & ~handled) {
  1503. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1504. priv->isr_stats.unhandled++;
  1505. }
  1506. if (inta & ~priv->inta_mask) {
  1507. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1508. inta & ~priv->inta_mask);
  1509. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1510. }
  1511. /* Re-enable all interrupts */
  1512. /* only Re-enable if disabled by irq */
  1513. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1514. iwl_enable_interrupts(priv);
  1515. #ifdef CONFIG_IWLWIFI_DEBUG
  1516. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1517. inta = iwl_read32(priv, CSR_INT);
  1518. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1519. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1520. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1521. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1522. }
  1523. #endif
  1524. }
  1525. static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv,
  1526. struct ieee80211_vif *vif,
  1527. enum ieee80211_band band,
  1528. struct iwl3945_scan_channel *scan_ch)
  1529. {
  1530. const struct ieee80211_supported_band *sband;
  1531. u16 passive_dwell = 0;
  1532. u16 active_dwell = 0;
  1533. int added = 0;
  1534. u8 channel = 0;
  1535. sband = iwl_get_hw_mode(priv, band);
  1536. if (!sband) {
  1537. IWL_ERR(priv, "invalid band\n");
  1538. return added;
  1539. }
  1540. active_dwell = iwl_get_active_dwell_time(priv, band, 0);
  1541. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1542. if (passive_dwell <= active_dwell)
  1543. passive_dwell = active_dwell + 1;
  1544. channel = iwl_get_single_channel_number(priv, band);
  1545. if (channel) {
  1546. scan_ch->channel = channel;
  1547. scan_ch->type = 0; /* passive */
  1548. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1549. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1550. /* Set txpower levels to defaults */
  1551. scan_ch->tpc.dsp_atten = 110;
  1552. if (band == IEEE80211_BAND_5GHZ)
  1553. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1554. else
  1555. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1556. added++;
  1557. } else
  1558. IWL_ERR(priv, "no valid channel found\n");
  1559. return added;
  1560. }
  1561. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  1562. enum ieee80211_band band,
  1563. u8 is_active, u8 n_probes,
  1564. struct iwl3945_scan_channel *scan_ch,
  1565. struct ieee80211_vif *vif)
  1566. {
  1567. struct ieee80211_channel *chan;
  1568. const struct ieee80211_supported_band *sband;
  1569. const struct iwl_channel_info *ch_info;
  1570. u16 passive_dwell = 0;
  1571. u16 active_dwell = 0;
  1572. int added, i;
  1573. sband = iwl_get_hw_mode(priv, band);
  1574. if (!sband)
  1575. return 0;
  1576. active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
  1577. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1578. if (passive_dwell <= active_dwell)
  1579. passive_dwell = active_dwell + 1;
  1580. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  1581. chan = priv->scan_request->channels[i];
  1582. if (chan->band != band)
  1583. continue;
  1584. scan_ch->channel = chan->hw_value;
  1585. ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
  1586. if (!is_channel_valid(ch_info)) {
  1587. IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
  1588. scan_ch->channel);
  1589. continue;
  1590. }
  1591. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1592. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1593. /* If passive , set up for auto-switch
  1594. * and use long active_dwell time.
  1595. */
  1596. if (!is_active || is_channel_passive(ch_info) ||
  1597. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  1598. scan_ch->type = 0; /* passive */
  1599. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  1600. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  1601. } else {
  1602. scan_ch->type = 1; /* active */
  1603. }
  1604. /* Set direct probe bits. These may be used both for active
  1605. * scan channels (probes gets sent right away),
  1606. * or for passive channels (probes get se sent only after
  1607. * hearing clear Rx packet).*/
  1608. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  1609. if (n_probes)
  1610. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1611. } else {
  1612. /* uCode v1 does not allow setting direct probe bits on
  1613. * passive channel. */
  1614. if ((scan_ch->type & 1) && n_probes)
  1615. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1616. }
  1617. /* Set txpower levels to defaults */
  1618. scan_ch->tpc.dsp_atten = 110;
  1619. /* scan_pwr_info->tpc.dsp_atten; */
  1620. /*scan_pwr_info->tpc.tx_gain; */
  1621. if (band == IEEE80211_BAND_5GHZ)
  1622. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1623. else {
  1624. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1625. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1626. * power level:
  1627. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1628. */
  1629. }
  1630. IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
  1631. scan_ch->channel,
  1632. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  1633. (scan_ch->type & 1) ?
  1634. active_dwell : passive_dwell);
  1635. scan_ch++;
  1636. added++;
  1637. }
  1638. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  1639. return added;
  1640. }
  1641. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  1642. struct ieee80211_rate *rates)
  1643. {
  1644. int i;
  1645. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  1646. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  1647. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  1648. rates[i].hw_value_short = i;
  1649. rates[i].flags = 0;
  1650. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  1651. /*
  1652. * If CCK != 1M then set short preamble rate flag.
  1653. */
  1654. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  1655. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  1656. }
  1657. }
  1658. }
  1659. /******************************************************************************
  1660. *
  1661. * uCode download functions
  1662. *
  1663. ******************************************************************************/
  1664. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  1665. {
  1666. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1667. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1668. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1669. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1670. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1671. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1672. }
  1673. /**
  1674. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  1675. * looking at all data.
  1676. */
  1677. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  1678. {
  1679. u32 val;
  1680. u32 save_len = len;
  1681. int rc = 0;
  1682. u32 errcnt;
  1683. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1684. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1685. IWL39_RTC_INST_LOWER_BOUND);
  1686. errcnt = 0;
  1687. for (; len > 0; len -= sizeof(u32), image++) {
  1688. /* read data comes through single port, auto-incr addr */
  1689. /* NOTE: Use the debugless read so we don't flood kernel log
  1690. * if IWL_DL_IO is set */
  1691. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1692. if (val != le32_to_cpu(*image)) {
  1693. IWL_ERR(priv, "uCode INST section is invalid at "
  1694. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1695. save_len - len, val, le32_to_cpu(*image));
  1696. rc = -EIO;
  1697. errcnt++;
  1698. if (errcnt >= 20)
  1699. break;
  1700. }
  1701. }
  1702. if (!errcnt)
  1703. IWL_DEBUG_INFO(priv,
  1704. "ucode image in INSTRUCTION memory is good\n");
  1705. return rc;
  1706. }
  1707. /**
  1708. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1709. * using sample data 100 bytes apart. If these sample points are good,
  1710. * it's a pretty good bet that everything between them is good, too.
  1711. */
  1712. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1713. {
  1714. u32 val;
  1715. int rc = 0;
  1716. u32 errcnt = 0;
  1717. u32 i;
  1718. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1719. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1720. /* read data comes through single port, auto-incr addr */
  1721. /* NOTE: Use the debugless read so we don't flood kernel log
  1722. * if IWL_DL_IO is set */
  1723. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1724. i + IWL39_RTC_INST_LOWER_BOUND);
  1725. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1726. if (val != le32_to_cpu(*image)) {
  1727. #if 0 /* Enable this if you want to see details */
  1728. IWL_ERR(priv, "uCode INST section is invalid at "
  1729. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1730. i, val, *image);
  1731. #endif
  1732. rc = -EIO;
  1733. errcnt++;
  1734. if (errcnt >= 3)
  1735. break;
  1736. }
  1737. }
  1738. return rc;
  1739. }
  1740. /**
  1741. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  1742. * and verify its contents
  1743. */
  1744. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  1745. {
  1746. __le32 *image;
  1747. u32 len;
  1748. int rc = 0;
  1749. /* Try bootstrap */
  1750. image = (__le32 *)priv->ucode_boot.v_addr;
  1751. len = priv->ucode_boot.len;
  1752. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1753. if (rc == 0) {
  1754. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1755. return 0;
  1756. }
  1757. /* Try initialize */
  1758. image = (__le32 *)priv->ucode_init.v_addr;
  1759. len = priv->ucode_init.len;
  1760. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1761. if (rc == 0) {
  1762. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1763. return 0;
  1764. }
  1765. /* Try runtime/protocol */
  1766. image = (__le32 *)priv->ucode_code.v_addr;
  1767. len = priv->ucode_code.len;
  1768. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1769. if (rc == 0) {
  1770. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1771. return 0;
  1772. }
  1773. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1774. /* Since nothing seems to match, show first several data entries in
  1775. * instruction SRAM, so maybe visual inspection will give a clue.
  1776. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1777. image = (__le32 *)priv->ucode_boot.v_addr;
  1778. len = priv->ucode_boot.len;
  1779. rc = iwl3945_verify_inst_full(priv, image, len);
  1780. return rc;
  1781. }
  1782. static void iwl3945_nic_start(struct iwl_priv *priv)
  1783. {
  1784. /* Remove all resets to allow NIC to operate */
  1785. iwl_write32(priv, CSR_RESET, 0);
  1786. }
  1787. #define IWL3945_UCODE_GET(item) \
  1788. static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\
  1789. { \
  1790. return le32_to_cpu(ucode->u.v1.item); \
  1791. }
  1792. static u32 iwl3945_ucode_get_header_size(u32 api_ver)
  1793. {
  1794. return 24;
  1795. }
  1796. static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode)
  1797. {
  1798. return (u8 *) ucode->u.v1.data;
  1799. }
  1800. IWL3945_UCODE_GET(inst_size);
  1801. IWL3945_UCODE_GET(data_size);
  1802. IWL3945_UCODE_GET(init_size);
  1803. IWL3945_UCODE_GET(init_data_size);
  1804. IWL3945_UCODE_GET(boot_size);
  1805. /**
  1806. * iwl3945_read_ucode - Read uCode images from disk file.
  1807. *
  1808. * Copy into buffers for card to fetch via bus-mastering
  1809. */
  1810. static int iwl3945_read_ucode(struct iwl_priv *priv)
  1811. {
  1812. const struct iwl_ucode_header *ucode;
  1813. int ret = -EINVAL, index;
  1814. const struct firmware *ucode_raw;
  1815. /* firmware file name contains uCode/driver compatibility version */
  1816. const char *name_pre = priv->cfg->fw_name_pre;
  1817. const unsigned int api_max = priv->cfg->ucode_api_max;
  1818. const unsigned int api_min = priv->cfg->ucode_api_min;
  1819. char buf[25];
  1820. u8 *src;
  1821. size_t len;
  1822. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1823. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1824. * request_firmware() is synchronous, file is in memory on return. */
  1825. for (index = api_max; index >= api_min; index--) {
  1826. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  1827. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1828. if (ret < 0) {
  1829. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1830. buf, ret);
  1831. if (ret == -ENOENT)
  1832. continue;
  1833. else
  1834. goto error;
  1835. } else {
  1836. if (index < api_max)
  1837. IWL_ERR(priv, "Loaded firmware %s, "
  1838. "which is deprecated. "
  1839. " Please use API v%u instead.\n",
  1840. buf, api_max);
  1841. IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
  1842. "(%zd bytes) from disk\n",
  1843. buf, ucode_raw->size);
  1844. break;
  1845. }
  1846. }
  1847. if (ret < 0)
  1848. goto error;
  1849. /* Make sure that we got at least our header! */
  1850. if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) {
  1851. IWL_ERR(priv, "File size way too small!\n");
  1852. ret = -EINVAL;
  1853. goto err_release;
  1854. }
  1855. /* Data from ucode file: header followed by uCode images */
  1856. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1857. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1858. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1859. inst_size = iwl3945_ucode_get_inst_size(ucode);
  1860. data_size = iwl3945_ucode_get_data_size(ucode);
  1861. init_size = iwl3945_ucode_get_init_size(ucode);
  1862. init_data_size = iwl3945_ucode_get_init_data_size(ucode);
  1863. boot_size = iwl3945_ucode_get_boot_size(ucode);
  1864. src = iwl3945_ucode_get_data(ucode);
  1865. /* api_ver should match the api version forming part of the
  1866. * firmware filename ... but we don't check for that and only rely
  1867. * on the API version read from firmware header from here on forward */
  1868. if (api_ver < api_min || api_ver > api_max) {
  1869. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1870. "Driver supports v%u, firmware is v%u.\n",
  1871. api_max, api_ver);
  1872. priv->ucode_ver = 0;
  1873. ret = -EINVAL;
  1874. goto err_release;
  1875. }
  1876. if (api_ver != api_max)
  1877. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  1878. "got %u. New firmware can be obtained "
  1879. "from http://www.intellinuxwireless.org.\n",
  1880. api_max, api_ver);
  1881. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1882. IWL_UCODE_MAJOR(priv->ucode_ver),
  1883. IWL_UCODE_MINOR(priv->ucode_ver),
  1884. IWL_UCODE_API(priv->ucode_ver),
  1885. IWL_UCODE_SERIAL(priv->ucode_ver));
  1886. snprintf(priv->hw->wiphy->fw_version,
  1887. sizeof(priv->hw->wiphy->fw_version),
  1888. "%u.%u.%u.%u",
  1889. IWL_UCODE_MAJOR(priv->ucode_ver),
  1890. IWL_UCODE_MINOR(priv->ucode_ver),
  1891. IWL_UCODE_API(priv->ucode_ver),
  1892. IWL_UCODE_SERIAL(priv->ucode_ver));
  1893. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1894. priv->ucode_ver);
  1895. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1896. inst_size);
  1897. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1898. data_size);
  1899. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1900. init_size);
  1901. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1902. init_data_size);
  1903. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1904. boot_size);
  1905. /* Verify size of file vs. image size info in file's header */
  1906. if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) +
  1907. inst_size + data_size + init_size +
  1908. init_data_size + boot_size) {
  1909. IWL_DEBUG_INFO(priv,
  1910. "uCode file size %zd does not match expected size\n",
  1911. ucode_raw->size);
  1912. ret = -EINVAL;
  1913. goto err_release;
  1914. }
  1915. /* Verify that uCode images will fit in card's SRAM */
  1916. if (inst_size > IWL39_MAX_INST_SIZE) {
  1917. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1918. inst_size);
  1919. ret = -EINVAL;
  1920. goto err_release;
  1921. }
  1922. if (data_size > IWL39_MAX_DATA_SIZE) {
  1923. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1924. data_size);
  1925. ret = -EINVAL;
  1926. goto err_release;
  1927. }
  1928. if (init_size > IWL39_MAX_INST_SIZE) {
  1929. IWL_DEBUG_INFO(priv,
  1930. "uCode init instr len %d too large to fit in\n",
  1931. init_size);
  1932. ret = -EINVAL;
  1933. goto err_release;
  1934. }
  1935. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  1936. IWL_DEBUG_INFO(priv,
  1937. "uCode init data len %d too large to fit in\n",
  1938. init_data_size);
  1939. ret = -EINVAL;
  1940. goto err_release;
  1941. }
  1942. if (boot_size > IWL39_MAX_BSM_SIZE) {
  1943. IWL_DEBUG_INFO(priv,
  1944. "uCode boot instr len %d too large to fit in\n",
  1945. boot_size);
  1946. ret = -EINVAL;
  1947. goto err_release;
  1948. }
  1949. /* Allocate ucode buffers for card's bus-master loading ... */
  1950. /* Runtime instructions and 2 copies of data:
  1951. * 1) unmodified from disk
  1952. * 2) backup cache for save/restore during power-downs */
  1953. priv->ucode_code.len = inst_size;
  1954. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1955. priv->ucode_data.len = data_size;
  1956. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1957. priv->ucode_data_backup.len = data_size;
  1958. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1959. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1960. !priv->ucode_data_backup.v_addr)
  1961. goto err_pci_alloc;
  1962. /* Initialization instructions and data */
  1963. if (init_size && init_data_size) {
  1964. priv->ucode_init.len = init_size;
  1965. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1966. priv->ucode_init_data.len = init_data_size;
  1967. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1968. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1969. goto err_pci_alloc;
  1970. }
  1971. /* Bootstrap (instructions only, no data) */
  1972. if (boot_size) {
  1973. priv->ucode_boot.len = boot_size;
  1974. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1975. if (!priv->ucode_boot.v_addr)
  1976. goto err_pci_alloc;
  1977. }
  1978. /* Copy images into buffers for card's bus-master reads ... */
  1979. /* Runtime instructions (first block of data in file) */
  1980. len = inst_size;
  1981. IWL_DEBUG_INFO(priv,
  1982. "Copying (but not loading) uCode instr len %zd\n", len);
  1983. memcpy(priv->ucode_code.v_addr, src, len);
  1984. src += len;
  1985. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1986. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1987. /* Runtime data (2nd block)
  1988. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  1989. len = data_size;
  1990. IWL_DEBUG_INFO(priv,
  1991. "Copying (but not loading) uCode data len %zd\n", len);
  1992. memcpy(priv->ucode_data.v_addr, src, len);
  1993. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1994. src += len;
  1995. /* Initialization instructions (3rd block) */
  1996. if (init_size) {
  1997. len = init_size;
  1998. IWL_DEBUG_INFO(priv,
  1999. "Copying (but not loading) init instr len %zd\n", len);
  2000. memcpy(priv->ucode_init.v_addr, src, len);
  2001. src += len;
  2002. }
  2003. /* Initialization data (4th block) */
  2004. if (init_data_size) {
  2005. len = init_data_size;
  2006. IWL_DEBUG_INFO(priv,
  2007. "Copying (but not loading) init data len %zd\n", len);
  2008. memcpy(priv->ucode_init_data.v_addr, src, len);
  2009. src += len;
  2010. }
  2011. /* Bootstrap instructions (5th block) */
  2012. len = boot_size;
  2013. IWL_DEBUG_INFO(priv,
  2014. "Copying (but not loading) boot instr len %zd\n", len);
  2015. memcpy(priv->ucode_boot.v_addr, src, len);
  2016. /* We have our copies now, allow OS release its copies */
  2017. release_firmware(ucode_raw);
  2018. return 0;
  2019. err_pci_alloc:
  2020. IWL_ERR(priv, "failed to allocate pci memory\n");
  2021. ret = -ENOMEM;
  2022. iwl3945_dealloc_ucode_pci(priv);
  2023. err_release:
  2024. release_firmware(ucode_raw);
  2025. error:
  2026. return ret;
  2027. }
  2028. /**
  2029. * iwl3945_set_ucode_ptrs - Set uCode address location
  2030. *
  2031. * Tell initialization uCode where to find runtime uCode.
  2032. *
  2033. * BSM registers initially contain pointers to initialization uCode.
  2034. * We need to replace them to load runtime uCode inst and data,
  2035. * and to save runtime data when powering down.
  2036. */
  2037. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  2038. {
  2039. dma_addr_t pinst;
  2040. dma_addr_t pdata;
  2041. /* bits 31:0 for 3945 */
  2042. pinst = priv->ucode_code.p_addr;
  2043. pdata = priv->ucode_data_backup.p_addr;
  2044. /* Tell bootstrap uCode where to find image to load */
  2045. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  2046. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  2047. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  2048. priv->ucode_data.len);
  2049. /* Inst byte count must be last to set up, bit 31 signals uCode
  2050. * that all new ptr/size info is in place */
  2051. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  2052. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  2053. IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
  2054. return 0;
  2055. }
  2056. /**
  2057. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  2058. *
  2059. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  2060. *
  2061. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  2062. */
  2063. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  2064. {
  2065. /* Check alive response for "valid" sign from uCode */
  2066. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  2067. /* We had an error bringing up the hardware, so take it
  2068. * all the way back down so we can try again */
  2069. IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
  2070. goto restart;
  2071. }
  2072. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  2073. * This is a paranoid check, because we would not have gotten the
  2074. * "initialize" alive if code weren't properly loaded. */
  2075. if (iwl3945_verify_ucode(priv)) {
  2076. /* Runtime instruction load was bad;
  2077. * take it all the way back down so we can try again */
  2078. IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
  2079. goto restart;
  2080. }
  2081. /* Send pointers to protocol/runtime uCode image ... init code will
  2082. * load and launch runtime uCode, which will send us another "Alive"
  2083. * notification. */
  2084. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  2085. if (iwl3945_set_ucode_ptrs(priv)) {
  2086. /* Runtime instruction load won't happen;
  2087. * take it all the way back down so we can try again */
  2088. IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
  2089. goto restart;
  2090. }
  2091. return;
  2092. restart:
  2093. queue_work(priv->workqueue, &priv->restart);
  2094. }
  2095. /**
  2096. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  2097. * from protocol/runtime uCode (initialization uCode's
  2098. * Alive gets handled by iwl3945_init_alive_start()).
  2099. */
  2100. static void iwl3945_alive_start(struct iwl_priv *priv)
  2101. {
  2102. int thermal_spin = 0;
  2103. u32 rfkill;
  2104. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2105. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2106. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2107. /* We had an error bringing up the hardware, so take it
  2108. * all the way back down so we can try again */
  2109. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2110. goto restart;
  2111. }
  2112. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2113. * This is a paranoid check, because we would not have gotten the
  2114. * "runtime" alive if code weren't properly loaded. */
  2115. if (iwl3945_verify_ucode(priv)) {
  2116. /* Runtime instruction load was bad;
  2117. * take it all the way back down so we can try again */
  2118. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2119. goto restart;
  2120. }
  2121. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  2122. IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
  2123. if (rfkill & 0x1) {
  2124. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2125. /* if RFKILL is not on, then wait for thermal
  2126. * sensor in adapter to kick in */
  2127. while (iwl3945_hw_get_temperature(priv) == 0) {
  2128. thermal_spin++;
  2129. udelay(10);
  2130. }
  2131. if (thermal_spin)
  2132. IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
  2133. thermal_spin * 10);
  2134. } else
  2135. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2136. /* After the ALIVE response, we can send commands to 3945 uCode */
  2137. set_bit(STATUS_ALIVE, &priv->status);
  2138. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2139. /* Enable timer to monitor the driver queues */
  2140. mod_timer(&priv->monitor_recover,
  2141. jiffies +
  2142. msecs_to_jiffies(
  2143. priv->cfg->base_params->monitor_recover_period));
  2144. }
  2145. if (iwl_is_rfkill(priv))
  2146. return;
  2147. ieee80211_wake_queues(priv->hw);
  2148. priv->active_rate = IWL_RATES_MASK;
  2149. iwl_power_update_mode(priv, true);
  2150. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2151. struct iwl3945_rxon_cmd *active_rxon =
  2152. (struct iwl3945_rxon_cmd *)(&ctx->active);
  2153. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2154. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2155. } else {
  2156. /* Initialize our rx_config data */
  2157. iwl_connection_init_rx_config(priv, ctx);
  2158. }
  2159. /* Configure Bluetooth device coexistence support */
  2160. priv->cfg->ops->hcmd->send_bt_config(priv);
  2161. /* Configure the adapter for unassociated operation */
  2162. iwl3945_commit_rxon(priv, ctx);
  2163. iwl3945_reg_txpower_periodic(priv);
  2164. iwl_leds_init(priv);
  2165. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2166. set_bit(STATUS_READY, &priv->status);
  2167. wake_up_interruptible(&priv->wait_command_queue);
  2168. return;
  2169. restart:
  2170. queue_work(priv->workqueue, &priv->restart);
  2171. }
  2172. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  2173. static void __iwl3945_down(struct iwl_priv *priv)
  2174. {
  2175. unsigned long flags;
  2176. int exit_pending;
  2177. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2178. iwl_scan_cancel_timeout(priv, 200);
  2179. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
  2180. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  2181. * to prevent rearm timer */
  2182. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2183. del_timer_sync(&priv->monitor_recover);
  2184. /* Station information will now be cleared in device */
  2185. iwl_clear_ucode_stations(priv, NULL);
  2186. iwl_dealloc_bcast_stations(priv);
  2187. iwl_clear_driver_stations(priv);
  2188. /* Unblock any waiting calls */
  2189. wake_up_interruptible_all(&priv->wait_command_queue);
  2190. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2191. * exiting the module */
  2192. if (!exit_pending)
  2193. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2194. /* stop and reset the on-board processor */
  2195. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2196. /* tell the device to stop sending interrupts */
  2197. spin_lock_irqsave(&priv->lock, flags);
  2198. iwl_disable_interrupts(priv);
  2199. spin_unlock_irqrestore(&priv->lock, flags);
  2200. iwl_synchronize_irq(priv);
  2201. if (priv->mac80211_registered)
  2202. ieee80211_stop_queues(priv->hw);
  2203. /* If we have not previously called iwl3945_init() then
  2204. * clear all bits but the RF Kill bits and return */
  2205. if (!iwl_is_init(priv)) {
  2206. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2207. STATUS_RF_KILL_HW |
  2208. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2209. STATUS_GEO_CONFIGURED |
  2210. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2211. STATUS_EXIT_PENDING;
  2212. goto exit;
  2213. }
  2214. /* ...otherwise clear out all the status bits but the RF Kill
  2215. * bit and continue taking the NIC down. */
  2216. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2217. STATUS_RF_KILL_HW |
  2218. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2219. STATUS_GEO_CONFIGURED |
  2220. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2221. STATUS_FW_ERROR |
  2222. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2223. STATUS_EXIT_PENDING;
  2224. iwl3945_hw_txq_ctx_stop(priv);
  2225. iwl3945_hw_rxq_stop(priv);
  2226. /* Power-down device's busmaster DMA clocks */
  2227. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2228. udelay(5);
  2229. /* Stop the device, and put it in low power state */
  2230. iwl_apm_stop(priv);
  2231. exit:
  2232. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2233. if (priv->beacon_skb)
  2234. dev_kfree_skb(priv->beacon_skb);
  2235. priv->beacon_skb = NULL;
  2236. /* clear out any free frames */
  2237. iwl3945_clear_free_frames(priv);
  2238. }
  2239. static void iwl3945_down(struct iwl_priv *priv)
  2240. {
  2241. mutex_lock(&priv->mutex);
  2242. __iwl3945_down(priv);
  2243. mutex_unlock(&priv->mutex);
  2244. iwl3945_cancel_deferred_work(priv);
  2245. }
  2246. #define MAX_HW_RESTARTS 5
  2247. static int iwl3945_alloc_bcast_station(struct iwl_priv *priv)
  2248. {
  2249. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2250. unsigned long flags;
  2251. u8 sta_id;
  2252. spin_lock_irqsave(&priv->sta_lock, flags);
  2253. sta_id = iwl_prep_station(priv, ctx, iwl_bcast_addr, false, NULL);
  2254. if (sta_id == IWL_INVALID_STATION) {
  2255. IWL_ERR(priv, "Unable to prepare broadcast station\n");
  2256. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2257. return -EINVAL;
  2258. }
  2259. priv->stations[sta_id].used |= IWL_STA_DRIVER_ACTIVE;
  2260. priv->stations[sta_id].used |= IWL_STA_BCAST;
  2261. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2262. return 0;
  2263. }
  2264. static int __iwl3945_up(struct iwl_priv *priv)
  2265. {
  2266. int rc, i;
  2267. rc = iwl3945_alloc_bcast_station(priv);
  2268. if (rc)
  2269. return rc;
  2270. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2271. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2272. return -EIO;
  2273. }
  2274. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2275. IWL_ERR(priv, "ucode not available for device bring up\n");
  2276. return -EIO;
  2277. }
  2278. /* If platform's RF_KILL switch is NOT set to KILL */
  2279. if (iwl_read32(priv, CSR_GP_CNTRL) &
  2280. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2281. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2282. else {
  2283. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2284. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2285. return -ENODEV;
  2286. }
  2287. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2288. rc = iwl3945_hw_nic_init(priv);
  2289. if (rc) {
  2290. IWL_ERR(priv, "Unable to int nic\n");
  2291. return rc;
  2292. }
  2293. /* make sure rfkill handshake bits are cleared */
  2294. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2295. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2296. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2297. /* clear (again), then enable host interrupts */
  2298. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2299. iwl_enable_interrupts(priv);
  2300. /* really make sure rfkill handshake bits are cleared */
  2301. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2302. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2303. /* Copy original ucode data image from disk into backup cache.
  2304. * This will be used to initialize the on-board processor's
  2305. * data SRAM for a clean start when the runtime program first loads. */
  2306. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2307. priv->ucode_data.len);
  2308. /* We return success when we resume from suspend and rf_kill is on. */
  2309. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  2310. return 0;
  2311. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2312. /* load bootstrap state machine,
  2313. * load bootstrap program into processor's memory,
  2314. * prepare to load the "initialize" uCode */
  2315. rc = priv->cfg->ops->lib->load_ucode(priv);
  2316. if (rc) {
  2317. IWL_ERR(priv,
  2318. "Unable to set up bootstrap uCode: %d\n", rc);
  2319. continue;
  2320. }
  2321. /* start card; "initialize" will load runtime ucode */
  2322. iwl3945_nic_start(priv);
  2323. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2324. return 0;
  2325. }
  2326. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2327. __iwl3945_down(priv);
  2328. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2329. /* tried to restart and config the device for as long as our
  2330. * patience could withstand */
  2331. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2332. return -EIO;
  2333. }
  2334. /*****************************************************************************
  2335. *
  2336. * Workqueue callbacks
  2337. *
  2338. *****************************************************************************/
  2339. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  2340. {
  2341. struct iwl_priv *priv =
  2342. container_of(data, struct iwl_priv, init_alive_start.work);
  2343. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2344. return;
  2345. mutex_lock(&priv->mutex);
  2346. iwl3945_init_alive_start(priv);
  2347. mutex_unlock(&priv->mutex);
  2348. }
  2349. static void iwl3945_bg_alive_start(struct work_struct *data)
  2350. {
  2351. struct iwl_priv *priv =
  2352. container_of(data, struct iwl_priv, alive_start.work);
  2353. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2354. return;
  2355. mutex_lock(&priv->mutex);
  2356. iwl3945_alive_start(priv);
  2357. mutex_unlock(&priv->mutex);
  2358. }
  2359. /*
  2360. * 3945 cannot interrupt driver when hardware rf kill switch toggles;
  2361. * driver must poll CSR_GP_CNTRL_REG register for change. This register
  2362. * *is* readable even when device has been SW_RESET into low power mode
  2363. * (e.g. during RF KILL).
  2364. */
  2365. static void iwl3945_rfkill_poll(struct work_struct *data)
  2366. {
  2367. struct iwl_priv *priv =
  2368. container_of(data, struct iwl_priv, _3945.rfkill_poll.work);
  2369. bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
  2370. bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
  2371. & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
  2372. if (new_rfkill != old_rfkill) {
  2373. if (new_rfkill)
  2374. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2375. else
  2376. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2377. wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
  2378. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  2379. new_rfkill ? "disable radio" : "enable radio");
  2380. }
  2381. /* Keep this running, even if radio now enabled. This will be
  2382. * cancelled in mac_start() if system decides to start again */
  2383. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2384. round_jiffies_relative(2 * HZ));
  2385. }
  2386. int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2387. {
  2388. struct iwl_host_cmd cmd = {
  2389. .id = REPLY_SCAN_CMD,
  2390. .len = sizeof(struct iwl3945_scan_cmd),
  2391. .flags = CMD_SIZE_HUGE,
  2392. };
  2393. struct iwl3945_scan_cmd *scan;
  2394. u8 n_probes = 0;
  2395. enum ieee80211_band band;
  2396. bool is_active = false;
  2397. int ret;
  2398. lockdep_assert_held(&priv->mutex);
  2399. if (!priv->scan_cmd) {
  2400. priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  2401. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  2402. if (!priv->scan_cmd) {
  2403. IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n");
  2404. return -ENOMEM;
  2405. }
  2406. }
  2407. scan = priv->scan_cmd;
  2408. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  2409. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  2410. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  2411. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2412. u16 interval = 0;
  2413. u32 extra;
  2414. u32 suspend_time = 100;
  2415. u32 scan_suspend_time = 100;
  2416. unsigned long flags;
  2417. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  2418. spin_lock_irqsave(&priv->lock, flags);
  2419. if (priv->is_internal_short_scan)
  2420. interval = 0;
  2421. else
  2422. interval = vif->bss_conf.beacon_int;
  2423. spin_unlock_irqrestore(&priv->lock, flags);
  2424. scan->suspend_time = 0;
  2425. scan->max_out_time = cpu_to_le32(200 * 1024);
  2426. if (!interval)
  2427. interval = suspend_time;
  2428. /*
  2429. * suspend time format:
  2430. * 0-19: beacon interval in usec (time before exec.)
  2431. * 20-23: 0
  2432. * 24-31: number of beacons (suspend between channels)
  2433. */
  2434. extra = (suspend_time / interval) << 24;
  2435. scan_suspend_time = 0xFF0FFFFF &
  2436. (extra | ((suspend_time % interval) * 1024));
  2437. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  2438. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  2439. scan_suspend_time, interval);
  2440. }
  2441. if (priv->is_internal_short_scan) {
  2442. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  2443. } else if (priv->scan_request->n_ssids) {
  2444. int i, p = 0;
  2445. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  2446. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  2447. /* always does wildcard anyway */
  2448. if (!priv->scan_request->ssids[i].ssid_len)
  2449. continue;
  2450. scan->direct_scan[p].id = WLAN_EID_SSID;
  2451. scan->direct_scan[p].len =
  2452. priv->scan_request->ssids[i].ssid_len;
  2453. memcpy(scan->direct_scan[p].ssid,
  2454. priv->scan_request->ssids[i].ssid,
  2455. priv->scan_request->ssids[i].ssid_len);
  2456. n_probes++;
  2457. p++;
  2458. }
  2459. is_active = true;
  2460. } else
  2461. IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
  2462. /* We don't build a direct scan probe request; the uCode will do
  2463. * that based on the direct_mask added to each channel entry */
  2464. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  2465. scan->tx_cmd.sta_id = priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
  2466. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2467. /* flags + rate selection */
  2468. switch (priv->scan_band) {
  2469. case IEEE80211_BAND_2GHZ:
  2470. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  2471. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  2472. band = IEEE80211_BAND_2GHZ;
  2473. break;
  2474. case IEEE80211_BAND_5GHZ:
  2475. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  2476. band = IEEE80211_BAND_5GHZ;
  2477. break;
  2478. default:
  2479. IWL_WARN(priv, "Invalid scan band\n");
  2480. return -EIO;
  2481. }
  2482. /*
  2483. * If active scaning is requested but a certain channel
  2484. * is marked passive, we can do active scanning if we
  2485. * detect transmissions.
  2486. */
  2487. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  2488. IWL_GOOD_CRC_TH_DISABLED;
  2489. if (!priv->is_internal_short_scan) {
  2490. scan->tx_cmd.len = cpu_to_le16(
  2491. iwl_fill_probe_req(priv,
  2492. (struct ieee80211_mgmt *)scan->data,
  2493. vif->addr,
  2494. priv->scan_request->ie,
  2495. priv->scan_request->ie_len,
  2496. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2497. } else {
  2498. /* use bcast addr, will not be transmitted but must be valid */
  2499. scan->tx_cmd.len = cpu_to_le16(
  2500. iwl_fill_probe_req(priv,
  2501. (struct ieee80211_mgmt *)scan->data,
  2502. iwl_bcast_addr, NULL, 0,
  2503. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2504. }
  2505. /* select Rx antennas */
  2506. scan->flags |= iwl3945_get_antenna_flags(priv);
  2507. if (priv->is_internal_short_scan) {
  2508. scan->channel_count =
  2509. iwl3945_get_single_channel_for_scan(priv, vif, band,
  2510. (void *)&scan->data[le16_to_cpu(
  2511. scan->tx_cmd.len)]);
  2512. } else {
  2513. scan->channel_count =
  2514. iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
  2515. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif);
  2516. }
  2517. if (scan->channel_count == 0) {
  2518. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  2519. return -EIO;
  2520. }
  2521. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  2522. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  2523. cmd.data = scan;
  2524. scan->len = cpu_to_le16(cmd.len);
  2525. set_bit(STATUS_SCAN_HW, &priv->status);
  2526. ret = iwl_send_cmd_sync(priv, &cmd);
  2527. if (ret)
  2528. clear_bit(STATUS_SCAN_HW, &priv->status);
  2529. return ret;
  2530. }
  2531. void iwl3945_post_scan(struct iwl_priv *priv)
  2532. {
  2533. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2534. /*
  2535. * Since setting the RXON may have been deferred while
  2536. * performing the scan, fire one off if needed
  2537. */
  2538. if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
  2539. iwl3945_commit_rxon(priv, ctx);
  2540. }
  2541. static void iwl3945_bg_restart(struct work_struct *data)
  2542. {
  2543. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2544. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2545. return;
  2546. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2547. struct iwl_rxon_context *ctx;
  2548. mutex_lock(&priv->mutex);
  2549. for_each_context(priv, ctx)
  2550. ctx->vif = NULL;
  2551. priv->is_open = 0;
  2552. mutex_unlock(&priv->mutex);
  2553. iwl3945_down(priv);
  2554. ieee80211_restart_hw(priv->hw);
  2555. } else {
  2556. iwl3945_down(priv);
  2557. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2558. return;
  2559. mutex_lock(&priv->mutex);
  2560. __iwl3945_up(priv);
  2561. mutex_unlock(&priv->mutex);
  2562. }
  2563. }
  2564. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  2565. {
  2566. struct iwl_priv *priv =
  2567. container_of(data, struct iwl_priv, rx_replenish);
  2568. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2569. return;
  2570. mutex_lock(&priv->mutex);
  2571. iwl3945_rx_replenish(priv);
  2572. mutex_unlock(&priv->mutex);
  2573. }
  2574. void iwl3945_post_associate(struct iwl_priv *priv)
  2575. {
  2576. int rc = 0;
  2577. struct ieee80211_conf *conf = NULL;
  2578. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2579. if (!ctx->vif || !priv->is_open)
  2580. return;
  2581. if (ctx->vif->type == NL80211_IFTYPE_AP) {
  2582. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2583. return;
  2584. }
  2585. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2586. ctx->vif->bss_conf.aid, ctx->active.bssid_addr);
  2587. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2588. return;
  2589. iwl_scan_cancel_timeout(priv, 200);
  2590. conf = ieee80211_get_hw_conf(priv->hw);
  2591. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2592. iwl3945_commit_rxon(priv, ctx);
  2593. rc = iwl_send_rxon_timing(priv, ctx);
  2594. if (rc)
  2595. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2596. "Attempting to continue.\n");
  2597. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2598. ctx->staging.assoc_id = cpu_to_le16(ctx->vif->bss_conf.aid);
  2599. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2600. ctx->vif->bss_conf.aid, ctx->vif->bss_conf.beacon_int);
  2601. if (ctx->vif->bss_conf.use_short_preamble)
  2602. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2603. else
  2604. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2605. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2606. if (ctx->vif->bss_conf.use_short_slot)
  2607. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2608. else
  2609. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2610. }
  2611. iwl3945_commit_rxon(priv, ctx);
  2612. switch (ctx->vif->type) {
  2613. case NL80211_IFTYPE_STATION:
  2614. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  2615. break;
  2616. case NL80211_IFTYPE_ADHOC:
  2617. iwl3945_send_beacon_cmd(priv);
  2618. break;
  2619. default:
  2620. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2621. __func__, ctx->vif->type);
  2622. break;
  2623. }
  2624. }
  2625. /*****************************************************************************
  2626. *
  2627. * mac80211 entry point functions
  2628. *
  2629. *****************************************************************************/
  2630. #define UCODE_READY_TIMEOUT (2 * HZ)
  2631. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  2632. {
  2633. struct iwl_priv *priv = hw->priv;
  2634. int ret;
  2635. IWL_DEBUG_MAC80211(priv, "enter\n");
  2636. /* we should be verifying the device is ready to be opened */
  2637. mutex_lock(&priv->mutex);
  2638. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2639. * ucode filename and max sizes are card-specific. */
  2640. if (!priv->ucode_code.len) {
  2641. ret = iwl3945_read_ucode(priv);
  2642. if (ret) {
  2643. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2644. mutex_unlock(&priv->mutex);
  2645. goto out_release_irq;
  2646. }
  2647. }
  2648. ret = __iwl3945_up(priv);
  2649. mutex_unlock(&priv->mutex);
  2650. if (ret)
  2651. goto out_release_irq;
  2652. IWL_DEBUG_INFO(priv, "Start UP work.\n");
  2653. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  2654. * mac80211 will not be run successfully. */
  2655. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2656. test_bit(STATUS_READY, &priv->status),
  2657. UCODE_READY_TIMEOUT);
  2658. if (!ret) {
  2659. if (!test_bit(STATUS_READY, &priv->status)) {
  2660. IWL_ERR(priv,
  2661. "Wait for START_ALIVE timeout after %dms.\n",
  2662. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2663. ret = -ETIMEDOUT;
  2664. goto out_release_irq;
  2665. }
  2666. }
  2667. /* ucode is running and will send rfkill notifications,
  2668. * no need to poll the killswitch state anymore */
  2669. cancel_delayed_work(&priv->_3945.rfkill_poll);
  2670. iwl_led_start(priv);
  2671. priv->is_open = 1;
  2672. IWL_DEBUG_MAC80211(priv, "leave\n");
  2673. return 0;
  2674. out_release_irq:
  2675. priv->is_open = 0;
  2676. IWL_DEBUG_MAC80211(priv, "leave - failed\n");
  2677. return ret;
  2678. }
  2679. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  2680. {
  2681. struct iwl_priv *priv = hw->priv;
  2682. IWL_DEBUG_MAC80211(priv, "enter\n");
  2683. if (!priv->is_open) {
  2684. IWL_DEBUG_MAC80211(priv, "leave - skip\n");
  2685. return;
  2686. }
  2687. priv->is_open = 0;
  2688. iwl3945_down(priv);
  2689. flush_workqueue(priv->workqueue);
  2690. /* start polling the killswitch state again */
  2691. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2692. round_jiffies_relative(2 * HZ));
  2693. IWL_DEBUG_MAC80211(priv, "leave\n");
  2694. }
  2695. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2696. {
  2697. struct iwl_priv *priv = hw->priv;
  2698. IWL_DEBUG_MAC80211(priv, "enter\n");
  2699. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2700. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2701. if (iwl3945_tx_skb(priv, skb))
  2702. dev_kfree_skb_any(skb);
  2703. IWL_DEBUG_MAC80211(priv, "leave\n");
  2704. return NETDEV_TX_OK;
  2705. }
  2706. void iwl3945_config_ap(struct iwl_priv *priv)
  2707. {
  2708. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2709. struct ieee80211_vif *vif = ctx->vif;
  2710. int rc = 0;
  2711. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2712. return;
  2713. /* The following should be done only at AP bring up */
  2714. if (!(iwl_is_associated(priv, IWL_RXON_CTX_BSS))) {
  2715. /* RXON - unassoc (to set timing command) */
  2716. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2717. iwl3945_commit_rxon(priv, ctx);
  2718. /* RXON Timing */
  2719. rc = iwl_send_rxon_timing(priv, ctx);
  2720. if (rc)
  2721. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2722. "Attempting to continue.\n");
  2723. ctx->staging.assoc_id = 0;
  2724. if (vif->bss_conf.use_short_preamble)
  2725. ctx->staging.flags |=
  2726. RXON_FLG_SHORT_PREAMBLE_MSK;
  2727. else
  2728. ctx->staging.flags &=
  2729. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2730. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2731. if (vif->bss_conf.use_short_slot)
  2732. ctx->staging.flags |=
  2733. RXON_FLG_SHORT_SLOT_MSK;
  2734. else
  2735. ctx->staging.flags &=
  2736. ~RXON_FLG_SHORT_SLOT_MSK;
  2737. }
  2738. /* restore RXON assoc */
  2739. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2740. iwl3945_commit_rxon(priv, ctx);
  2741. }
  2742. iwl3945_send_beacon_cmd(priv);
  2743. /* FIXME - we need to add code here to detect a totally new
  2744. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2745. * clear sta table, add BCAST sta... */
  2746. }
  2747. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2748. struct ieee80211_vif *vif,
  2749. struct ieee80211_sta *sta,
  2750. struct ieee80211_key_conf *key)
  2751. {
  2752. struct iwl_priv *priv = hw->priv;
  2753. int ret = 0;
  2754. u8 sta_id = IWL_INVALID_STATION;
  2755. u8 static_key;
  2756. IWL_DEBUG_MAC80211(priv, "enter\n");
  2757. if (iwl3945_mod_params.sw_crypto) {
  2758. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2759. return -EOPNOTSUPP;
  2760. }
  2761. static_key = !iwl_is_associated(priv, IWL_RXON_CTX_BSS);
  2762. if (!static_key) {
  2763. sta_id = iwl_sta_id_or_broadcast(
  2764. priv, &priv->contexts[IWL_RXON_CTX_BSS], sta);
  2765. if (sta_id == IWL_INVALID_STATION)
  2766. return -EINVAL;
  2767. }
  2768. mutex_lock(&priv->mutex);
  2769. iwl_scan_cancel_timeout(priv, 100);
  2770. switch (cmd) {
  2771. case SET_KEY:
  2772. if (static_key)
  2773. ret = iwl3945_set_static_key(priv, key);
  2774. else
  2775. ret = iwl3945_set_dynamic_key(priv, key, sta_id);
  2776. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2777. break;
  2778. case DISABLE_KEY:
  2779. if (static_key)
  2780. ret = iwl3945_remove_static_key(priv);
  2781. else
  2782. ret = iwl3945_clear_sta_key_info(priv, sta_id);
  2783. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2784. break;
  2785. default:
  2786. ret = -EINVAL;
  2787. }
  2788. mutex_unlock(&priv->mutex);
  2789. IWL_DEBUG_MAC80211(priv, "leave\n");
  2790. return ret;
  2791. }
  2792. static int iwl3945_mac_sta_add(struct ieee80211_hw *hw,
  2793. struct ieee80211_vif *vif,
  2794. struct ieee80211_sta *sta)
  2795. {
  2796. struct iwl_priv *priv = hw->priv;
  2797. struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv;
  2798. int ret;
  2799. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2800. u8 sta_id;
  2801. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2802. sta->addr);
  2803. mutex_lock(&priv->mutex);
  2804. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2805. sta->addr);
  2806. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2807. ret = iwl_add_station_common(priv, &priv->contexts[IWL_RXON_CTX_BSS],
  2808. sta->addr, is_ap, sta, &sta_id);
  2809. if (ret) {
  2810. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2811. sta->addr, ret);
  2812. /* Should we return success if return code is EEXIST ? */
  2813. mutex_unlock(&priv->mutex);
  2814. return ret;
  2815. }
  2816. sta_priv->common.sta_id = sta_id;
  2817. /* Initialize rate scaling */
  2818. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2819. sta->addr);
  2820. iwl3945_rs_rate_init(priv, sta, sta_id);
  2821. mutex_unlock(&priv->mutex);
  2822. return 0;
  2823. }
  2824. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  2825. unsigned int changed_flags,
  2826. unsigned int *total_flags,
  2827. u64 multicast)
  2828. {
  2829. struct iwl_priv *priv = hw->priv;
  2830. __le32 filter_or = 0, filter_nand = 0;
  2831. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2832. #define CHK(test, flag) do { \
  2833. if (*total_flags & (test)) \
  2834. filter_or |= (flag); \
  2835. else \
  2836. filter_nand |= (flag); \
  2837. } while (0)
  2838. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2839. changed_flags, *total_flags);
  2840. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2841. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  2842. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2843. #undef CHK
  2844. mutex_lock(&priv->mutex);
  2845. ctx->staging.filter_flags &= ~filter_nand;
  2846. ctx->staging.filter_flags |= filter_or;
  2847. /*
  2848. * Not committing directly because hardware can perform a scan,
  2849. * but even if hw is ready, committing here breaks for some reason,
  2850. * we'll eventually commit the filter flags change anyway.
  2851. */
  2852. mutex_unlock(&priv->mutex);
  2853. /*
  2854. * Receiving all multicast frames is always enabled by the
  2855. * default flags setup in iwl_connection_init_rx_config()
  2856. * since we currently do not support programming multicast
  2857. * filters into the device.
  2858. */
  2859. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2860. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2861. }
  2862. /*****************************************************************************
  2863. *
  2864. * sysfs attributes
  2865. *
  2866. *****************************************************************************/
  2867. #ifdef CONFIG_IWLWIFI_DEBUG
  2868. /*
  2869. * The following adds a new attribute to the sysfs representation
  2870. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  2871. * used for controlling the debug level.
  2872. *
  2873. * See the level definitions in iwl for details.
  2874. *
  2875. * The debug_level being managed using sysfs below is a per device debug
  2876. * level that is used instead of the global debug level if it (the per
  2877. * device debug level) is set.
  2878. */
  2879. static ssize_t show_debug_level(struct device *d,
  2880. struct device_attribute *attr, char *buf)
  2881. {
  2882. struct iwl_priv *priv = dev_get_drvdata(d);
  2883. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2884. }
  2885. static ssize_t store_debug_level(struct device *d,
  2886. struct device_attribute *attr,
  2887. const char *buf, size_t count)
  2888. {
  2889. struct iwl_priv *priv = dev_get_drvdata(d);
  2890. unsigned long val;
  2891. int ret;
  2892. ret = strict_strtoul(buf, 0, &val);
  2893. if (ret)
  2894. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  2895. else {
  2896. priv->debug_level = val;
  2897. if (iwl_alloc_traffic_mem(priv))
  2898. IWL_ERR(priv,
  2899. "Not enough memory to generate traffic log\n");
  2900. }
  2901. return strnlen(buf, count);
  2902. }
  2903. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2904. show_debug_level, store_debug_level);
  2905. #endif /* CONFIG_IWLWIFI_DEBUG */
  2906. static ssize_t show_temperature(struct device *d,
  2907. struct device_attribute *attr, char *buf)
  2908. {
  2909. struct iwl_priv *priv = dev_get_drvdata(d);
  2910. if (!iwl_is_alive(priv))
  2911. return -EAGAIN;
  2912. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  2913. }
  2914. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2915. static ssize_t show_tx_power(struct device *d,
  2916. struct device_attribute *attr, char *buf)
  2917. {
  2918. struct iwl_priv *priv = dev_get_drvdata(d);
  2919. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2920. }
  2921. static ssize_t store_tx_power(struct device *d,
  2922. struct device_attribute *attr,
  2923. const char *buf, size_t count)
  2924. {
  2925. struct iwl_priv *priv = dev_get_drvdata(d);
  2926. char *p = (char *)buf;
  2927. u32 val;
  2928. val = simple_strtoul(p, &p, 10);
  2929. if (p == buf)
  2930. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  2931. else
  2932. iwl3945_hw_reg_set_txpower(priv, val);
  2933. return count;
  2934. }
  2935. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2936. static ssize_t show_flags(struct device *d,
  2937. struct device_attribute *attr, char *buf)
  2938. {
  2939. struct iwl_priv *priv = dev_get_drvdata(d);
  2940. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2941. return sprintf(buf, "0x%04X\n", ctx->active.flags);
  2942. }
  2943. static ssize_t store_flags(struct device *d,
  2944. struct device_attribute *attr,
  2945. const char *buf, size_t count)
  2946. {
  2947. struct iwl_priv *priv = dev_get_drvdata(d);
  2948. u32 flags = simple_strtoul(buf, NULL, 0);
  2949. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2950. mutex_lock(&priv->mutex);
  2951. if (le32_to_cpu(ctx->staging.flags) != flags) {
  2952. /* Cancel any currently running scans... */
  2953. if (iwl_scan_cancel_timeout(priv, 100))
  2954. IWL_WARN(priv, "Could not cancel scan.\n");
  2955. else {
  2956. IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
  2957. flags);
  2958. ctx->staging.flags = cpu_to_le32(flags);
  2959. iwl3945_commit_rxon(priv, ctx);
  2960. }
  2961. }
  2962. mutex_unlock(&priv->mutex);
  2963. return count;
  2964. }
  2965. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2966. static ssize_t show_filter_flags(struct device *d,
  2967. struct device_attribute *attr, char *buf)
  2968. {
  2969. struct iwl_priv *priv = dev_get_drvdata(d);
  2970. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2971. return sprintf(buf, "0x%04X\n",
  2972. le32_to_cpu(ctx->active.filter_flags));
  2973. }
  2974. static ssize_t store_filter_flags(struct device *d,
  2975. struct device_attribute *attr,
  2976. const char *buf, size_t count)
  2977. {
  2978. struct iwl_priv *priv = dev_get_drvdata(d);
  2979. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2980. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  2981. mutex_lock(&priv->mutex);
  2982. if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
  2983. /* Cancel any currently running scans... */
  2984. if (iwl_scan_cancel_timeout(priv, 100))
  2985. IWL_WARN(priv, "Could not cancel scan.\n");
  2986. else {
  2987. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2988. "0x%04X\n", filter_flags);
  2989. ctx->staging.filter_flags =
  2990. cpu_to_le32(filter_flags);
  2991. iwl3945_commit_rxon(priv, ctx);
  2992. }
  2993. }
  2994. mutex_unlock(&priv->mutex);
  2995. return count;
  2996. }
  2997. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2998. store_filter_flags);
  2999. static ssize_t show_measurement(struct device *d,
  3000. struct device_attribute *attr, char *buf)
  3001. {
  3002. struct iwl_priv *priv = dev_get_drvdata(d);
  3003. struct iwl_spectrum_notification measure_report;
  3004. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  3005. u8 *data = (u8 *)&measure_report;
  3006. unsigned long flags;
  3007. spin_lock_irqsave(&priv->lock, flags);
  3008. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  3009. spin_unlock_irqrestore(&priv->lock, flags);
  3010. return 0;
  3011. }
  3012. memcpy(&measure_report, &priv->measure_report, size);
  3013. priv->measurement_status = 0;
  3014. spin_unlock_irqrestore(&priv->lock, flags);
  3015. while (size && (PAGE_SIZE - len)) {
  3016. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  3017. PAGE_SIZE - len, 1);
  3018. len = strlen(buf);
  3019. if (PAGE_SIZE - len)
  3020. buf[len++] = '\n';
  3021. ofs += 16;
  3022. size -= min(size, 16U);
  3023. }
  3024. return len;
  3025. }
  3026. static ssize_t store_measurement(struct device *d,
  3027. struct device_attribute *attr,
  3028. const char *buf, size_t count)
  3029. {
  3030. struct iwl_priv *priv = dev_get_drvdata(d);
  3031. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  3032. struct ieee80211_measurement_params params = {
  3033. .channel = le16_to_cpu(ctx->active.channel),
  3034. .start_time = cpu_to_le64(priv->_3945.last_tsf),
  3035. .duration = cpu_to_le16(1),
  3036. };
  3037. u8 type = IWL_MEASURE_BASIC;
  3038. u8 buffer[32];
  3039. u8 channel;
  3040. if (count) {
  3041. char *p = buffer;
  3042. strncpy(buffer, buf, min(sizeof(buffer), count));
  3043. channel = simple_strtoul(p, NULL, 0);
  3044. if (channel)
  3045. params.channel = channel;
  3046. p = buffer;
  3047. while (*p && *p != ' ')
  3048. p++;
  3049. if (*p)
  3050. type = simple_strtoul(p + 1, NULL, 0);
  3051. }
  3052. IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
  3053. "channel %d (for '%s')\n", type, params.channel, buf);
  3054. iwl3945_get_measurement(priv, &params, type);
  3055. return count;
  3056. }
  3057. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  3058. show_measurement, store_measurement);
  3059. static ssize_t store_retry_rate(struct device *d,
  3060. struct device_attribute *attr,
  3061. const char *buf, size_t count)
  3062. {
  3063. struct iwl_priv *priv = dev_get_drvdata(d);
  3064. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  3065. if (priv->retry_rate <= 0)
  3066. priv->retry_rate = 1;
  3067. return count;
  3068. }
  3069. static ssize_t show_retry_rate(struct device *d,
  3070. struct device_attribute *attr, char *buf)
  3071. {
  3072. struct iwl_priv *priv = dev_get_drvdata(d);
  3073. return sprintf(buf, "%d", priv->retry_rate);
  3074. }
  3075. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  3076. store_retry_rate);
  3077. static ssize_t show_channels(struct device *d,
  3078. struct device_attribute *attr, char *buf)
  3079. {
  3080. /* all this shit doesn't belong into sysfs anyway */
  3081. return 0;
  3082. }
  3083. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  3084. static ssize_t show_antenna(struct device *d,
  3085. struct device_attribute *attr, char *buf)
  3086. {
  3087. struct iwl_priv *priv = dev_get_drvdata(d);
  3088. if (!iwl_is_alive(priv))
  3089. return -EAGAIN;
  3090. return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
  3091. }
  3092. static ssize_t store_antenna(struct device *d,
  3093. struct device_attribute *attr,
  3094. const char *buf, size_t count)
  3095. {
  3096. struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
  3097. int ant;
  3098. if (count == 0)
  3099. return 0;
  3100. if (sscanf(buf, "%1i", &ant) != 1) {
  3101. IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
  3102. return count;
  3103. }
  3104. if ((ant >= 0) && (ant <= 2)) {
  3105. IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
  3106. iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
  3107. } else
  3108. IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
  3109. return count;
  3110. }
  3111. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  3112. static ssize_t show_status(struct device *d,
  3113. struct device_attribute *attr, char *buf)
  3114. {
  3115. struct iwl_priv *priv = dev_get_drvdata(d);
  3116. if (!iwl_is_alive(priv))
  3117. return -EAGAIN;
  3118. return sprintf(buf, "0x%08x\n", (int)priv->status);
  3119. }
  3120. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  3121. static ssize_t dump_error_log(struct device *d,
  3122. struct device_attribute *attr,
  3123. const char *buf, size_t count)
  3124. {
  3125. struct iwl_priv *priv = dev_get_drvdata(d);
  3126. char *p = (char *)buf;
  3127. if (p[0] == '1')
  3128. iwl3945_dump_nic_error_log(priv);
  3129. return strnlen(buf, count);
  3130. }
  3131. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  3132. /*****************************************************************************
  3133. *
  3134. * driver setup and tear down
  3135. *
  3136. *****************************************************************************/
  3137. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  3138. {
  3139. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3140. init_waitqueue_head(&priv->wait_command_queue);
  3141. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  3142. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  3143. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  3144. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  3145. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  3146. INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll);
  3147. iwl_setup_scan_deferred_work(priv);
  3148. iwl3945_hw_setup_deferred_work(priv);
  3149. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  3150. init_timer(&priv->monitor_recover);
  3151. priv->monitor_recover.data = (unsigned long)priv;
  3152. priv->monitor_recover.function =
  3153. priv->cfg->ops->lib->recover_from_tx_stall;
  3154. }
  3155. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3156. iwl3945_irq_tasklet, (unsigned long)priv);
  3157. }
  3158. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  3159. {
  3160. iwl3945_hw_cancel_deferred_work(priv);
  3161. cancel_delayed_work_sync(&priv->init_alive_start);
  3162. cancel_delayed_work(&priv->alive_start);
  3163. cancel_work_sync(&priv->beacon_update);
  3164. iwl_cancel_scan_deferred_work(priv);
  3165. }
  3166. static struct attribute *iwl3945_sysfs_entries[] = {
  3167. &dev_attr_antenna.attr,
  3168. &dev_attr_channels.attr,
  3169. &dev_attr_dump_errors.attr,
  3170. &dev_attr_flags.attr,
  3171. &dev_attr_filter_flags.attr,
  3172. &dev_attr_measurement.attr,
  3173. &dev_attr_retry_rate.attr,
  3174. &dev_attr_status.attr,
  3175. &dev_attr_temperature.attr,
  3176. &dev_attr_tx_power.attr,
  3177. #ifdef CONFIG_IWLWIFI_DEBUG
  3178. &dev_attr_debug_level.attr,
  3179. #endif
  3180. NULL
  3181. };
  3182. static struct attribute_group iwl3945_attribute_group = {
  3183. .name = NULL, /* put in device directory */
  3184. .attrs = iwl3945_sysfs_entries,
  3185. };
  3186. struct ieee80211_ops iwl3945_hw_ops = {
  3187. .tx = iwl3945_mac_tx,
  3188. .start = iwl3945_mac_start,
  3189. .stop = iwl3945_mac_stop,
  3190. .add_interface = iwl_mac_add_interface,
  3191. .remove_interface = iwl_mac_remove_interface,
  3192. .change_interface = iwl_mac_change_interface,
  3193. .config = iwl_legacy_mac_config,
  3194. .configure_filter = iwl3945_configure_filter,
  3195. .set_key = iwl3945_mac_set_key,
  3196. .conf_tx = iwl_mac_conf_tx,
  3197. .reset_tsf = iwl_legacy_mac_reset_tsf,
  3198. .bss_info_changed = iwl_legacy_mac_bss_info_changed,
  3199. .hw_scan = iwl_mac_hw_scan,
  3200. .sta_add = iwl3945_mac_sta_add,
  3201. .sta_remove = iwl_mac_sta_remove,
  3202. .tx_last_beacon = iwl_mac_tx_last_beacon,
  3203. };
  3204. static int iwl3945_init_drv(struct iwl_priv *priv)
  3205. {
  3206. int ret;
  3207. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3208. priv->retry_rate = 1;
  3209. priv->beacon_skb = NULL;
  3210. spin_lock_init(&priv->sta_lock);
  3211. spin_lock_init(&priv->hcmd_lock);
  3212. INIT_LIST_HEAD(&priv->free_frames);
  3213. mutex_init(&priv->mutex);
  3214. mutex_init(&priv->sync_cmd_mutex);
  3215. priv->ieee_channels = NULL;
  3216. priv->ieee_rates = NULL;
  3217. priv->band = IEEE80211_BAND_2GHZ;
  3218. priv->iw_mode = NL80211_IFTYPE_STATION;
  3219. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3220. priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
  3221. priv->tx_power_next = IWL_DEFAULT_TX_POWER;
  3222. if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
  3223. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3224. eeprom->version);
  3225. ret = -EINVAL;
  3226. goto err;
  3227. }
  3228. ret = iwl_init_channel_map(priv);
  3229. if (ret) {
  3230. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3231. goto err;
  3232. }
  3233. /* Set up txpower settings in driver for all channels */
  3234. if (iwl3945_txpower_set_from_eeprom(priv)) {
  3235. ret = -EIO;
  3236. goto err_free_channel_map;
  3237. }
  3238. ret = iwlcore_init_geos(priv);
  3239. if (ret) {
  3240. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3241. goto err_free_channel_map;
  3242. }
  3243. iwl3945_init_hw_rates(priv, priv->ieee_rates);
  3244. return 0;
  3245. err_free_channel_map:
  3246. iwl_free_channel_map(priv);
  3247. err:
  3248. return ret;
  3249. }
  3250. #define IWL3945_MAX_PROBE_REQUEST 200
  3251. static int iwl3945_setup_mac(struct iwl_priv *priv)
  3252. {
  3253. int ret;
  3254. struct ieee80211_hw *hw = priv->hw;
  3255. hw->rate_control_algorithm = "iwl-3945-rs";
  3256. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  3257. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  3258. /* Tell mac80211 our characteristics */
  3259. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  3260. IEEE80211_HW_SPECTRUM_MGMT;
  3261. if (!priv->cfg->base_params->broken_powersave)
  3262. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  3263. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  3264. hw->wiphy->interface_modes =
  3265. priv->contexts[IWL_RXON_CTX_BSS].interface_modes;
  3266. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  3267. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  3268. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
  3269. /* we create the 802.11 header and a zero-length SSID element */
  3270. hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2;
  3271. /* Default value; 4 EDCA QOS priorities */
  3272. hw->queues = 4;
  3273. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3274. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3275. &priv->bands[IEEE80211_BAND_2GHZ];
  3276. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3277. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3278. &priv->bands[IEEE80211_BAND_5GHZ];
  3279. ret = ieee80211_register_hw(priv->hw);
  3280. if (ret) {
  3281. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  3282. return ret;
  3283. }
  3284. priv->mac80211_registered = 1;
  3285. return 0;
  3286. }
  3287. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3288. {
  3289. int err = 0, i;
  3290. struct iwl_priv *priv;
  3291. struct ieee80211_hw *hw;
  3292. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3293. struct iwl3945_eeprom *eeprom;
  3294. unsigned long flags;
  3295. /***********************
  3296. * 1. Allocating HW data
  3297. * ********************/
  3298. /* mac80211 allocates memory for this device instance, including
  3299. * space for this driver's private structure */
  3300. hw = iwl_alloc_all(cfg);
  3301. if (hw == NULL) {
  3302. pr_err("Can not allocate network device\n");
  3303. err = -ENOMEM;
  3304. goto out;
  3305. }
  3306. priv = hw->priv;
  3307. SET_IEEE80211_DEV(hw, &pdev->dev);
  3308. priv->cmd_queue = IWL39_CMD_QUEUE_NUM;
  3309. /* 3945 has only one valid context */
  3310. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  3311. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  3312. priv->contexts[i].ctxid = i;
  3313. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  3314. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  3315. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  3316. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  3317. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  3318. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  3319. priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
  3320. BIT(NL80211_IFTYPE_STATION) |
  3321. BIT(NL80211_IFTYPE_ADHOC);
  3322. priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
  3323. priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
  3324. priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
  3325. /*
  3326. * Disabling hardware scan means that mac80211 will perform scans
  3327. * "the hard way", rather than using device's scan.
  3328. */
  3329. if (iwl3945_mod_params.disable_hw_scan) {
  3330. dev_printk(KERN_DEBUG, &(pdev->dev),
  3331. "sw scan support is deprecated\n");
  3332. iwl3945_hw_ops.hw_scan = NULL;
  3333. }
  3334. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3335. priv->cfg = cfg;
  3336. priv->pci_dev = pdev;
  3337. priv->inta_mask = CSR_INI_SET_MASK;
  3338. if (iwl_alloc_traffic_mem(priv))
  3339. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3340. /***************************
  3341. * 2. Initializing PCI bus
  3342. * *************************/
  3343. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3344. PCIE_LINK_STATE_CLKPM);
  3345. if (pci_enable_device(pdev)) {
  3346. err = -ENODEV;
  3347. goto out_ieee80211_free_hw;
  3348. }
  3349. pci_set_master(pdev);
  3350. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3351. if (!err)
  3352. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3353. if (err) {
  3354. IWL_WARN(priv, "No suitable DMA available.\n");
  3355. goto out_pci_disable_device;
  3356. }
  3357. pci_set_drvdata(pdev, priv);
  3358. err = pci_request_regions(pdev, DRV_NAME);
  3359. if (err)
  3360. goto out_pci_disable_device;
  3361. /***********************
  3362. * 3. Read REV Register
  3363. * ********************/
  3364. priv->hw_base = pci_iomap(pdev, 0, 0);
  3365. if (!priv->hw_base) {
  3366. err = -ENODEV;
  3367. goto out_pci_release_regions;
  3368. }
  3369. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3370. (unsigned long long) pci_resource_len(pdev, 0));
  3371. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3372. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3373. * PCI Tx retries from interfering with C3 CPU state */
  3374. pci_write_config_byte(pdev, 0x41, 0x00);
  3375. /* these spin locks will be used in apm_ops.init and EEPROM access
  3376. * we should init now
  3377. */
  3378. spin_lock_init(&priv->reg_lock);
  3379. spin_lock_init(&priv->lock);
  3380. /*
  3381. * stop and reset the on-board processor just in case it is in a
  3382. * strange state ... like being left stranded by a primary kernel
  3383. * and this is now the kdump kernel trying to start up
  3384. */
  3385. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3386. /***********************
  3387. * 4. Read EEPROM
  3388. * ********************/
  3389. /* Read the EEPROM */
  3390. err = iwl_eeprom_init(priv);
  3391. if (err) {
  3392. IWL_ERR(priv, "Unable to init EEPROM\n");
  3393. goto out_iounmap;
  3394. }
  3395. /* MAC Address location in EEPROM same for 3945/4965 */
  3396. eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3397. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", eeprom->mac_address);
  3398. SET_IEEE80211_PERM_ADDR(priv->hw, eeprom->mac_address);
  3399. /***********************
  3400. * 5. Setup HW Constants
  3401. * ********************/
  3402. /* Device-specific setup */
  3403. if (iwl3945_hw_set_hw_params(priv)) {
  3404. IWL_ERR(priv, "failed to set hw settings\n");
  3405. goto out_eeprom_free;
  3406. }
  3407. /***********************
  3408. * 6. Setup priv
  3409. * ********************/
  3410. err = iwl3945_init_drv(priv);
  3411. if (err) {
  3412. IWL_ERR(priv, "initializing driver failed\n");
  3413. goto out_unset_hw_params;
  3414. }
  3415. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  3416. priv->cfg->name);
  3417. /***********************
  3418. * 7. Setup Services
  3419. * ********************/
  3420. spin_lock_irqsave(&priv->lock, flags);
  3421. iwl_disable_interrupts(priv);
  3422. spin_unlock_irqrestore(&priv->lock, flags);
  3423. pci_enable_msi(priv->pci_dev);
  3424. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
  3425. IRQF_SHARED, DRV_NAME, priv);
  3426. if (err) {
  3427. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3428. goto out_disable_msi;
  3429. }
  3430. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3431. if (err) {
  3432. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3433. goto out_release_irq;
  3434. }
  3435. iwl_set_rxon_channel(priv,
  3436. &priv->bands[IEEE80211_BAND_2GHZ].channels[5],
  3437. &priv->contexts[IWL_RXON_CTX_BSS]);
  3438. iwl3945_setup_deferred_work(priv);
  3439. iwl3945_setup_rx_handlers(priv);
  3440. iwl_power_initialize(priv);
  3441. /*********************************
  3442. * 8. Setup and Register mac80211
  3443. * *******************************/
  3444. iwl_enable_interrupts(priv);
  3445. err = iwl3945_setup_mac(priv);
  3446. if (err)
  3447. goto out_remove_sysfs;
  3448. err = iwl_dbgfs_register(priv, DRV_NAME);
  3449. if (err)
  3450. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  3451. /* Start monitoring the killswitch */
  3452. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  3453. 2 * HZ);
  3454. return 0;
  3455. out_remove_sysfs:
  3456. destroy_workqueue(priv->workqueue);
  3457. priv->workqueue = NULL;
  3458. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3459. out_release_irq:
  3460. free_irq(priv->pci_dev->irq, priv);
  3461. out_disable_msi:
  3462. pci_disable_msi(priv->pci_dev);
  3463. iwlcore_free_geos(priv);
  3464. iwl_free_channel_map(priv);
  3465. out_unset_hw_params:
  3466. iwl3945_unset_hw_params(priv);
  3467. out_eeprom_free:
  3468. iwl_eeprom_free(priv);
  3469. out_iounmap:
  3470. pci_iounmap(pdev, priv->hw_base);
  3471. out_pci_release_regions:
  3472. pci_release_regions(pdev);
  3473. out_pci_disable_device:
  3474. pci_set_drvdata(pdev, NULL);
  3475. pci_disable_device(pdev);
  3476. out_ieee80211_free_hw:
  3477. iwl_free_traffic_mem(priv);
  3478. ieee80211_free_hw(priv->hw);
  3479. out:
  3480. return err;
  3481. }
  3482. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  3483. {
  3484. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3485. unsigned long flags;
  3486. if (!priv)
  3487. return;
  3488. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3489. iwl_dbgfs_unregister(priv);
  3490. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3491. if (priv->mac80211_registered) {
  3492. ieee80211_unregister_hw(priv->hw);
  3493. priv->mac80211_registered = 0;
  3494. } else {
  3495. iwl3945_down(priv);
  3496. }
  3497. /*
  3498. * Make sure device is reset to low power before unloading driver.
  3499. * This may be redundant with iwl_down(), but there are paths to
  3500. * run iwl_down() without calling apm_ops.stop(), and there are
  3501. * paths to avoid running iwl_down() at all before leaving driver.
  3502. * This (inexpensive) call *makes sure* device is reset.
  3503. */
  3504. iwl_apm_stop(priv);
  3505. /* make sure we flush any pending irq or
  3506. * tasklet for the driver
  3507. */
  3508. spin_lock_irqsave(&priv->lock, flags);
  3509. iwl_disable_interrupts(priv);
  3510. spin_unlock_irqrestore(&priv->lock, flags);
  3511. iwl_synchronize_irq(priv);
  3512. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3513. cancel_delayed_work_sync(&priv->_3945.rfkill_poll);
  3514. iwl3945_dealloc_ucode_pci(priv);
  3515. if (priv->rxq.bd)
  3516. iwl3945_rx_queue_free(priv, &priv->rxq);
  3517. iwl3945_hw_txq_ctx_free(priv);
  3518. iwl3945_unset_hw_params(priv);
  3519. /*netif_stop_queue(dev); */
  3520. flush_workqueue(priv->workqueue);
  3521. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  3522. * priv->workqueue... so we can't take down the workqueue
  3523. * until now... */
  3524. destroy_workqueue(priv->workqueue);
  3525. priv->workqueue = NULL;
  3526. iwl_free_traffic_mem(priv);
  3527. free_irq(pdev->irq, priv);
  3528. pci_disable_msi(pdev);
  3529. pci_iounmap(pdev, priv->hw_base);
  3530. pci_release_regions(pdev);
  3531. pci_disable_device(pdev);
  3532. pci_set_drvdata(pdev, NULL);
  3533. iwl_free_channel_map(priv);
  3534. iwlcore_free_geos(priv);
  3535. kfree(priv->scan_cmd);
  3536. if (priv->beacon_skb)
  3537. dev_kfree_skb(priv->beacon_skb);
  3538. ieee80211_free_hw(priv->hw);
  3539. }
  3540. /*****************************************************************************
  3541. *
  3542. * driver and module entry point
  3543. *
  3544. *****************************************************************************/
  3545. static struct pci_driver iwl3945_driver = {
  3546. .name = DRV_NAME,
  3547. .id_table = iwl3945_hw_card_ids,
  3548. .probe = iwl3945_pci_probe,
  3549. .remove = __devexit_p(iwl3945_pci_remove),
  3550. .driver.pm = IWL_PM_OPS,
  3551. };
  3552. static int __init iwl3945_init(void)
  3553. {
  3554. int ret;
  3555. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3556. pr_info(DRV_COPYRIGHT "\n");
  3557. ret = iwl3945_rate_control_register();
  3558. if (ret) {
  3559. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3560. return ret;
  3561. }
  3562. ret = pci_register_driver(&iwl3945_driver);
  3563. if (ret) {
  3564. pr_err("Unable to initialize PCI module\n");
  3565. goto error_register;
  3566. }
  3567. return ret;
  3568. error_register:
  3569. iwl3945_rate_control_unregister();
  3570. return ret;
  3571. }
  3572. static void __exit iwl3945_exit(void)
  3573. {
  3574. pci_unregister_driver(&iwl3945_driver);
  3575. iwl3945_rate_control_unregister();
  3576. }
  3577. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  3578. module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
  3579. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3580. module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
  3581. MODULE_PARM_DESC(swcrypto,
  3582. "using software crypto (default 1 [software])\n");
  3583. #ifdef CONFIG_IWLWIFI_DEBUG
  3584. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3585. MODULE_PARM_DESC(debug, "debug output mask");
  3586. #endif
  3587. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
  3588. int, S_IRUGO);
  3589. MODULE_PARM_DESC(disable_hw_scan,
  3590. "disable hardware scanning (default 0) (deprecated)");
  3591. module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
  3592. MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
  3593. module_exit(iwl3945_exit);
  3594. module_init(iwl3945_init);