main.c 54 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/pm_qos_params.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath_update_txpow(struct ath_softc *sc)
  21. {
  22. struct ath_hw *ah = sc->sc_ah;
  23. if (sc->curtxpow != sc->config.txpowlimit) {
  24. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
  25. /* read back in case value is clamped */
  26. sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  27. }
  28. }
  29. static u8 parse_mpdudensity(u8 mpdudensity)
  30. {
  31. /*
  32. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  33. * 0 for no restriction
  34. * 1 for 1/4 us
  35. * 2 for 1/2 us
  36. * 3 for 1 us
  37. * 4 for 2 us
  38. * 5 for 4 us
  39. * 6 for 8 us
  40. * 7 for 16 us
  41. */
  42. switch (mpdudensity) {
  43. case 0:
  44. return 0;
  45. case 1:
  46. case 2:
  47. case 3:
  48. /* Our lower layer calculations limit our precision to
  49. 1 microsecond */
  50. return 1;
  51. case 4:
  52. return 2;
  53. case 5:
  54. return 4;
  55. case 6:
  56. return 8;
  57. case 7:
  58. return 16;
  59. default:
  60. return 0;
  61. }
  62. }
  63. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  64. struct ieee80211_hw *hw)
  65. {
  66. struct ieee80211_channel *curchan = hw->conf.channel;
  67. struct ath9k_channel *channel;
  68. u8 chan_idx;
  69. chan_idx = curchan->hw_value;
  70. channel = &sc->sc_ah->channels[chan_idx];
  71. ath9k_update_ichannel(sc, hw, channel);
  72. return channel;
  73. }
  74. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  75. {
  76. unsigned long flags;
  77. bool ret;
  78. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  79. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  80. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  81. return ret;
  82. }
  83. void ath9k_ps_wakeup(struct ath_softc *sc)
  84. {
  85. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  86. unsigned long flags;
  87. enum ath9k_power_mode power_mode;
  88. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  89. if (++sc->ps_usecount != 1)
  90. goto unlock;
  91. power_mode = sc->sc_ah->power_mode;
  92. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  93. /*
  94. * While the hardware is asleep, the cycle counters contain no
  95. * useful data. Better clear them now so that they don't mess up
  96. * survey data results.
  97. */
  98. if (power_mode != ATH9K_PM_AWAKE) {
  99. spin_lock(&common->cc_lock);
  100. ath_hw_cycle_counters_update(common);
  101. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  102. spin_unlock(&common->cc_lock);
  103. }
  104. unlock:
  105. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  106. }
  107. void ath9k_ps_restore(struct ath_softc *sc)
  108. {
  109. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  110. unsigned long flags;
  111. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  112. if (--sc->ps_usecount != 0)
  113. goto unlock;
  114. spin_lock(&common->cc_lock);
  115. ath_hw_cycle_counters_update(common);
  116. spin_unlock(&common->cc_lock);
  117. if (sc->ps_idle)
  118. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  119. else if (sc->ps_enabled &&
  120. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  121. PS_WAIT_FOR_CAB |
  122. PS_WAIT_FOR_PSPOLL_DATA |
  123. PS_WAIT_FOR_TX_ACK)))
  124. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  125. unlock:
  126. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  127. }
  128. static void ath_start_ani(struct ath_common *common)
  129. {
  130. struct ath_hw *ah = common->ah;
  131. unsigned long timestamp = jiffies_to_msecs(jiffies);
  132. struct ath_softc *sc = (struct ath_softc *) common->priv;
  133. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  134. return;
  135. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  136. return;
  137. common->ani.longcal_timer = timestamp;
  138. common->ani.shortcal_timer = timestamp;
  139. common->ani.checkani_timer = timestamp;
  140. mod_timer(&common->ani.timer,
  141. jiffies +
  142. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  143. }
  144. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  145. {
  146. struct ath_hw *ah = sc->sc_ah;
  147. struct ath9k_channel *chan = &ah->channels[channel];
  148. struct survey_info *survey = &sc->survey[channel];
  149. if (chan->noisefloor) {
  150. survey->filled |= SURVEY_INFO_NOISE_DBM;
  151. survey->noise = chan->noisefloor;
  152. }
  153. }
  154. static void ath_update_survey_stats(struct ath_softc *sc)
  155. {
  156. struct ath_hw *ah = sc->sc_ah;
  157. struct ath_common *common = ath9k_hw_common(ah);
  158. int pos = ah->curchan - &ah->channels[0];
  159. struct survey_info *survey = &sc->survey[pos];
  160. struct ath_cycle_counters *cc = &common->cc_survey;
  161. unsigned int div = common->clockrate * 1000;
  162. if (!ah->curchan)
  163. return;
  164. if (ah->power_mode == ATH9K_PM_AWAKE)
  165. ath_hw_cycle_counters_update(common);
  166. if (cc->cycles > 0) {
  167. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  168. SURVEY_INFO_CHANNEL_TIME_BUSY |
  169. SURVEY_INFO_CHANNEL_TIME_RX |
  170. SURVEY_INFO_CHANNEL_TIME_TX;
  171. survey->channel_time += cc->cycles / div;
  172. survey->channel_time_busy += cc->rx_busy / div;
  173. survey->channel_time_rx += cc->rx_frame / div;
  174. survey->channel_time_tx += cc->tx_frame / div;
  175. }
  176. memset(cc, 0, sizeof(*cc));
  177. ath_update_survey_nf(sc, pos);
  178. }
  179. /*
  180. * Set/change channels. If the channel is really being changed, it's done
  181. * by reseting the chip. To accomplish this we must first cleanup any pending
  182. * DMA, then restart stuff.
  183. */
  184. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  185. struct ath9k_channel *hchan)
  186. {
  187. struct ath_wiphy *aphy = hw->priv;
  188. struct ath_hw *ah = sc->sc_ah;
  189. struct ath_common *common = ath9k_hw_common(ah);
  190. struct ieee80211_conf *conf = &common->hw->conf;
  191. bool fastcc = true, stopped;
  192. struct ieee80211_channel *channel = hw->conf.channel;
  193. struct ath9k_hw_cal_data *caldata = NULL;
  194. int r;
  195. if (sc->sc_flags & SC_OP_INVALID)
  196. return -EIO;
  197. del_timer_sync(&common->ani.timer);
  198. cancel_work_sync(&sc->paprd_work);
  199. cancel_work_sync(&sc->hw_check_work);
  200. cancel_delayed_work_sync(&sc->tx_complete_work);
  201. ath9k_ps_wakeup(sc);
  202. spin_lock_bh(&sc->sc_pcu_lock);
  203. /*
  204. * This is only performed if the channel settings have
  205. * actually changed.
  206. *
  207. * To switch channels clear any pending DMA operations;
  208. * wait long enough for the RX fifo to drain, reset the
  209. * hardware at the new frequency, and then re-enable
  210. * the relevant bits of the h/w.
  211. */
  212. ath9k_hw_disable_interrupts(ah);
  213. ath_drain_all_txq(sc, false);
  214. stopped = ath_stoprecv(sc);
  215. /* XXX: do not flush receive queue here. We don't want
  216. * to flush data frames already in queue because of
  217. * changing channel. */
  218. if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
  219. fastcc = false;
  220. if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
  221. caldata = &aphy->caldata;
  222. ath_print(common, ATH_DBG_CONFIG,
  223. "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
  224. sc->sc_ah->curchan->channel,
  225. channel->center_freq, conf_is_ht40(conf),
  226. fastcc);
  227. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  228. if (r) {
  229. ath_print(common, ATH_DBG_FATAL,
  230. "Unable to reset channel (%u MHz), "
  231. "reset status %d\n",
  232. channel->center_freq, r);
  233. goto ps_restore;
  234. }
  235. if (ath_startrecv(sc) != 0) {
  236. ath_print(common, ATH_DBG_FATAL,
  237. "Unable to restart recv logic\n");
  238. r = -EIO;
  239. goto ps_restore;
  240. }
  241. ath_update_txpow(sc);
  242. ath9k_hw_set_interrupts(ah, ah->imask);
  243. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
  244. ath_beacon_config(sc, NULL);
  245. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  246. ath_start_ani(common);
  247. }
  248. ps_restore:
  249. spin_unlock_bh(&sc->sc_pcu_lock);
  250. ath9k_ps_restore(sc);
  251. return r;
  252. }
  253. static void ath_paprd_activate(struct ath_softc *sc)
  254. {
  255. struct ath_hw *ah = sc->sc_ah;
  256. struct ath9k_hw_cal_data *caldata = ah->caldata;
  257. struct ath_common *common = ath9k_hw_common(ah);
  258. int chain;
  259. if (!caldata || !caldata->paprd_done)
  260. return;
  261. ath9k_ps_wakeup(sc);
  262. ar9003_paprd_enable(ah, false);
  263. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  264. if (!(common->tx_chainmask & BIT(chain)))
  265. continue;
  266. ar9003_paprd_populate_single_table(ah, caldata, chain);
  267. }
  268. ar9003_paprd_enable(ah, true);
  269. ath9k_ps_restore(sc);
  270. }
  271. void ath_paprd_calibrate(struct work_struct *work)
  272. {
  273. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  274. struct ieee80211_hw *hw = sc->hw;
  275. struct ath_hw *ah = sc->sc_ah;
  276. struct ieee80211_hdr *hdr;
  277. struct sk_buff *skb = NULL;
  278. struct ieee80211_tx_info *tx_info;
  279. int band = hw->conf.channel->band;
  280. struct ieee80211_supported_band *sband = &sc->sbands[band];
  281. struct ath_tx_control txctl;
  282. struct ath9k_hw_cal_data *caldata = ah->caldata;
  283. struct ath_common *common = ath9k_hw_common(ah);
  284. int ftype;
  285. int chain_ok = 0;
  286. int chain;
  287. int len = 1800;
  288. int time_left;
  289. int i;
  290. if (!caldata)
  291. return;
  292. skb = alloc_skb(len, GFP_KERNEL);
  293. if (!skb)
  294. return;
  295. tx_info = IEEE80211_SKB_CB(skb);
  296. skb_put(skb, len);
  297. memset(skb->data, 0, len);
  298. hdr = (struct ieee80211_hdr *)skb->data;
  299. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  300. hdr->frame_control = cpu_to_le16(ftype);
  301. hdr->duration_id = cpu_to_le16(10);
  302. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  303. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  304. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  305. memset(&txctl, 0, sizeof(txctl));
  306. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  307. ath9k_ps_wakeup(sc);
  308. ar9003_paprd_init_table(ah);
  309. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  310. if (!(common->tx_chainmask & BIT(chain)))
  311. continue;
  312. chain_ok = 0;
  313. memset(tx_info, 0, sizeof(*tx_info));
  314. tx_info->band = band;
  315. for (i = 0; i < 4; i++) {
  316. tx_info->control.rates[i].idx = sband->n_bitrates - 1;
  317. tx_info->control.rates[i].count = 6;
  318. }
  319. init_completion(&sc->paprd_complete);
  320. ar9003_paprd_setup_gain_table(ah, chain);
  321. txctl.paprd = BIT(chain);
  322. if (ath_tx_start(hw, skb, &txctl) != 0)
  323. break;
  324. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  325. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  326. if (!time_left) {
  327. ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
  328. "Timeout waiting for paprd training on "
  329. "TX chain %d\n",
  330. chain);
  331. goto fail_paprd;
  332. }
  333. if (!ar9003_paprd_is_done(ah))
  334. break;
  335. if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
  336. break;
  337. chain_ok = 1;
  338. }
  339. kfree_skb(skb);
  340. if (chain_ok) {
  341. caldata->paprd_done = true;
  342. ath_paprd_activate(sc);
  343. }
  344. fail_paprd:
  345. ath9k_ps_restore(sc);
  346. }
  347. /*
  348. * This routine performs the periodic noise floor calibration function
  349. * that is used to adjust and optimize the chip performance. This
  350. * takes environmental changes (location, temperature) into account.
  351. * When the task is complete, it reschedules itself depending on the
  352. * appropriate interval that was calculated.
  353. */
  354. void ath_ani_calibrate(unsigned long data)
  355. {
  356. struct ath_softc *sc = (struct ath_softc *)data;
  357. struct ath_hw *ah = sc->sc_ah;
  358. struct ath_common *common = ath9k_hw_common(ah);
  359. bool longcal = false;
  360. bool shortcal = false;
  361. bool aniflag = false;
  362. unsigned int timestamp = jiffies_to_msecs(jiffies);
  363. u32 cal_interval, short_cal_interval, long_cal_interval;
  364. unsigned long flags;
  365. if (ah->caldata && ah->caldata->nfcal_interference)
  366. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  367. else
  368. long_cal_interval = ATH_LONG_CALINTERVAL;
  369. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  370. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  371. /* Only calibrate if awake */
  372. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  373. goto set_timer;
  374. ath9k_ps_wakeup(sc);
  375. /* Long calibration runs independently of short calibration. */
  376. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  377. longcal = true;
  378. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  379. common->ani.longcal_timer = timestamp;
  380. }
  381. /* Short calibration applies only while caldone is false */
  382. if (!common->ani.caldone) {
  383. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  384. shortcal = true;
  385. ath_print(common, ATH_DBG_ANI,
  386. "shortcal @%lu\n", jiffies);
  387. common->ani.shortcal_timer = timestamp;
  388. common->ani.resetcal_timer = timestamp;
  389. }
  390. } else {
  391. if ((timestamp - common->ani.resetcal_timer) >=
  392. ATH_RESTART_CALINTERVAL) {
  393. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  394. if (common->ani.caldone)
  395. common->ani.resetcal_timer = timestamp;
  396. }
  397. }
  398. /* Verify whether we must check ANI */
  399. if ((timestamp - common->ani.checkani_timer) >=
  400. ah->config.ani_poll_interval) {
  401. aniflag = true;
  402. common->ani.checkani_timer = timestamp;
  403. }
  404. /* Skip all processing if there's nothing to do. */
  405. if (longcal || shortcal || aniflag) {
  406. /* Call ANI routine if necessary */
  407. if (aniflag) {
  408. spin_lock_irqsave(&common->cc_lock, flags);
  409. ath9k_hw_ani_monitor(ah, ah->curchan);
  410. ath_update_survey_stats(sc);
  411. spin_unlock_irqrestore(&common->cc_lock, flags);
  412. }
  413. /* Perform calibration if necessary */
  414. if (longcal || shortcal) {
  415. common->ani.caldone =
  416. ath9k_hw_calibrate(ah,
  417. ah->curchan,
  418. common->rx_chainmask,
  419. longcal);
  420. }
  421. }
  422. ath9k_ps_restore(sc);
  423. set_timer:
  424. /*
  425. * Set timer interval based on previous results.
  426. * The interval must be the shortest necessary to satisfy ANI,
  427. * short calibration and long calibration.
  428. */
  429. cal_interval = ATH_LONG_CALINTERVAL;
  430. if (sc->sc_ah->config.enable_ani)
  431. cal_interval = min(cal_interval,
  432. (u32)ah->config.ani_poll_interval);
  433. if (!common->ani.caldone)
  434. cal_interval = min(cal_interval, (u32)short_cal_interval);
  435. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  436. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  437. if (!ah->caldata->paprd_done)
  438. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  439. else
  440. ath_paprd_activate(sc);
  441. }
  442. }
  443. /*
  444. * Update tx/rx chainmask. For legacy association,
  445. * hard code chainmask to 1x1, for 11n association, use
  446. * the chainmask configuration, for bt coexistence, use
  447. * the chainmask configuration even in legacy mode.
  448. */
  449. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  450. {
  451. struct ath_hw *ah = sc->sc_ah;
  452. struct ath_common *common = ath9k_hw_common(ah);
  453. if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
  454. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  455. common->tx_chainmask = ah->caps.tx_chainmask;
  456. common->rx_chainmask = ah->caps.rx_chainmask;
  457. } else {
  458. common->tx_chainmask = 1;
  459. common->rx_chainmask = 1;
  460. }
  461. ath_print(common, ATH_DBG_CONFIG,
  462. "tx chmask: %d, rx chmask: %d\n",
  463. common->tx_chainmask,
  464. common->rx_chainmask);
  465. }
  466. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  467. {
  468. struct ath_node *an;
  469. an = (struct ath_node *)sta->drv_priv;
  470. if (sc->sc_flags & SC_OP_TXAGGR) {
  471. ath_tx_node_init(sc, an);
  472. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  473. sta->ht_cap.ampdu_factor);
  474. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  475. }
  476. }
  477. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  478. {
  479. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  480. if (sc->sc_flags & SC_OP_TXAGGR)
  481. ath_tx_node_cleanup(sc, an);
  482. }
  483. void ath_hw_check(struct work_struct *work)
  484. {
  485. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  486. int i;
  487. ath9k_ps_wakeup(sc);
  488. for (i = 0; i < 3; i++) {
  489. if (ath9k_hw_check_alive(sc->sc_ah))
  490. goto out;
  491. msleep(1);
  492. }
  493. ath_reset(sc, true);
  494. out:
  495. ath9k_ps_restore(sc);
  496. }
  497. void ath9k_tasklet(unsigned long data)
  498. {
  499. struct ath_softc *sc = (struct ath_softc *)data;
  500. struct ath_hw *ah = sc->sc_ah;
  501. struct ath_common *common = ath9k_hw_common(ah);
  502. u32 status = sc->intrstatus;
  503. u32 rxmask;
  504. ath9k_ps_wakeup(sc);
  505. if (status & ATH9K_INT_FATAL) {
  506. ath_reset(sc, true);
  507. ath9k_ps_restore(sc);
  508. return;
  509. }
  510. spin_lock_bh(&sc->sc_pcu_lock);
  511. if (!ath9k_hw_check_alive(ah))
  512. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  513. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  514. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  515. ATH9K_INT_RXORN);
  516. else
  517. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  518. if (status & rxmask) {
  519. /* Check for high priority Rx first */
  520. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  521. (status & ATH9K_INT_RXHP))
  522. ath_rx_tasklet(sc, 0, true);
  523. ath_rx_tasklet(sc, 0, false);
  524. }
  525. if (status & ATH9K_INT_TX) {
  526. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  527. ath_tx_edma_tasklet(sc);
  528. else
  529. ath_tx_tasklet(sc);
  530. }
  531. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  532. /*
  533. * TSF sync does not look correct; remain awake to sync with
  534. * the next Beacon.
  535. */
  536. ath_print(common, ATH_DBG_PS,
  537. "TSFOOR - Sync with next Beacon\n");
  538. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  539. }
  540. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  541. if (status & ATH9K_INT_GENTIMER)
  542. ath_gen_timer_isr(sc->sc_ah);
  543. /* re-enable hardware interrupt */
  544. ath9k_hw_enable_interrupts(ah);
  545. spin_unlock_bh(&sc->sc_pcu_lock);
  546. ath9k_ps_restore(sc);
  547. }
  548. irqreturn_t ath_isr(int irq, void *dev)
  549. {
  550. #define SCHED_INTR ( \
  551. ATH9K_INT_FATAL | \
  552. ATH9K_INT_RXORN | \
  553. ATH9K_INT_RXEOL | \
  554. ATH9K_INT_RX | \
  555. ATH9K_INT_RXLP | \
  556. ATH9K_INT_RXHP | \
  557. ATH9K_INT_TX | \
  558. ATH9K_INT_BMISS | \
  559. ATH9K_INT_CST | \
  560. ATH9K_INT_TSFOOR | \
  561. ATH9K_INT_GENTIMER)
  562. struct ath_softc *sc = dev;
  563. struct ath_hw *ah = sc->sc_ah;
  564. struct ath_common *common = ath9k_hw_common(ah);
  565. enum ath9k_int status;
  566. bool sched = false;
  567. /*
  568. * The hardware is not ready/present, don't
  569. * touch anything. Note this can happen early
  570. * on if the IRQ is shared.
  571. */
  572. if (sc->sc_flags & SC_OP_INVALID)
  573. return IRQ_NONE;
  574. /* shared irq, not for us */
  575. if (!ath9k_hw_intrpend(ah))
  576. return IRQ_NONE;
  577. /*
  578. * Figure out the reason(s) for the interrupt. Note
  579. * that the hal returns a pseudo-ISR that may include
  580. * bits we haven't explicitly enabled so we mask the
  581. * value to insure we only process bits we requested.
  582. */
  583. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  584. status &= ah->imask; /* discard unasked-for bits */
  585. /*
  586. * If there are no status bits set, then this interrupt was not
  587. * for me (should have been caught above).
  588. */
  589. if (!status)
  590. return IRQ_NONE;
  591. /* Cache the status */
  592. sc->intrstatus = status;
  593. if (status & SCHED_INTR)
  594. sched = true;
  595. /*
  596. * If a FATAL or RXORN interrupt is received, we have to reset the
  597. * chip immediately.
  598. */
  599. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  600. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  601. goto chip_reset;
  602. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  603. (status & ATH9K_INT_BB_WATCHDOG)) {
  604. spin_lock(&common->cc_lock);
  605. ath_hw_cycle_counters_update(common);
  606. ar9003_hw_bb_watchdog_dbg_info(ah);
  607. spin_unlock(&common->cc_lock);
  608. goto chip_reset;
  609. }
  610. if (status & ATH9K_INT_SWBA)
  611. tasklet_schedule(&sc->bcon_tasklet);
  612. if (status & ATH9K_INT_TXURN)
  613. ath9k_hw_updatetxtriglevel(ah, true);
  614. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  615. if (status & ATH9K_INT_RXEOL) {
  616. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  617. ath9k_hw_set_interrupts(ah, ah->imask);
  618. }
  619. }
  620. if (status & ATH9K_INT_MIB) {
  621. /*
  622. * Disable interrupts until we service the MIB
  623. * interrupt; otherwise it will continue to
  624. * fire.
  625. */
  626. ath9k_hw_disable_interrupts(ah);
  627. /*
  628. * Let the hal handle the event. We assume
  629. * it will clear whatever condition caused
  630. * the interrupt.
  631. */
  632. spin_lock(&common->cc_lock);
  633. ath9k_hw_proc_mib_event(ah);
  634. spin_unlock(&common->cc_lock);
  635. ath9k_hw_enable_interrupts(ah);
  636. }
  637. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  638. if (status & ATH9K_INT_TIM_TIMER) {
  639. /* Clear RxAbort bit so that we can
  640. * receive frames */
  641. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  642. ath9k_hw_setrxabort(sc->sc_ah, 0);
  643. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  644. }
  645. chip_reset:
  646. ath_debug_stat_interrupt(sc, status);
  647. if (sched) {
  648. /* turn off every interrupt */
  649. ath9k_hw_disable_interrupts(ah);
  650. tasklet_schedule(&sc->intr_tq);
  651. }
  652. return IRQ_HANDLED;
  653. #undef SCHED_INTR
  654. }
  655. static u32 ath_get_extchanmode(struct ath_softc *sc,
  656. struct ieee80211_channel *chan,
  657. enum nl80211_channel_type channel_type)
  658. {
  659. u32 chanmode = 0;
  660. switch (chan->band) {
  661. case IEEE80211_BAND_2GHZ:
  662. switch(channel_type) {
  663. case NL80211_CHAN_NO_HT:
  664. case NL80211_CHAN_HT20:
  665. chanmode = CHANNEL_G_HT20;
  666. break;
  667. case NL80211_CHAN_HT40PLUS:
  668. chanmode = CHANNEL_G_HT40PLUS;
  669. break;
  670. case NL80211_CHAN_HT40MINUS:
  671. chanmode = CHANNEL_G_HT40MINUS;
  672. break;
  673. }
  674. break;
  675. case IEEE80211_BAND_5GHZ:
  676. switch(channel_type) {
  677. case NL80211_CHAN_NO_HT:
  678. case NL80211_CHAN_HT20:
  679. chanmode = CHANNEL_A_HT20;
  680. break;
  681. case NL80211_CHAN_HT40PLUS:
  682. chanmode = CHANNEL_A_HT40PLUS;
  683. break;
  684. case NL80211_CHAN_HT40MINUS:
  685. chanmode = CHANNEL_A_HT40MINUS;
  686. break;
  687. }
  688. break;
  689. default:
  690. break;
  691. }
  692. return chanmode;
  693. }
  694. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  695. struct ieee80211_hw *hw,
  696. struct ieee80211_vif *vif,
  697. struct ieee80211_bss_conf *bss_conf)
  698. {
  699. struct ath_wiphy *aphy = hw->priv;
  700. struct ath_hw *ah = sc->sc_ah;
  701. struct ath_common *common = ath9k_hw_common(ah);
  702. if (bss_conf->assoc) {
  703. ath_print(common, ATH_DBG_CONFIG,
  704. "Bss Info ASSOC %d, bssid: %pM\n",
  705. bss_conf->aid, common->curbssid);
  706. /* New association, store aid */
  707. common->curaid = bss_conf->aid;
  708. ath9k_hw_write_associd(ah);
  709. /*
  710. * Request a re-configuration of Beacon related timers
  711. * on the receipt of the first Beacon frame (i.e.,
  712. * after time sync with the AP).
  713. */
  714. sc->ps_flags |= PS_BEACON_SYNC;
  715. /* Configure the beacon */
  716. ath_beacon_config(sc, vif);
  717. /* Reset rssi stats */
  718. aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
  719. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  720. sc->sc_flags |= SC_OP_ANI_RUN;
  721. ath_start_ani(common);
  722. } else {
  723. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  724. common->curaid = 0;
  725. /* Stop ANI */
  726. sc->sc_flags &= ~SC_OP_ANI_RUN;
  727. del_timer_sync(&common->ani.timer);
  728. }
  729. }
  730. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  731. {
  732. struct ath_hw *ah = sc->sc_ah;
  733. struct ath_common *common = ath9k_hw_common(ah);
  734. struct ieee80211_channel *channel = hw->conf.channel;
  735. int r;
  736. ath9k_ps_wakeup(sc);
  737. spin_lock_bh(&sc->sc_pcu_lock);
  738. ath9k_hw_configpcipowersave(ah, 0, 0);
  739. if (!ah->curchan)
  740. ah->curchan = ath_get_curchannel(sc, sc->hw);
  741. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  742. if (r) {
  743. ath_print(common, ATH_DBG_FATAL,
  744. "Unable to reset channel (%u MHz), "
  745. "reset status %d\n",
  746. channel->center_freq, r);
  747. }
  748. ath_update_txpow(sc);
  749. if (ath_startrecv(sc) != 0) {
  750. ath_print(common, ATH_DBG_FATAL,
  751. "Unable to restart recv logic\n");
  752. spin_unlock_bh(&sc->sc_pcu_lock);
  753. return;
  754. }
  755. if (sc->sc_flags & SC_OP_BEACONS)
  756. ath_beacon_config(sc, NULL); /* restart beacons */
  757. /* Re-Enable interrupts */
  758. ath9k_hw_set_interrupts(ah, ah->imask);
  759. /* Enable LED */
  760. ath9k_hw_cfg_output(ah, ah->led_pin,
  761. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  762. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  763. ieee80211_wake_queues(hw);
  764. spin_unlock_bh(&sc->sc_pcu_lock);
  765. ath9k_ps_restore(sc);
  766. }
  767. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  768. {
  769. struct ath_hw *ah = sc->sc_ah;
  770. struct ieee80211_channel *channel = hw->conf.channel;
  771. int r;
  772. ath9k_ps_wakeup(sc);
  773. spin_lock_bh(&sc->sc_pcu_lock);
  774. ieee80211_stop_queues(hw);
  775. /*
  776. * Keep the LED on when the radio is disabled
  777. * during idle unassociated state.
  778. */
  779. if (!sc->ps_idle) {
  780. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  781. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  782. }
  783. /* Disable interrupts */
  784. ath9k_hw_disable_interrupts(ah);
  785. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  786. ath_stoprecv(sc); /* turn off frame recv */
  787. ath_flushrecv(sc); /* flush recv queue */
  788. if (!ah->curchan)
  789. ah->curchan = ath_get_curchannel(sc, hw);
  790. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  791. if (r) {
  792. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  793. "Unable to reset channel (%u MHz), "
  794. "reset status %d\n",
  795. channel->center_freq, r);
  796. }
  797. ath9k_hw_phy_disable(ah);
  798. ath9k_hw_configpcipowersave(ah, 1, 1);
  799. spin_unlock_bh(&sc->sc_pcu_lock);
  800. ath9k_ps_restore(sc);
  801. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  802. }
  803. int ath_reset(struct ath_softc *sc, bool retry_tx)
  804. {
  805. struct ath_hw *ah = sc->sc_ah;
  806. struct ath_common *common = ath9k_hw_common(ah);
  807. struct ieee80211_hw *hw = sc->hw;
  808. int r;
  809. /* Stop ANI */
  810. del_timer_sync(&common->ani.timer);
  811. spin_lock_bh(&sc->sc_pcu_lock);
  812. ieee80211_stop_queues(hw);
  813. ath9k_hw_disable_interrupts(ah);
  814. ath_drain_all_txq(sc, retry_tx);
  815. ath_stoprecv(sc);
  816. ath_flushrecv(sc);
  817. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
  818. if (r)
  819. ath_print(common, ATH_DBG_FATAL,
  820. "Unable to reset hardware; reset status %d\n", r);
  821. if (ath_startrecv(sc) != 0)
  822. ath_print(common, ATH_DBG_FATAL,
  823. "Unable to start recv logic\n");
  824. /*
  825. * We may be doing a reset in response to a request
  826. * that changes the channel so update any state that
  827. * might change as a result.
  828. */
  829. ath_update_txpow(sc);
  830. if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
  831. ath_beacon_config(sc, NULL); /* restart beacons */
  832. ath9k_hw_set_interrupts(ah, ah->imask);
  833. if (retry_tx) {
  834. int i;
  835. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  836. if (ATH_TXQ_SETUP(sc, i)) {
  837. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  838. ath_txq_schedule(sc, &sc->tx.txq[i]);
  839. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  840. }
  841. }
  842. }
  843. ieee80211_wake_queues(hw);
  844. spin_unlock_bh(&sc->sc_pcu_lock);
  845. /* Start ANI */
  846. ath_start_ani(common);
  847. return r;
  848. }
  849. /* XXX: Remove me once we don't depend on ath9k_channel for all
  850. * this redundant data */
  851. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  852. struct ath9k_channel *ichan)
  853. {
  854. struct ieee80211_channel *chan = hw->conf.channel;
  855. struct ieee80211_conf *conf = &hw->conf;
  856. ichan->channel = chan->center_freq;
  857. ichan->chan = chan;
  858. if (chan->band == IEEE80211_BAND_2GHZ) {
  859. ichan->chanmode = CHANNEL_G;
  860. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  861. } else {
  862. ichan->chanmode = CHANNEL_A;
  863. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  864. }
  865. if (conf_is_ht(conf))
  866. ichan->chanmode = ath_get_extchanmode(sc, chan,
  867. conf->channel_type);
  868. }
  869. /**********************/
  870. /* mac80211 callbacks */
  871. /**********************/
  872. static int ath9k_start(struct ieee80211_hw *hw)
  873. {
  874. struct ath_wiphy *aphy = hw->priv;
  875. struct ath_softc *sc = aphy->sc;
  876. struct ath_hw *ah = sc->sc_ah;
  877. struct ath_common *common = ath9k_hw_common(ah);
  878. struct ieee80211_channel *curchan = hw->conf.channel;
  879. struct ath9k_channel *init_channel;
  880. int r;
  881. ath_print(common, ATH_DBG_CONFIG,
  882. "Starting driver with initial channel: %d MHz\n",
  883. curchan->center_freq);
  884. mutex_lock(&sc->mutex);
  885. if (ath9k_wiphy_started(sc)) {
  886. if (sc->chan_idx == curchan->hw_value) {
  887. /*
  888. * Already on the operational channel, the new wiphy
  889. * can be marked active.
  890. */
  891. aphy->state = ATH_WIPHY_ACTIVE;
  892. ieee80211_wake_queues(hw);
  893. } else {
  894. /*
  895. * Another wiphy is on another channel, start the new
  896. * wiphy in paused state.
  897. */
  898. aphy->state = ATH_WIPHY_PAUSED;
  899. ieee80211_stop_queues(hw);
  900. }
  901. mutex_unlock(&sc->mutex);
  902. return 0;
  903. }
  904. aphy->state = ATH_WIPHY_ACTIVE;
  905. /* setup initial channel */
  906. sc->chan_idx = curchan->hw_value;
  907. init_channel = ath_get_curchannel(sc, hw);
  908. /* Reset SERDES registers */
  909. ath9k_hw_configpcipowersave(ah, 0, 0);
  910. /*
  911. * The basic interface to setting the hardware in a good
  912. * state is ``reset''. On return the hardware is known to
  913. * be powered up and with interrupts disabled. This must
  914. * be followed by initialization of the appropriate bits
  915. * and then setup of the interrupt mask.
  916. */
  917. spin_lock_bh(&sc->sc_pcu_lock);
  918. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  919. if (r) {
  920. ath_print(common, ATH_DBG_FATAL,
  921. "Unable to reset hardware; reset status %d "
  922. "(freq %u MHz)\n", r,
  923. curchan->center_freq);
  924. spin_unlock_bh(&sc->sc_pcu_lock);
  925. goto mutex_unlock;
  926. }
  927. /*
  928. * This is needed only to setup initial state
  929. * but it's best done after a reset.
  930. */
  931. ath_update_txpow(sc);
  932. /*
  933. * Setup the hardware after reset:
  934. * The receive engine is set going.
  935. * Frame transmit is handled entirely
  936. * in the frame output path; there's nothing to do
  937. * here except setup the interrupt mask.
  938. */
  939. if (ath_startrecv(sc) != 0) {
  940. ath_print(common, ATH_DBG_FATAL,
  941. "Unable to start recv logic\n");
  942. r = -EIO;
  943. spin_unlock_bh(&sc->sc_pcu_lock);
  944. goto mutex_unlock;
  945. }
  946. spin_unlock_bh(&sc->sc_pcu_lock);
  947. /* Setup our intr mask. */
  948. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  949. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  950. ATH9K_INT_GLOBAL;
  951. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  952. ah->imask |= ATH9K_INT_RXHP |
  953. ATH9K_INT_RXLP |
  954. ATH9K_INT_BB_WATCHDOG;
  955. else
  956. ah->imask |= ATH9K_INT_RX;
  957. ah->imask |= ATH9K_INT_GTT;
  958. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  959. ah->imask |= ATH9K_INT_CST;
  960. sc->sc_flags &= ~SC_OP_INVALID;
  961. sc->sc_ah->is_monitoring = false;
  962. /* Disable BMISS interrupt when we're not associated */
  963. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  964. ath9k_hw_set_interrupts(ah, ah->imask);
  965. ieee80211_wake_queues(hw);
  966. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  967. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  968. !ah->btcoex_hw.enabled) {
  969. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  970. AR_STOMP_LOW_WLAN_WGHT);
  971. ath9k_hw_btcoex_enable(ah);
  972. if (common->bus_ops->bt_coex_prep)
  973. common->bus_ops->bt_coex_prep(common);
  974. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  975. ath9k_btcoex_timer_resume(sc);
  976. }
  977. pm_qos_update_request(&ath9k_pm_qos_req, 55);
  978. mutex_unlock:
  979. mutex_unlock(&sc->mutex);
  980. return r;
  981. }
  982. static int ath9k_tx(struct ieee80211_hw *hw,
  983. struct sk_buff *skb)
  984. {
  985. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  986. struct ath_wiphy *aphy = hw->priv;
  987. struct ath_softc *sc = aphy->sc;
  988. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  989. struct ath_tx_control txctl;
  990. int padpos, padsize;
  991. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  992. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  993. ath_print(common, ATH_DBG_XMIT,
  994. "ath9k: %s: TX in unexpected wiphy state "
  995. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  996. goto exit;
  997. }
  998. if (sc->ps_enabled) {
  999. /*
  1000. * mac80211 does not set PM field for normal data frames, so we
  1001. * need to update that based on the current PS mode.
  1002. */
  1003. if (ieee80211_is_data(hdr->frame_control) &&
  1004. !ieee80211_is_nullfunc(hdr->frame_control) &&
  1005. !ieee80211_has_pm(hdr->frame_control)) {
  1006. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  1007. "while in PS mode\n");
  1008. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  1009. }
  1010. }
  1011. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  1012. /*
  1013. * We are using PS-Poll and mac80211 can request TX while in
  1014. * power save mode. Need to wake up hardware for the TX to be
  1015. * completed and if needed, also for RX of buffered frames.
  1016. */
  1017. ath9k_ps_wakeup(sc);
  1018. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  1019. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1020. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1021. ath_print(common, ATH_DBG_PS,
  1022. "Sending PS-Poll to pick a buffered frame\n");
  1023. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  1024. } else {
  1025. ath_print(common, ATH_DBG_PS,
  1026. "Wake up to complete TX\n");
  1027. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1028. }
  1029. /*
  1030. * The actual restore operation will happen only after
  1031. * the sc_flags bit is cleared. We are just dropping
  1032. * the ps_usecount here.
  1033. */
  1034. ath9k_ps_restore(sc);
  1035. }
  1036. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1037. /*
  1038. * As a temporary workaround, assign seq# here; this will likely need
  1039. * to be cleaned up to work better with Beacon transmission and virtual
  1040. * BSSes.
  1041. */
  1042. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1043. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1044. sc->tx.seq_no += 0x10;
  1045. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1046. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1047. }
  1048. /* Add the padding after the header if this is not already done */
  1049. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1050. padsize = padpos & 3;
  1051. if (padsize && skb->len>padpos) {
  1052. if (skb_headroom(skb) < padsize)
  1053. return -1;
  1054. skb_push(skb, padsize);
  1055. memmove(skb->data, skb->data + padsize, padpos);
  1056. }
  1057. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  1058. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1059. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1060. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1061. goto exit;
  1062. }
  1063. return 0;
  1064. exit:
  1065. dev_kfree_skb_any(skb);
  1066. return 0;
  1067. }
  1068. static void ath9k_stop(struct ieee80211_hw *hw)
  1069. {
  1070. struct ath_wiphy *aphy = hw->priv;
  1071. struct ath_softc *sc = aphy->sc;
  1072. struct ath_hw *ah = sc->sc_ah;
  1073. struct ath_common *common = ath9k_hw_common(ah);
  1074. int i;
  1075. mutex_lock(&sc->mutex);
  1076. aphy->state = ATH_WIPHY_INACTIVE;
  1077. if (led_blink)
  1078. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1079. cancel_delayed_work_sync(&sc->tx_complete_work);
  1080. cancel_work_sync(&sc->paprd_work);
  1081. cancel_work_sync(&sc->hw_check_work);
  1082. for (i = 0; i < sc->num_sec_wiphy; i++) {
  1083. if (sc->sec_wiphy[i])
  1084. break;
  1085. }
  1086. if (i == sc->num_sec_wiphy) {
  1087. cancel_delayed_work_sync(&sc->wiphy_work);
  1088. cancel_work_sync(&sc->chan_work);
  1089. }
  1090. if (sc->sc_flags & SC_OP_INVALID) {
  1091. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1092. mutex_unlock(&sc->mutex);
  1093. return;
  1094. }
  1095. if (ath9k_wiphy_started(sc)) {
  1096. mutex_unlock(&sc->mutex);
  1097. return; /* another wiphy still in use */
  1098. }
  1099. /* Ensure HW is awake when we try to shut it down. */
  1100. ath9k_ps_wakeup(sc);
  1101. if (ah->btcoex_hw.enabled) {
  1102. ath9k_hw_btcoex_disable(ah);
  1103. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1104. ath9k_btcoex_timer_pause(sc);
  1105. }
  1106. spin_lock_bh(&sc->sc_pcu_lock);
  1107. /* make sure h/w will not generate any interrupt
  1108. * before setting the invalid flag. */
  1109. ath9k_hw_disable_interrupts(ah);
  1110. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1111. ath_drain_all_txq(sc, false);
  1112. ath_stoprecv(sc);
  1113. ath9k_hw_phy_disable(ah);
  1114. } else
  1115. sc->rx.rxlink = NULL;
  1116. /* disable HAL and put h/w to sleep */
  1117. ath9k_hw_disable(ah);
  1118. ath9k_hw_configpcipowersave(ah, 1, 1);
  1119. spin_unlock_bh(&sc->sc_pcu_lock);
  1120. ath9k_ps_restore(sc);
  1121. /* Finally, put the chip in FULL SLEEP mode */
  1122. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1123. sc->sc_flags |= SC_OP_INVALID;
  1124. pm_qos_update_request(&ath9k_pm_qos_req, PM_QOS_DEFAULT_VALUE);
  1125. mutex_unlock(&sc->mutex);
  1126. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1127. }
  1128. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1129. struct ieee80211_vif *vif)
  1130. {
  1131. struct ath_wiphy *aphy = hw->priv;
  1132. struct ath_softc *sc = aphy->sc;
  1133. struct ath_hw *ah = sc->sc_ah;
  1134. struct ath_common *common = ath9k_hw_common(ah);
  1135. struct ath_vif *avp = (void *)vif->drv_priv;
  1136. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1137. int ret = 0;
  1138. mutex_lock(&sc->mutex);
  1139. switch (vif->type) {
  1140. case NL80211_IFTYPE_STATION:
  1141. ic_opmode = NL80211_IFTYPE_STATION;
  1142. break;
  1143. case NL80211_IFTYPE_WDS:
  1144. ic_opmode = NL80211_IFTYPE_WDS;
  1145. break;
  1146. case NL80211_IFTYPE_ADHOC:
  1147. case NL80211_IFTYPE_AP:
  1148. case NL80211_IFTYPE_MESH_POINT:
  1149. if (sc->nbcnvifs >= ATH_BCBUF) {
  1150. ret = -ENOBUFS;
  1151. goto out;
  1152. }
  1153. ic_opmode = vif->type;
  1154. break;
  1155. default:
  1156. ath_print(common, ATH_DBG_FATAL,
  1157. "Interface type %d not yet supported\n", vif->type);
  1158. ret = -EOPNOTSUPP;
  1159. goto out;
  1160. }
  1161. ath_print(common, ATH_DBG_CONFIG,
  1162. "Attach a VIF of type: %d\n", ic_opmode);
  1163. /* Set the VIF opmode */
  1164. avp->av_opmode = ic_opmode;
  1165. avp->av_bslot = -1;
  1166. sc->nvifs++;
  1167. ath9k_set_bssid_mask(hw, vif);
  1168. if (sc->nvifs > 1)
  1169. goto out; /* skip global settings for secondary vif */
  1170. if (ic_opmode == NL80211_IFTYPE_AP) {
  1171. ath9k_hw_set_tsfadjust(ah, 1);
  1172. sc->sc_flags |= SC_OP_TSF_RESET;
  1173. }
  1174. /* Set the device opmode */
  1175. ah->opmode = ic_opmode;
  1176. /*
  1177. * Enable MIB interrupts when there are hardware phy counters.
  1178. * Note we only do this (at the moment) for station mode.
  1179. */
  1180. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1181. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1182. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1183. if (ah->config.enable_ani)
  1184. ah->imask |= ATH9K_INT_MIB;
  1185. ah->imask |= ATH9K_INT_TSFOOR;
  1186. }
  1187. ath9k_hw_set_interrupts(ah, ah->imask);
  1188. if (vif->type == NL80211_IFTYPE_AP ||
  1189. vif->type == NL80211_IFTYPE_ADHOC) {
  1190. sc->sc_flags |= SC_OP_ANI_RUN;
  1191. ath_start_ani(common);
  1192. }
  1193. out:
  1194. mutex_unlock(&sc->mutex);
  1195. return ret;
  1196. }
  1197. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1198. struct ieee80211_vif *vif)
  1199. {
  1200. struct ath_wiphy *aphy = hw->priv;
  1201. struct ath_softc *sc = aphy->sc;
  1202. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1203. struct ath_vif *avp = (void *)vif->drv_priv;
  1204. int i;
  1205. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1206. mutex_lock(&sc->mutex);
  1207. /* Stop ANI */
  1208. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1209. del_timer_sync(&common->ani.timer);
  1210. /* Reclaim beacon resources */
  1211. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1212. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1213. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1214. ath9k_ps_wakeup(sc);
  1215. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1216. ath9k_ps_restore(sc);
  1217. }
  1218. ath_beacon_return(sc, avp);
  1219. sc->sc_flags &= ~SC_OP_BEACONS;
  1220. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1221. if (sc->beacon.bslot[i] == vif) {
  1222. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1223. "slot\n", __func__);
  1224. sc->beacon.bslot[i] = NULL;
  1225. sc->beacon.bslot_aphy[i] = NULL;
  1226. }
  1227. }
  1228. sc->nvifs--;
  1229. mutex_unlock(&sc->mutex);
  1230. }
  1231. static void ath9k_enable_ps(struct ath_softc *sc)
  1232. {
  1233. struct ath_hw *ah = sc->sc_ah;
  1234. sc->ps_enabled = true;
  1235. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1236. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1237. ah->imask |= ATH9K_INT_TIM_TIMER;
  1238. ath9k_hw_set_interrupts(ah, ah->imask);
  1239. }
  1240. ath9k_hw_setrxabort(ah, 1);
  1241. }
  1242. }
  1243. static void ath9k_disable_ps(struct ath_softc *sc)
  1244. {
  1245. struct ath_hw *ah = sc->sc_ah;
  1246. sc->ps_enabled = false;
  1247. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1248. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1249. ath9k_hw_setrxabort(ah, 0);
  1250. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1251. PS_WAIT_FOR_CAB |
  1252. PS_WAIT_FOR_PSPOLL_DATA |
  1253. PS_WAIT_FOR_TX_ACK);
  1254. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1255. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1256. ath9k_hw_set_interrupts(ah, ah->imask);
  1257. }
  1258. }
  1259. }
  1260. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1261. {
  1262. struct ath_wiphy *aphy = hw->priv;
  1263. struct ath_softc *sc = aphy->sc;
  1264. struct ath_hw *ah = sc->sc_ah;
  1265. struct ath_common *common = ath9k_hw_common(ah);
  1266. struct ieee80211_conf *conf = &hw->conf;
  1267. bool disable_radio;
  1268. mutex_lock(&sc->mutex);
  1269. /*
  1270. * Leave this as the first check because we need to turn on the
  1271. * radio if it was disabled before prior to processing the rest
  1272. * of the changes. Likewise we must only disable the radio towards
  1273. * the end.
  1274. */
  1275. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1276. bool enable_radio;
  1277. bool all_wiphys_idle;
  1278. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1279. spin_lock_bh(&sc->wiphy_lock);
  1280. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1281. ath9k_set_wiphy_idle(aphy, idle);
  1282. enable_radio = (!idle && all_wiphys_idle);
  1283. /*
  1284. * After we unlock here its possible another wiphy
  1285. * can be re-renabled so to account for that we will
  1286. * only disable the radio toward the end of this routine
  1287. * if by then all wiphys are still idle.
  1288. */
  1289. spin_unlock_bh(&sc->wiphy_lock);
  1290. if (enable_radio) {
  1291. sc->ps_idle = false;
  1292. ath_radio_enable(sc, hw);
  1293. ath_print(common, ATH_DBG_CONFIG,
  1294. "not-idle: enabling radio\n");
  1295. }
  1296. }
  1297. /*
  1298. * We just prepare to enable PS. We have to wait until our AP has
  1299. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1300. * those ACKs and end up retransmitting the same null data frames.
  1301. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1302. */
  1303. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1304. unsigned long flags;
  1305. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1306. if (conf->flags & IEEE80211_CONF_PS)
  1307. ath9k_enable_ps(sc);
  1308. else
  1309. ath9k_disable_ps(sc);
  1310. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1311. }
  1312. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1313. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1314. ath_print(common, ATH_DBG_CONFIG,
  1315. "Monitor mode is enabled\n");
  1316. sc->sc_ah->is_monitoring = true;
  1317. } else {
  1318. ath_print(common, ATH_DBG_CONFIG,
  1319. "Monitor mode is disabled\n");
  1320. sc->sc_ah->is_monitoring = false;
  1321. }
  1322. }
  1323. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1324. struct ieee80211_channel *curchan = hw->conf.channel;
  1325. int pos = curchan->hw_value;
  1326. int old_pos = -1;
  1327. unsigned long flags;
  1328. if (ah->curchan)
  1329. old_pos = ah->curchan - &ah->channels[0];
  1330. aphy->chan_idx = pos;
  1331. aphy->chan_is_ht = conf_is_ht(conf);
  1332. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1333. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1334. else
  1335. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1336. if (aphy->state == ATH_WIPHY_SCAN ||
  1337. aphy->state == ATH_WIPHY_ACTIVE)
  1338. ath9k_wiphy_pause_all_forced(sc, aphy);
  1339. else {
  1340. /*
  1341. * Do not change operational channel based on a paused
  1342. * wiphy changes.
  1343. */
  1344. goto skip_chan_change;
  1345. }
  1346. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1347. curchan->center_freq);
  1348. /* XXX: remove me eventualy */
  1349. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1350. ath_update_chainmask(sc, conf_is_ht(conf));
  1351. /* update survey stats for the old channel before switching */
  1352. spin_lock_irqsave(&common->cc_lock, flags);
  1353. ath_update_survey_stats(sc);
  1354. spin_unlock_irqrestore(&common->cc_lock, flags);
  1355. /*
  1356. * If the operating channel changes, change the survey in-use flags
  1357. * along with it.
  1358. * Reset the survey data for the new channel, unless we're switching
  1359. * back to the operating channel from an off-channel operation.
  1360. */
  1361. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1362. sc->cur_survey != &sc->survey[pos]) {
  1363. if (sc->cur_survey)
  1364. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1365. sc->cur_survey = &sc->survey[pos];
  1366. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1367. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1368. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1369. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1370. }
  1371. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1372. ath_print(common, ATH_DBG_FATAL,
  1373. "Unable to set channel\n");
  1374. mutex_unlock(&sc->mutex);
  1375. return -EINVAL;
  1376. }
  1377. /*
  1378. * The most recent snapshot of channel->noisefloor for the old
  1379. * channel is only available after the hardware reset. Copy it to
  1380. * the survey stats now.
  1381. */
  1382. if (old_pos >= 0)
  1383. ath_update_survey_nf(sc, old_pos);
  1384. }
  1385. skip_chan_change:
  1386. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1387. sc->config.txpowlimit = 2 * conf->power_level;
  1388. ath_update_txpow(sc);
  1389. }
  1390. spin_lock_bh(&sc->wiphy_lock);
  1391. disable_radio = ath9k_all_wiphys_idle(sc);
  1392. spin_unlock_bh(&sc->wiphy_lock);
  1393. if (disable_radio) {
  1394. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1395. sc->ps_idle = true;
  1396. ath_radio_disable(sc, hw);
  1397. }
  1398. mutex_unlock(&sc->mutex);
  1399. return 0;
  1400. }
  1401. #define SUPPORTED_FILTERS \
  1402. (FIF_PROMISC_IN_BSS | \
  1403. FIF_ALLMULTI | \
  1404. FIF_CONTROL | \
  1405. FIF_PSPOLL | \
  1406. FIF_OTHER_BSS | \
  1407. FIF_BCN_PRBRESP_PROMISC | \
  1408. FIF_PROBE_REQ | \
  1409. FIF_FCSFAIL)
  1410. /* FIXME: sc->sc_full_reset ? */
  1411. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1412. unsigned int changed_flags,
  1413. unsigned int *total_flags,
  1414. u64 multicast)
  1415. {
  1416. struct ath_wiphy *aphy = hw->priv;
  1417. struct ath_softc *sc = aphy->sc;
  1418. u32 rfilt;
  1419. changed_flags &= SUPPORTED_FILTERS;
  1420. *total_flags &= SUPPORTED_FILTERS;
  1421. sc->rx.rxfilter = *total_flags;
  1422. ath9k_ps_wakeup(sc);
  1423. rfilt = ath_calcrxfilter(sc);
  1424. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1425. ath9k_ps_restore(sc);
  1426. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1427. "Set HW RX filter: 0x%x\n", rfilt);
  1428. }
  1429. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1430. struct ieee80211_vif *vif,
  1431. struct ieee80211_sta *sta)
  1432. {
  1433. struct ath_wiphy *aphy = hw->priv;
  1434. struct ath_softc *sc = aphy->sc;
  1435. ath_node_attach(sc, sta);
  1436. return 0;
  1437. }
  1438. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1439. struct ieee80211_vif *vif,
  1440. struct ieee80211_sta *sta)
  1441. {
  1442. struct ath_wiphy *aphy = hw->priv;
  1443. struct ath_softc *sc = aphy->sc;
  1444. ath_node_detach(sc, sta);
  1445. return 0;
  1446. }
  1447. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1448. const struct ieee80211_tx_queue_params *params)
  1449. {
  1450. struct ath_wiphy *aphy = hw->priv;
  1451. struct ath_softc *sc = aphy->sc;
  1452. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1453. struct ath_txq *txq;
  1454. struct ath9k_tx_queue_info qi;
  1455. int ret = 0;
  1456. if (queue >= WME_NUM_AC)
  1457. return 0;
  1458. txq = sc->tx.txq_map[queue];
  1459. mutex_lock(&sc->mutex);
  1460. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1461. qi.tqi_aifs = params->aifs;
  1462. qi.tqi_cwmin = params->cw_min;
  1463. qi.tqi_cwmax = params->cw_max;
  1464. qi.tqi_burstTime = params->txop;
  1465. ath_print(common, ATH_DBG_CONFIG,
  1466. "Configure tx [queue/halq] [%d/%d], "
  1467. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1468. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1469. params->cw_max, params->txop);
  1470. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1471. if (ret)
  1472. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1473. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1474. if (queue == WME_AC_BE && !ret)
  1475. ath_beaconq_config(sc);
  1476. mutex_unlock(&sc->mutex);
  1477. return ret;
  1478. }
  1479. static int ath9k_set_key(struct ieee80211_hw *hw,
  1480. enum set_key_cmd cmd,
  1481. struct ieee80211_vif *vif,
  1482. struct ieee80211_sta *sta,
  1483. struct ieee80211_key_conf *key)
  1484. {
  1485. struct ath_wiphy *aphy = hw->priv;
  1486. struct ath_softc *sc = aphy->sc;
  1487. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1488. int ret = 0;
  1489. if (modparam_nohwcrypt)
  1490. return -ENOSPC;
  1491. mutex_lock(&sc->mutex);
  1492. ath9k_ps_wakeup(sc);
  1493. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1494. switch (cmd) {
  1495. case SET_KEY:
  1496. ret = ath_key_config(common, vif, sta, key);
  1497. if (ret >= 0) {
  1498. key->hw_key_idx = ret;
  1499. /* push IV and Michael MIC generation to stack */
  1500. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1501. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1502. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1503. if (sc->sc_ah->sw_mgmt_crypto &&
  1504. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1505. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1506. ret = 0;
  1507. }
  1508. break;
  1509. case DISABLE_KEY:
  1510. ath_key_delete(common, key);
  1511. break;
  1512. default:
  1513. ret = -EINVAL;
  1514. }
  1515. ath9k_ps_restore(sc);
  1516. mutex_unlock(&sc->mutex);
  1517. return ret;
  1518. }
  1519. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1520. struct ieee80211_vif *vif,
  1521. struct ieee80211_bss_conf *bss_conf,
  1522. u32 changed)
  1523. {
  1524. struct ath_wiphy *aphy = hw->priv;
  1525. struct ath_softc *sc = aphy->sc;
  1526. struct ath_hw *ah = sc->sc_ah;
  1527. struct ath_common *common = ath9k_hw_common(ah);
  1528. struct ath_vif *avp = (void *)vif->drv_priv;
  1529. int slottime;
  1530. int error;
  1531. mutex_lock(&sc->mutex);
  1532. if (changed & BSS_CHANGED_BSSID) {
  1533. /* Set BSSID */
  1534. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1535. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1536. common->curaid = 0;
  1537. ath9k_hw_write_associd(ah);
  1538. /* Set aggregation protection mode parameters */
  1539. sc->config.ath_aggr_prot = 0;
  1540. /* Only legacy IBSS for now */
  1541. if (vif->type == NL80211_IFTYPE_ADHOC)
  1542. ath_update_chainmask(sc, 0);
  1543. ath_print(common, ATH_DBG_CONFIG,
  1544. "BSSID: %pM aid: 0x%x\n",
  1545. common->curbssid, common->curaid);
  1546. /* need to reconfigure the beacon */
  1547. sc->sc_flags &= ~SC_OP_BEACONS ;
  1548. }
  1549. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1550. if ((changed & BSS_CHANGED_BEACON) ||
  1551. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1552. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1553. error = ath_beacon_alloc(aphy, vif);
  1554. if (!error)
  1555. ath_beacon_config(sc, vif);
  1556. }
  1557. if (changed & BSS_CHANGED_ERP_SLOT) {
  1558. if (bss_conf->use_short_slot)
  1559. slottime = 9;
  1560. else
  1561. slottime = 20;
  1562. if (vif->type == NL80211_IFTYPE_AP) {
  1563. /*
  1564. * Defer update, so that connected stations can adjust
  1565. * their settings at the same time.
  1566. * See beacon.c for more details
  1567. */
  1568. sc->beacon.slottime = slottime;
  1569. sc->beacon.updateslot = UPDATE;
  1570. } else {
  1571. ah->slottime = slottime;
  1572. ath9k_hw_init_global_settings(ah);
  1573. }
  1574. }
  1575. /* Disable transmission of beacons */
  1576. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1577. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1578. if (changed & BSS_CHANGED_BEACON_INT) {
  1579. sc->beacon_interval = bss_conf->beacon_int;
  1580. /*
  1581. * In case of AP mode, the HW TSF has to be reset
  1582. * when the beacon interval changes.
  1583. */
  1584. if (vif->type == NL80211_IFTYPE_AP) {
  1585. sc->sc_flags |= SC_OP_TSF_RESET;
  1586. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1587. error = ath_beacon_alloc(aphy, vif);
  1588. if (!error)
  1589. ath_beacon_config(sc, vif);
  1590. } else {
  1591. ath_beacon_config(sc, vif);
  1592. }
  1593. }
  1594. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1595. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1596. bss_conf->use_short_preamble);
  1597. if (bss_conf->use_short_preamble)
  1598. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1599. else
  1600. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1601. }
  1602. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1603. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1604. bss_conf->use_cts_prot);
  1605. if (bss_conf->use_cts_prot &&
  1606. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1607. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1608. else
  1609. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1610. }
  1611. if (changed & BSS_CHANGED_ASSOC) {
  1612. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1613. bss_conf->assoc);
  1614. ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
  1615. }
  1616. mutex_unlock(&sc->mutex);
  1617. }
  1618. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1619. {
  1620. u64 tsf;
  1621. struct ath_wiphy *aphy = hw->priv;
  1622. struct ath_softc *sc = aphy->sc;
  1623. mutex_lock(&sc->mutex);
  1624. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1625. mutex_unlock(&sc->mutex);
  1626. return tsf;
  1627. }
  1628. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1629. {
  1630. struct ath_wiphy *aphy = hw->priv;
  1631. struct ath_softc *sc = aphy->sc;
  1632. mutex_lock(&sc->mutex);
  1633. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1634. mutex_unlock(&sc->mutex);
  1635. }
  1636. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1637. {
  1638. struct ath_wiphy *aphy = hw->priv;
  1639. struct ath_softc *sc = aphy->sc;
  1640. mutex_lock(&sc->mutex);
  1641. ath9k_ps_wakeup(sc);
  1642. ath9k_hw_reset_tsf(sc->sc_ah);
  1643. ath9k_ps_restore(sc);
  1644. mutex_unlock(&sc->mutex);
  1645. }
  1646. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1647. struct ieee80211_vif *vif,
  1648. enum ieee80211_ampdu_mlme_action action,
  1649. struct ieee80211_sta *sta,
  1650. u16 tid, u16 *ssn)
  1651. {
  1652. struct ath_wiphy *aphy = hw->priv;
  1653. struct ath_softc *sc = aphy->sc;
  1654. int ret = 0;
  1655. local_bh_disable();
  1656. switch (action) {
  1657. case IEEE80211_AMPDU_RX_START:
  1658. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1659. ret = -ENOTSUPP;
  1660. break;
  1661. case IEEE80211_AMPDU_RX_STOP:
  1662. break;
  1663. case IEEE80211_AMPDU_TX_START:
  1664. ath9k_ps_wakeup(sc);
  1665. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1666. if (!ret)
  1667. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1668. ath9k_ps_restore(sc);
  1669. break;
  1670. case IEEE80211_AMPDU_TX_STOP:
  1671. ath9k_ps_wakeup(sc);
  1672. ath_tx_aggr_stop(sc, sta, tid);
  1673. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1674. ath9k_ps_restore(sc);
  1675. break;
  1676. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1677. ath9k_ps_wakeup(sc);
  1678. ath_tx_aggr_resume(sc, sta, tid);
  1679. ath9k_ps_restore(sc);
  1680. break;
  1681. default:
  1682. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1683. "Unknown AMPDU action\n");
  1684. }
  1685. local_bh_enable();
  1686. return ret;
  1687. }
  1688. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1689. struct survey_info *survey)
  1690. {
  1691. struct ath_wiphy *aphy = hw->priv;
  1692. struct ath_softc *sc = aphy->sc;
  1693. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1694. struct ieee80211_supported_band *sband;
  1695. struct ieee80211_channel *chan;
  1696. unsigned long flags;
  1697. int pos;
  1698. spin_lock_irqsave(&common->cc_lock, flags);
  1699. if (idx == 0)
  1700. ath_update_survey_stats(sc);
  1701. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1702. if (sband && idx >= sband->n_channels) {
  1703. idx -= sband->n_channels;
  1704. sband = NULL;
  1705. }
  1706. if (!sband)
  1707. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1708. if (!sband || idx >= sband->n_channels) {
  1709. spin_unlock_irqrestore(&common->cc_lock, flags);
  1710. return -ENOENT;
  1711. }
  1712. chan = &sband->channels[idx];
  1713. pos = chan->hw_value;
  1714. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1715. survey->channel = chan;
  1716. spin_unlock_irqrestore(&common->cc_lock, flags);
  1717. return 0;
  1718. }
  1719. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1720. {
  1721. struct ath_wiphy *aphy = hw->priv;
  1722. struct ath_softc *sc = aphy->sc;
  1723. mutex_lock(&sc->mutex);
  1724. if (ath9k_wiphy_scanning(sc)) {
  1725. /*
  1726. * There is a race here in mac80211 but fixing it requires
  1727. * we revisit how we handle the scan complete callback.
  1728. * After mac80211 fixes we will not have configured hardware
  1729. * to the home channel nor would we have configured the RX
  1730. * filter yet.
  1731. */
  1732. mutex_unlock(&sc->mutex);
  1733. return;
  1734. }
  1735. aphy->state = ATH_WIPHY_SCAN;
  1736. ath9k_wiphy_pause_all_forced(sc, aphy);
  1737. mutex_unlock(&sc->mutex);
  1738. }
  1739. /*
  1740. * XXX: this requires a revisit after the driver
  1741. * scan_complete gets moved to another place/removed in mac80211.
  1742. */
  1743. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1744. {
  1745. struct ath_wiphy *aphy = hw->priv;
  1746. struct ath_softc *sc = aphy->sc;
  1747. mutex_lock(&sc->mutex);
  1748. aphy->state = ATH_WIPHY_ACTIVE;
  1749. mutex_unlock(&sc->mutex);
  1750. }
  1751. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1752. {
  1753. struct ath_wiphy *aphy = hw->priv;
  1754. struct ath_softc *sc = aphy->sc;
  1755. struct ath_hw *ah = sc->sc_ah;
  1756. mutex_lock(&sc->mutex);
  1757. ah->coverage_class = coverage_class;
  1758. ath9k_hw_init_global_settings(ah);
  1759. mutex_unlock(&sc->mutex);
  1760. }
  1761. struct ieee80211_ops ath9k_ops = {
  1762. .tx = ath9k_tx,
  1763. .start = ath9k_start,
  1764. .stop = ath9k_stop,
  1765. .add_interface = ath9k_add_interface,
  1766. .remove_interface = ath9k_remove_interface,
  1767. .config = ath9k_config,
  1768. .configure_filter = ath9k_configure_filter,
  1769. .sta_add = ath9k_sta_add,
  1770. .sta_remove = ath9k_sta_remove,
  1771. .conf_tx = ath9k_conf_tx,
  1772. .bss_info_changed = ath9k_bss_info_changed,
  1773. .set_key = ath9k_set_key,
  1774. .get_tsf = ath9k_get_tsf,
  1775. .set_tsf = ath9k_set_tsf,
  1776. .reset_tsf = ath9k_reset_tsf,
  1777. .ampdu_action = ath9k_ampdu_action,
  1778. .get_survey = ath9k_get_survey,
  1779. .sw_scan_start = ath9k_sw_scan_start,
  1780. .sw_scan_complete = ath9k_sw_scan_complete,
  1781. .rfkill_poll = ath9k_rfkill_poll_state,
  1782. .set_coverage_class = ath9k_set_coverage_class,
  1783. };