r8a66597-udc.c 42 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/clk.h>
  18. #include <linux/err.h>
  19. #include <linux/slab.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include "r8a66597-udc.h"
  23. #define DRIVER_VERSION "2009-08-18"
  24. static const char udc_name[] = "r8a66597_udc";
  25. static const char *r8a66597_ep_name[] = {
  26. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  27. "ep8", "ep9",
  28. };
  29. static void init_controller(struct r8a66597 *r8a66597);
  30. static void disable_controller(struct r8a66597 *r8a66597);
  31. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  32. static void irq_packet_write(struct r8a66597_ep *ep,
  33. struct r8a66597_request *req);
  34. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  35. gfp_t gfp_flags);
  36. static void transfer_complete(struct r8a66597_ep *ep,
  37. struct r8a66597_request *req, int status);
  38. /*-------------------------------------------------------------------------*/
  39. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  40. {
  41. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  42. }
  43. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  44. unsigned long reg)
  45. {
  46. u16 tmp;
  47. tmp = r8a66597_read(r8a66597, INTENB0);
  48. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  49. INTENB0);
  50. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  51. r8a66597_write(r8a66597, tmp, INTENB0);
  52. }
  53. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  54. unsigned long reg)
  55. {
  56. u16 tmp;
  57. tmp = r8a66597_read(r8a66597, INTENB0);
  58. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  59. INTENB0);
  60. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  61. r8a66597_write(r8a66597, tmp, INTENB0);
  62. }
  63. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  64. {
  65. r8a66597_bset(r8a66597, CTRE, INTENB0);
  66. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  67. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  68. }
  69. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  70. __releases(r8a66597->lock)
  71. __acquires(r8a66597->lock)
  72. {
  73. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  74. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  75. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  76. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  77. spin_unlock(&r8a66597->lock);
  78. r8a66597->driver->disconnect(&r8a66597->gadget);
  79. spin_lock(&r8a66597->lock);
  80. disable_controller(r8a66597);
  81. init_controller(r8a66597);
  82. r8a66597_bset(r8a66597, VBSE, INTENB0);
  83. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  84. }
  85. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  86. {
  87. u16 pid = 0;
  88. unsigned long offset;
  89. if (pipenum == 0)
  90. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  91. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  92. offset = get_pipectr_addr(pipenum);
  93. pid = r8a66597_read(r8a66597, offset) & PID;
  94. } else
  95. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  96. return pid;
  97. }
  98. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  99. u16 pid)
  100. {
  101. unsigned long offset;
  102. if (pipenum == 0)
  103. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  104. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  105. offset = get_pipectr_addr(pipenum);
  106. r8a66597_mdfy(r8a66597, pid, PID, offset);
  107. } else
  108. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  109. }
  110. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  111. {
  112. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  113. }
  114. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  115. {
  116. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  117. }
  118. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  119. {
  120. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  121. }
  122. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  123. {
  124. u16 ret = 0;
  125. unsigned long offset;
  126. if (pipenum == 0)
  127. ret = r8a66597_read(r8a66597, DCPCTR);
  128. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  129. offset = get_pipectr_addr(pipenum);
  130. ret = r8a66597_read(r8a66597, offset);
  131. } else
  132. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  133. return ret;
  134. }
  135. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  136. {
  137. unsigned long offset;
  138. pipe_stop(r8a66597, pipenum);
  139. if (pipenum == 0)
  140. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  141. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  142. offset = get_pipectr_addr(pipenum);
  143. r8a66597_bset(r8a66597, SQCLR, offset);
  144. } else
  145. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  146. }
  147. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  148. {
  149. u16 tmp;
  150. int size;
  151. if (pipenum == 0) {
  152. tmp = r8a66597_read(r8a66597, DCPCFG);
  153. if ((tmp & R8A66597_CNTMD) != 0)
  154. size = 256;
  155. else {
  156. tmp = r8a66597_read(r8a66597, DCPMAXP);
  157. size = tmp & MAXP;
  158. }
  159. } else {
  160. r8a66597_write(r8a66597, pipenum, PIPESEL);
  161. tmp = r8a66597_read(r8a66597, PIPECFG);
  162. if ((tmp & R8A66597_CNTMD) != 0) {
  163. tmp = r8a66597_read(r8a66597, PIPEBUF);
  164. size = ((tmp >> 10) + 1) * 64;
  165. } else {
  166. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  167. size = tmp & MXPS;
  168. }
  169. }
  170. return size;
  171. }
  172. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  173. {
  174. if (r8a66597->pdata->on_chip)
  175. return MBW_32;
  176. else
  177. return MBW_16;
  178. }
  179. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  180. {
  181. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  182. if (ep->use_dma)
  183. return;
  184. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  185. ndelay(450);
  186. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  187. }
  188. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  189. struct r8a66597_pipe_info *info)
  190. {
  191. u16 bufnum = 0, buf_bsize = 0;
  192. u16 pipecfg = 0;
  193. if (info->pipe == 0)
  194. return -EINVAL;
  195. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  196. if (info->dir_in)
  197. pipecfg |= R8A66597_DIR;
  198. pipecfg |= info->type;
  199. pipecfg |= info->epnum;
  200. switch (info->type) {
  201. case R8A66597_INT:
  202. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  203. buf_bsize = 0;
  204. break;
  205. case R8A66597_BULK:
  206. /* isochronous pipes may be used as bulk pipes */
  207. if (info->pipe >= R8A66597_BASE_PIPENUM_BULK)
  208. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  209. else
  210. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  211. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  212. buf_bsize = 7;
  213. pipecfg |= R8A66597_DBLB;
  214. if (!info->dir_in)
  215. pipecfg |= R8A66597_SHTNAK;
  216. break;
  217. case R8A66597_ISO:
  218. bufnum = R8A66597_BASE_BUFNUM +
  219. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  220. buf_bsize = 7;
  221. break;
  222. }
  223. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  224. pr_err("r8a66597 pipe memory is insufficient\n");
  225. return -ENOMEM;
  226. }
  227. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  228. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  229. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  230. if (info->interval)
  231. info->interval--;
  232. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  233. return 0;
  234. }
  235. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  236. struct r8a66597_pipe_info *info)
  237. {
  238. if (info->pipe == 0)
  239. return;
  240. if (is_bulk_pipe(info->pipe))
  241. r8a66597->bulk--;
  242. else if (is_interrupt_pipe(info->pipe))
  243. r8a66597->interrupt--;
  244. else if (is_isoc_pipe(info->pipe)) {
  245. r8a66597->isochronous--;
  246. if (info->type == R8A66597_BULK)
  247. r8a66597->bulk--;
  248. } else
  249. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  250. info->pipe);
  251. }
  252. static void pipe_initialize(struct r8a66597_ep *ep)
  253. {
  254. struct r8a66597 *r8a66597 = ep->r8a66597;
  255. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  256. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  257. r8a66597_write(r8a66597, 0, ep->pipectr);
  258. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  259. if (ep->use_dma) {
  260. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  261. ndelay(450);
  262. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  263. }
  264. }
  265. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  266. struct r8a66597_ep *ep,
  267. const struct usb_endpoint_descriptor *desc,
  268. u16 pipenum, int dma)
  269. {
  270. ep->use_dma = 0;
  271. ep->fifoaddr = CFIFO;
  272. ep->fifosel = CFIFOSEL;
  273. ep->fifoctr = CFIFOCTR;
  274. ep->fifotrn = 0;
  275. ep->pipectr = get_pipectr_addr(pipenum);
  276. ep->pipenum = pipenum;
  277. ep->ep.maxpacket = usb_endpoint_maxp(desc);
  278. r8a66597->pipenum2ep[pipenum] = ep;
  279. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  280. = ep;
  281. INIT_LIST_HEAD(&ep->queue);
  282. }
  283. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  284. {
  285. struct r8a66597 *r8a66597 = ep->r8a66597;
  286. u16 pipenum = ep->pipenum;
  287. if (pipenum == 0)
  288. return;
  289. if (ep->use_dma)
  290. r8a66597->num_dma--;
  291. ep->pipenum = 0;
  292. ep->busy = 0;
  293. ep->use_dma = 0;
  294. }
  295. static int alloc_pipe_config(struct r8a66597_ep *ep,
  296. const struct usb_endpoint_descriptor *desc)
  297. {
  298. struct r8a66597 *r8a66597 = ep->r8a66597;
  299. struct r8a66597_pipe_info info;
  300. int dma = 0;
  301. unsigned char *counter;
  302. int ret;
  303. ep->desc = desc;
  304. if (ep->pipenum) /* already allocated pipe */
  305. return 0;
  306. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  307. case USB_ENDPOINT_XFER_BULK:
  308. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  309. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  310. printk(KERN_ERR "bulk pipe is insufficient\n");
  311. return -ENODEV;
  312. } else {
  313. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  314. + r8a66597->isochronous;
  315. counter = &r8a66597->isochronous;
  316. }
  317. } else {
  318. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  319. counter = &r8a66597->bulk;
  320. }
  321. info.type = R8A66597_BULK;
  322. dma = 1;
  323. break;
  324. case USB_ENDPOINT_XFER_INT:
  325. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  326. printk(KERN_ERR "interrupt pipe is insufficient\n");
  327. return -ENODEV;
  328. }
  329. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  330. info.type = R8A66597_INT;
  331. counter = &r8a66597->interrupt;
  332. break;
  333. case USB_ENDPOINT_XFER_ISOC:
  334. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  335. printk(KERN_ERR "isochronous pipe is insufficient\n");
  336. return -ENODEV;
  337. }
  338. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  339. info.type = R8A66597_ISO;
  340. counter = &r8a66597->isochronous;
  341. break;
  342. default:
  343. printk(KERN_ERR "unexpect xfer type\n");
  344. return -EINVAL;
  345. }
  346. ep->type = info.type;
  347. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  348. info.maxpacket = usb_endpoint_maxp(desc);
  349. info.interval = desc->bInterval;
  350. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  351. info.dir_in = 1;
  352. else
  353. info.dir_in = 0;
  354. ret = pipe_buffer_setting(r8a66597, &info);
  355. if (ret < 0) {
  356. printk(KERN_ERR "pipe_buffer_setting fail\n");
  357. return ret;
  358. }
  359. (*counter)++;
  360. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  361. r8a66597->bulk++;
  362. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  363. pipe_initialize(ep);
  364. return 0;
  365. }
  366. static int free_pipe_config(struct r8a66597_ep *ep)
  367. {
  368. struct r8a66597 *r8a66597 = ep->r8a66597;
  369. struct r8a66597_pipe_info info;
  370. info.pipe = ep->pipenum;
  371. info.type = ep->type;
  372. pipe_buffer_release(r8a66597, &info);
  373. r8a66597_ep_release(ep);
  374. return 0;
  375. }
  376. /*-------------------------------------------------------------------------*/
  377. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  378. {
  379. enable_irq_ready(r8a66597, pipenum);
  380. enable_irq_nrdy(r8a66597, pipenum);
  381. }
  382. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  383. {
  384. disable_irq_ready(r8a66597, pipenum);
  385. disable_irq_nrdy(r8a66597, pipenum);
  386. }
  387. /* if complete is true, gadget driver complete function is not call */
  388. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  389. {
  390. r8a66597->ep[0].internal_ccpl = ccpl;
  391. pipe_start(r8a66597, 0);
  392. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  393. }
  394. static void start_ep0_write(struct r8a66597_ep *ep,
  395. struct r8a66597_request *req)
  396. {
  397. struct r8a66597 *r8a66597 = ep->r8a66597;
  398. pipe_change(r8a66597, ep->pipenum);
  399. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  400. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  401. if (req->req.length == 0) {
  402. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  403. pipe_start(r8a66597, 0);
  404. transfer_complete(ep, req, 0);
  405. } else {
  406. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  407. irq_ep0_write(ep, req);
  408. }
  409. }
  410. static void start_packet_write(struct r8a66597_ep *ep,
  411. struct r8a66597_request *req)
  412. {
  413. struct r8a66597 *r8a66597 = ep->r8a66597;
  414. u16 tmp;
  415. pipe_change(r8a66597, ep->pipenum);
  416. disable_irq_empty(r8a66597, ep->pipenum);
  417. pipe_start(r8a66597, ep->pipenum);
  418. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  419. if (unlikely((tmp & FRDY) == 0))
  420. pipe_irq_enable(r8a66597, ep->pipenum);
  421. else
  422. irq_packet_write(ep, req);
  423. }
  424. static void start_packet_read(struct r8a66597_ep *ep,
  425. struct r8a66597_request *req)
  426. {
  427. struct r8a66597 *r8a66597 = ep->r8a66597;
  428. u16 pipenum = ep->pipenum;
  429. if (ep->pipenum == 0) {
  430. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  431. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  432. pipe_start(r8a66597, pipenum);
  433. pipe_irq_enable(r8a66597, pipenum);
  434. } else {
  435. if (ep->use_dma) {
  436. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  437. pipe_change(r8a66597, pipenum);
  438. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  439. r8a66597_write(r8a66597,
  440. (req->req.length + ep->ep.maxpacket - 1)
  441. / ep->ep.maxpacket,
  442. ep->fifotrn);
  443. }
  444. pipe_start(r8a66597, pipenum); /* trigger once */
  445. pipe_irq_enable(r8a66597, pipenum);
  446. }
  447. }
  448. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  449. {
  450. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  451. start_packet_write(ep, req);
  452. else
  453. start_packet_read(ep, req);
  454. }
  455. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  456. {
  457. u16 ctsq;
  458. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  459. switch (ctsq) {
  460. case CS_RDDS:
  461. start_ep0_write(ep, req);
  462. break;
  463. case CS_WRDS:
  464. start_packet_read(ep, req);
  465. break;
  466. case CS_WRND:
  467. control_end(ep->r8a66597, 0);
  468. break;
  469. default:
  470. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  471. break;
  472. }
  473. }
  474. static void init_controller(struct r8a66597 *r8a66597)
  475. {
  476. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  477. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  478. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  479. if (r8a66597->pdata->on_chip) {
  480. if (r8a66597->pdata->buswait)
  481. r8a66597_write(r8a66597, r8a66597->pdata->buswait,
  482. SYSCFG1);
  483. else
  484. r8a66597_write(r8a66597, 0x0f, SYSCFG1);
  485. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  486. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  487. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  488. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  489. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  490. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  491. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  492. DMA0CFG);
  493. } else {
  494. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  495. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  496. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  497. XTAL, SYSCFG0);
  498. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  499. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  500. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  501. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  502. msleep(3);
  503. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  504. msleep(1);
  505. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  506. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  507. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  508. DMA0CFG);
  509. }
  510. }
  511. static void disable_controller(struct r8a66597 *r8a66597)
  512. {
  513. if (r8a66597->pdata->on_chip) {
  514. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  515. r8a66597_bclr(r8a66597, UTST, TESTMODE);
  516. /* disable interrupts */
  517. r8a66597_write(r8a66597, 0, INTENB0);
  518. r8a66597_write(r8a66597, 0, INTENB1);
  519. r8a66597_write(r8a66597, 0, BRDYENB);
  520. r8a66597_write(r8a66597, 0, BEMPENB);
  521. r8a66597_write(r8a66597, 0, NRDYENB);
  522. /* clear status */
  523. r8a66597_write(r8a66597, 0, BRDYSTS);
  524. r8a66597_write(r8a66597, 0, NRDYSTS);
  525. r8a66597_write(r8a66597, 0, BEMPSTS);
  526. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  527. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  528. } else {
  529. r8a66597_bclr(r8a66597, UTST, TESTMODE);
  530. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  531. udelay(1);
  532. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  533. udelay(1);
  534. udelay(1);
  535. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  536. }
  537. }
  538. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  539. {
  540. u16 tmp;
  541. if (!r8a66597->pdata->on_chip) {
  542. tmp = r8a66597_read(r8a66597, SYSCFG0);
  543. if (!(tmp & XCKE))
  544. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  545. }
  546. }
  547. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  548. {
  549. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  550. }
  551. /*-------------------------------------------------------------------------*/
  552. static void transfer_complete(struct r8a66597_ep *ep,
  553. struct r8a66597_request *req, int status)
  554. __releases(r8a66597->lock)
  555. __acquires(r8a66597->lock)
  556. {
  557. int restart = 0;
  558. if (unlikely(ep->pipenum == 0)) {
  559. if (ep->internal_ccpl) {
  560. ep->internal_ccpl = 0;
  561. return;
  562. }
  563. }
  564. list_del_init(&req->queue);
  565. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  566. req->req.status = -ESHUTDOWN;
  567. else
  568. req->req.status = status;
  569. if (!list_empty(&ep->queue))
  570. restart = 1;
  571. spin_unlock(&ep->r8a66597->lock);
  572. req->req.complete(&ep->ep, &req->req);
  573. spin_lock(&ep->r8a66597->lock);
  574. if (restart) {
  575. req = get_request_from_ep(ep);
  576. if (ep->desc)
  577. start_packet(ep, req);
  578. }
  579. }
  580. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  581. {
  582. int i;
  583. u16 tmp;
  584. unsigned bufsize;
  585. size_t size;
  586. void *buf;
  587. u16 pipenum = ep->pipenum;
  588. struct r8a66597 *r8a66597 = ep->r8a66597;
  589. pipe_change(r8a66597, pipenum);
  590. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  591. i = 0;
  592. do {
  593. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  594. if (i++ > 100000) {
  595. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  596. "conflict. please power off this controller.");
  597. return;
  598. }
  599. ndelay(1);
  600. } while ((tmp & FRDY) == 0);
  601. /* prepare parameters */
  602. bufsize = get_buffer_size(r8a66597, pipenum);
  603. buf = req->req.buf + req->req.actual;
  604. size = min(bufsize, req->req.length - req->req.actual);
  605. /* write fifo */
  606. if (req->req.buf) {
  607. if (size > 0)
  608. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  609. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  610. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  611. }
  612. /* update parameters */
  613. req->req.actual += size;
  614. /* check transfer finish */
  615. if ((!req->req.zero && (req->req.actual == req->req.length))
  616. || (size % ep->ep.maxpacket)
  617. || (size == 0)) {
  618. disable_irq_ready(r8a66597, pipenum);
  619. disable_irq_empty(r8a66597, pipenum);
  620. } else {
  621. disable_irq_ready(r8a66597, pipenum);
  622. enable_irq_empty(r8a66597, pipenum);
  623. }
  624. pipe_start(r8a66597, pipenum);
  625. }
  626. static void irq_packet_write(struct r8a66597_ep *ep,
  627. struct r8a66597_request *req)
  628. {
  629. u16 tmp;
  630. unsigned bufsize;
  631. size_t size;
  632. void *buf;
  633. u16 pipenum = ep->pipenum;
  634. struct r8a66597 *r8a66597 = ep->r8a66597;
  635. pipe_change(r8a66597, pipenum);
  636. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  637. if (unlikely((tmp & FRDY) == 0)) {
  638. pipe_stop(r8a66597, pipenum);
  639. pipe_irq_disable(r8a66597, pipenum);
  640. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  641. return;
  642. }
  643. /* prepare parameters */
  644. bufsize = get_buffer_size(r8a66597, pipenum);
  645. buf = req->req.buf + req->req.actual;
  646. size = min(bufsize, req->req.length - req->req.actual);
  647. /* write fifo */
  648. if (req->req.buf) {
  649. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  650. if ((size == 0)
  651. || ((size % ep->ep.maxpacket) != 0)
  652. || ((bufsize != ep->ep.maxpacket)
  653. && (bufsize > size)))
  654. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  655. }
  656. /* update parameters */
  657. req->req.actual += size;
  658. /* check transfer finish */
  659. if ((!req->req.zero && (req->req.actual == req->req.length))
  660. || (size % ep->ep.maxpacket)
  661. || (size == 0)) {
  662. disable_irq_ready(r8a66597, pipenum);
  663. enable_irq_empty(r8a66597, pipenum);
  664. } else {
  665. disable_irq_empty(r8a66597, pipenum);
  666. pipe_irq_enable(r8a66597, pipenum);
  667. }
  668. }
  669. static void irq_packet_read(struct r8a66597_ep *ep,
  670. struct r8a66597_request *req)
  671. {
  672. u16 tmp;
  673. int rcv_len, bufsize, req_len;
  674. int size;
  675. void *buf;
  676. u16 pipenum = ep->pipenum;
  677. struct r8a66597 *r8a66597 = ep->r8a66597;
  678. int finish = 0;
  679. pipe_change(r8a66597, pipenum);
  680. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  681. if (unlikely((tmp & FRDY) == 0)) {
  682. req->req.status = -EPIPE;
  683. pipe_stop(r8a66597, pipenum);
  684. pipe_irq_disable(r8a66597, pipenum);
  685. printk(KERN_ERR "read fifo not ready");
  686. return;
  687. }
  688. /* prepare parameters */
  689. rcv_len = tmp & DTLN;
  690. bufsize = get_buffer_size(r8a66597, pipenum);
  691. buf = req->req.buf + req->req.actual;
  692. req_len = req->req.length - req->req.actual;
  693. if (rcv_len < bufsize)
  694. size = min(rcv_len, req_len);
  695. else
  696. size = min(bufsize, req_len);
  697. /* update parameters */
  698. req->req.actual += size;
  699. /* check transfer finish */
  700. if ((!req->req.zero && (req->req.actual == req->req.length))
  701. || (size % ep->ep.maxpacket)
  702. || (size == 0)) {
  703. pipe_stop(r8a66597, pipenum);
  704. pipe_irq_disable(r8a66597, pipenum);
  705. finish = 1;
  706. }
  707. /* read fifo */
  708. if (req->req.buf) {
  709. if (size == 0)
  710. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  711. else
  712. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  713. }
  714. if ((ep->pipenum != 0) && finish)
  715. transfer_complete(ep, req, 0);
  716. }
  717. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  718. {
  719. u16 check;
  720. u16 pipenum;
  721. struct r8a66597_ep *ep;
  722. struct r8a66597_request *req;
  723. if ((status & BRDY0) && (enb & BRDY0)) {
  724. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  725. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  726. ep = &r8a66597->ep[0];
  727. req = get_request_from_ep(ep);
  728. irq_packet_read(ep, req);
  729. } else {
  730. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  731. check = 1 << pipenum;
  732. if ((status & check) && (enb & check)) {
  733. r8a66597_write(r8a66597, ~check, BRDYSTS);
  734. ep = r8a66597->pipenum2ep[pipenum];
  735. req = get_request_from_ep(ep);
  736. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  737. irq_packet_write(ep, req);
  738. else
  739. irq_packet_read(ep, req);
  740. }
  741. }
  742. }
  743. }
  744. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  745. {
  746. u16 tmp;
  747. u16 check;
  748. u16 pipenum;
  749. struct r8a66597_ep *ep;
  750. struct r8a66597_request *req;
  751. if ((status & BEMP0) && (enb & BEMP0)) {
  752. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  753. ep = &r8a66597->ep[0];
  754. req = get_request_from_ep(ep);
  755. irq_ep0_write(ep, req);
  756. } else {
  757. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  758. check = 1 << pipenum;
  759. if ((status & check) && (enb & check)) {
  760. r8a66597_write(r8a66597, ~check, BEMPSTS);
  761. tmp = control_reg_get(r8a66597, pipenum);
  762. if ((tmp & INBUFM) == 0) {
  763. disable_irq_empty(r8a66597, pipenum);
  764. pipe_irq_disable(r8a66597, pipenum);
  765. pipe_stop(r8a66597, pipenum);
  766. ep = r8a66597->pipenum2ep[pipenum];
  767. req = get_request_from_ep(ep);
  768. if (!list_empty(&ep->queue))
  769. transfer_complete(ep, req, 0);
  770. }
  771. }
  772. }
  773. }
  774. }
  775. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  776. __releases(r8a66597->lock)
  777. __acquires(r8a66597->lock)
  778. {
  779. struct r8a66597_ep *ep;
  780. u16 pid;
  781. u16 status = 0;
  782. u16 w_index = le16_to_cpu(ctrl->wIndex);
  783. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  784. case USB_RECIP_DEVICE:
  785. status = 1 << USB_DEVICE_SELF_POWERED;
  786. break;
  787. case USB_RECIP_INTERFACE:
  788. status = 0;
  789. break;
  790. case USB_RECIP_ENDPOINT:
  791. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  792. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  793. if (pid == PID_STALL)
  794. status = 1 << USB_ENDPOINT_HALT;
  795. else
  796. status = 0;
  797. break;
  798. default:
  799. pipe_stall(r8a66597, 0);
  800. return; /* exit */
  801. }
  802. r8a66597->ep0_data = cpu_to_le16(status);
  803. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  804. r8a66597->ep0_req->length = 2;
  805. /* AV: what happens if we get called again before that gets through? */
  806. spin_unlock(&r8a66597->lock);
  807. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  808. spin_lock(&r8a66597->lock);
  809. }
  810. static void clear_feature(struct r8a66597 *r8a66597,
  811. struct usb_ctrlrequest *ctrl)
  812. {
  813. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  814. case USB_RECIP_DEVICE:
  815. control_end(r8a66597, 1);
  816. break;
  817. case USB_RECIP_INTERFACE:
  818. control_end(r8a66597, 1);
  819. break;
  820. case USB_RECIP_ENDPOINT: {
  821. struct r8a66597_ep *ep;
  822. struct r8a66597_request *req;
  823. u16 w_index = le16_to_cpu(ctrl->wIndex);
  824. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  825. if (!ep->wedge) {
  826. pipe_stop(r8a66597, ep->pipenum);
  827. control_reg_sqclr(r8a66597, ep->pipenum);
  828. spin_unlock(&r8a66597->lock);
  829. usb_ep_clear_halt(&ep->ep);
  830. spin_lock(&r8a66597->lock);
  831. }
  832. control_end(r8a66597, 1);
  833. req = get_request_from_ep(ep);
  834. if (ep->busy) {
  835. ep->busy = 0;
  836. if (list_empty(&ep->queue))
  837. break;
  838. start_packet(ep, req);
  839. } else if (!list_empty(&ep->queue))
  840. pipe_start(r8a66597, ep->pipenum);
  841. }
  842. break;
  843. default:
  844. pipe_stall(r8a66597, 0);
  845. break;
  846. }
  847. }
  848. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  849. {
  850. u16 tmp;
  851. int timeout = 3000;
  852. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  853. case USB_RECIP_DEVICE:
  854. switch (le16_to_cpu(ctrl->wValue)) {
  855. case USB_DEVICE_TEST_MODE:
  856. control_end(r8a66597, 1);
  857. /* Wait for the completion of status stage */
  858. do {
  859. tmp = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  860. udelay(1);
  861. } while (tmp != CS_IDST || timeout-- > 0);
  862. if (tmp == CS_IDST)
  863. r8a66597_bset(r8a66597,
  864. le16_to_cpu(ctrl->wIndex >> 8),
  865. TESTMODE);
  866. break;
  867. default:
  868. pipe_stall(r8a66597, 0);
  869. break;
  870. }
  871. break;
  872. case USB_RECIP_INTERFACE:
  873. control_end(r8a66597, 1);
  874. break;
  875. case USB_RECIP_ENDPOINT: {
  876. struct r8a66597_ep *ep;
  877. u16 w_index = le16_to_cpu(ctrl->wIndex);
  878. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  879. pipe_stall(r8a66597, ep->pipenum);
  880. control_end(r8a66597, 1);
  881. }
  882. break;
  883. default:
  884. pipe_stall(r8a66597, 0);
  885. break;
  886. }
  887. }
  888. /* if return value is true, call class driver's setup() */
  889. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  890. {
  891. u16 *p = (u16 *)ctrl;
  892. unsigned long offset = USBREQ;
  893. int i, ret = 0;
  894. /* read fifo */
  895. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  896. for (i = 0; i < 4; i++)
  897. p[i] = r8a66597_read(r8a66597, offset + i*2);
  898. /* check request */
  899. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  900. switch (ctrl->bRequest) {
  901. case USB_REQ_GET_STATUS:
  902. get_status(r8a66597, ctrl);
  903. break;
  904. case USB_REQ_CLEAR_FEATURE:
  905. clear_feature(r8a66597, ctrl);
  906. break;
  907. case USB_REQ_SET_FEATURE:
  908. set_feature(r8a66597, ctrl);
  909. break;
  910. default:
  911. ret = 1;
  912. break;
  913. }
  914. } else
  915. ret = 1;
  916. return ret;
  917. }
  918. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  919. {
  920. u16 speed = get_usb_speed(r8a66597);
  921. switch (speed) {
  922. case HSMODE:
  923. r8a66597->gadget.speed = USB_SPEED_HIGH;
  924. break;
  925. case FSMODE:
  926. r8a66597->gadget.speed = USB_SPEED_FULL;
  927. break;
  928. default:
  929. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  930. printk(KERN_ERR "USB speed unknown\n");
  931. }
  932. }
  933. static void irq_device_state(struct r8a66597 *r8a66597)
  934. {
  935. u16 dvsq;
  936. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  937. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  938. if (dvsq == DS_DFLT) {
  939. /* bus reset */
  940. spin_unlock(&r8a66597->lock);
  941. r8a66597->driver->disconnect(&r8a66597->gadget);
  942. spin_lock(&r8a66597->lock);
  943. r8a66597_update_usb_speed(r8a66597);
  944. }
  945. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  946. r8a66597_update_usb_speed(r8a66597);
  947. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  948. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  949. r8a66597_update_usb_speed(r8a66597);
  950. r8a66597->old_dvsq = dvsq;
  951. }
  952. static void irq_control_stage(struct r8a66597 *r8a66597)
  953. __releases(r8a66597->lock)
  954. __acquires(r8a66597->lock)
  955. {
  956. struct usb_ctrlrequest ctrl;
  957. u16 ctsq;
  958. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  959. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  960. switch (ctsq) {
  961. case CS_IDST: {
  962. struct r8a66597_ep *ep;
  963. struct r8a66597_request *req;
  964. ep = &r8a66597->ep[0];
  965. req = get_request_from_ep(ep);
  966. transfer_complete(ep, req, 0);
  967. }
  968. break;
  969. case CS_RDDS:
  970. case CS_WRDS:
  971. case CS_WRND:
  972. if (setup_packet(r8a66597, &ctrl)) {
  973. spin_unlock(&r8a66597->lock);
  974. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  975. < 0)
  976. pipe_stall(r8a66597, 0);
  977. spin_lock(&r8a66597->lock);
  978. }
  979. break;
  980. case CS_RDSS:
  981. case CS_WRSS:
  982. control_end(r8a66597, 0);
  983. break;
  984. default:
  985. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  986. break;
  987. }
  988. }
  989. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  990. {
  991. struct r8a66597 *r8a66597 = _r8a66597;
  992. u16 intsts0;
  993. u16 intenb0;
  994. u16 brdysts, nrdysts, bempsts;
  995. u16 brdyenb, nrdyenb, bempenb;
  996. u16 savepipe;
  997. u16 mask0;
  998. spin_lock(&r8a66597->lock);
  999. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  1000. intenb0 = r8a66597_read(r8a66597, INTENB0);
  1001. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  1002. mask0 = intsts0 & intenb0;
  1003. if (mask0) {
  1004. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  1005. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  1006. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  1007. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  1008. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  1009. bempenb = r8a66597_read(r8a66597, BEMPENB);
  1010. if (mask0 & VBINT) {
  1011. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  1012. INTSTS0);
  1013. r8a66597_start_xclock(r8a66597);
  1014. /* start vbus sampling */
  1015. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  1016. & VBSTS;
  1017. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1018. mod_timer(&r8a66597->timer,
  1019. jiffies + msecs_to_jiffies(50));
  1020. }
  1021. if (intsts0 & DVSQ)
  1022. irq_device_state(r8a66597);
  1023. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1024. && (brdysts & brdyenb))
  1025. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1026. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1027. && (bempsts & bempenb))
  1028. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1029. if (intsts0 & CTRT)
  1030. irq_control_stage(r8a66597);
  1031. }
  1032. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1033. spin_unlock(&r8a66597->lock);
  1034. return IRQ_HANDLED;
  1035. }
  1036. static void r8a66597_timer(unsigned long _r8a66597)
  1037. {
  1038. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1039. unsigned long flags;
  1040. u16 tmp;
  1041. spin_lock_irqsave(&r8a66597->lock, flags);
  1042. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1043. if (r8a66597->scount > 0) {
  1044. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1045. if (tmp == r8a66597->old_vbus) {
  1046. r8a66597->scount--;
  1047. if (r8a66597->scount == 0) {
  1048. if (tmp == VBSTS)
  1049. r8a66597_usb_connect(r8a66597);
  1050. else
  1051. r8a66597_usb_disconnect(r8a66597);
  1052. } else {
  1053. mod_timer(&r8a66597->timer,
  1054. jiffies + msecs_to_jiffies(50));
  1055. }
  1056. } else {
  1057. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1058. r8a66597->old_vbus = tmp;
  1059. mod_timer(&r8a66597->timer,
  1060. jiffies + msecs_to_jiffies(50));
  1061. }
  1062. }
  1063. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1064. }
  1065. /*-------------------------------------------------------------------------*/
  1066. static int r8a66597_enable(struct usb_ep *_ep,
  1067. const struct usb_endpoint_descriptor *desc)
  1068. {
  1069. struct r8a66597_ep *ep;
  1070. ep = container_of(_ep, struct r8a66597_ep, ep);
  1071. return alloc_pipe_config(ep, desc);
  1072. }
  1073. static int r8a66597_disable(struct usb_ep *_ep)
  1074. {
  1075. struct r8a66597_ep *ep;
  1076. struct r8a66597_request *req;
  1077. unsigned long flags;
  1078. ep = container_of(_ep, struct r8a66597_ep, ep);
  1079. BUG_ON(!ep);
  1080. while (!list_empty(&ep->queue)) {
  1081. req = get_request_from_ep(ep);
  1082. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1083. transfer_complete(ep, req, -ECONNRESET);
  1084. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1085. }
  1086. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1087. return free_pipe_config(ep);
  1088. }
  1089. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1090. gfp_t gfp_flags)
  1091. {
  1092. struct r8a66597_request *req;
  1093. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1094. if (!req)
  1095. return NULL;
  1096. INIT_LIST_HEAD(&req->queue);
  1097. return &req->req;
  1098. }
  1099. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1100. {
  1101. struct r8a66597_request *req;
  1102. req = container_of(_req, struct r8a66597_request, req);
  1103. kfree(req);
  1104. }
  1105. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1106. gfp_t gfp_flags)
  1107. {
  1108. struct r8a66597_ep *ep;
  1109. struct r8a66597_request *req;
  1110. unsigned long flags;
  1111. int request = 0;
  1112. ep = container_of(_ep, struct r8a66597_ep, ep);
  1113. req = container_of(_req, struct r8a66597_request, req);
  1114. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1115. return -ESHUTDOWN;
  1116. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1117. if (list_empty(&ep->queue))
  1118. request = 1;
  1119. list_add_tail(&req->queue, &ep->queue);
  1120. req->req.actual = 0;
  1121. req->req.status = -EINPROGRESS;
  1122. if (ep->desc == NULL) /* control */
  1123. start_ep0(ep, req);
  1124. else {
  1125. if (request && !ep->busy)
  1126. start_packet(ep, req);
  1127. }
  1128. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1129. return 0;
  1130. }
  1131. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1132. {
  1133. struct r8a66597_ep *ep;
  1134. struct r8a66597_request *req;
  1135. unsigned long flags;
  1136. ep = container_of(_ep, struct r8a66597_ep, ep);
  1137. req = container_of(_req, struct r8a66597_request, req);
  1138. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1139. if (!list_empty(&ep->queue))
  1140. transfer_complete(ep, req, -ECONNRESET);
  1141. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1142. return 0;
  1143. }
  1144. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1145. {
  1146. struct r8a66597_ep *ep;
  1147. struct r8a66597_request *req;
  1148. unsigned long flags;
  1149. int ret = 0;
  1150. ep = container_of(_ep, struct r8a66597_ep, ep);
  1151. req = get_request_from_ep(ep);
  1152. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1153. if (!list_empty(&ep->queue)) {
  1154. ret = -EAGAIN;
  1155. goto out;
  1156. }
  1157. if (value) {
  1158. ep->busy = 1;
  1159. pipe_stall(ep->r8a66597, ep->pipenum);
  1160. } else {
  1161. ep->busy = 0;
  1162. ep->wedge = 0;
  1163. pipe_stop(ep->r8a66597, ep->pipenum);
  1164. }
  1165. out:
  1166. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1167. return ret;
  1168. }
  1169. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1170. {
  1171. struct r8a66597_ep *ep;
  1172. unsigned long flags;
  1173. ep = container_of(_ep, struct r8a66597_ep, ep);
  1174. if (!ep || !ep->desc)
  1175. return -EINVAL;
  1176. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1177. ep->wedge = 1;
  1178. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1179. return usb_ep_set_halt(_ep);
  1180. }
  1181. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1182. {
  1183. struct r8a66597_ep *ep;
  1184. unsigned long flags;
  1185. ep = container_of(_ep, struct r8a66597_ep, ep);
  1186. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1187. if (list_empty(&ep->queue) && !ep->busy) {
  1188. pipe_stop(ep->r8a66597, ep->pipenum);
  1189. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1190. }
  1191. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1192. }
  1193. static struct usb_ep_ops r8a66597_ep_ops = {
  1194. .enable = r8a66597_enable,
  1195. .disable = r8a66597_disable,
  1196. .alloc_request = r8a66597_alloc_request,
  1197. .free_request = r8a66597_free_request,
  1198. .queue = r8a66597_queue,
  1199. .dequeue = r8a66597_dequeue,
  1200. .set_halt = r8a66597_set_halt,
  1201. .set_wedge = r8a66597_set_wedge,
  1202. .fifo_flush = r8a66597_fifo_flush,
  1203. };
  1204. /*-------------------------------------------------------------------------*/
  1205. static struct r8a66597 *the_controller;
  1206. static int r8a66597_start(struct usb_gadget_driver *driver,
  1207. int (*bind)(struct usb_gadget *))
  1208. {
  1209. struct r8a66597 *r8a66597 = the_controller;
  1210. int retval;
  1211. if (!driver
  1212. || driver->speed != USB_SPEED_HIGH
  1213. || !bind
  1214. || !driver->setup)
  1215. return -EINVAL;
  1216. if (!r8a66597)
  1217. return -ENODEV;
  1218. if (r8a66597->driver)
  1219. return -EBUSY;
  1220. /* hook up the driver */
  1221. driver->driver.bus = NULL;
  1222. r8a66597->driver = driver;
  1223. r8a66597->gadget.dev.driver = &driver->driver;
  1224. retval = device_add(&r8a66597->gadget.dev);
  1225. if (retval) {
  1226. printk(KERN_ERR "device_add error (%d)\n", retval);
  1227. goto error;
  1228. }
  1229. retval = bind(&r8a66597->gadget);
  1230. if (retval) {
  1231. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1232. device_del(&r8a66597->gadget.dev);
  1233. goto error;
  1234. }
  1235. init_controller(r8a66597);
  1236. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1237. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1238. r8a66597_start_xclock(r8a66597);
  1239. /* start vbus sampling */
  1240. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1241. INTSTS0) & VBSTS;
  1242. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1243. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1244. }
  1245. return 0;
  1246. error:
  1247. r8a66597->driver = NULL;
  1248. r8a66597->gadget.dev.driver = NULL;
  1249. return retval;
  1250. }
  1251. static int r8a66597_stop(struct usb_gadget_driver *driver)
  1252. {
  1253. struct r8a66597 *r8a66597 = the_controller;
  1254. unsigned long flags;
  1255. if (driver != r8a66597->driver || !driver->unbind)
  1256. return -EINVAL;
  1257. spin_lock_irqsave(&r8a66597->lock, flags);
  1258. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1259. r8a66597_usb_disconnect(r8a66597);
  1260. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1261. disable_controller(r8a66597);
  1262. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1263. driver->unbind(&r8a66597->gadget);
  1264. device_del(&r8a66597->gadget.dev);
  1265. r8a66597->driver = NULL;
  1266. return 0;
  1267. }
  1268. /*-------------------------------------------------------------------------*/
  1269. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1270. {
  1271. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1272. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1273. }
  1274. static int r8a66597_pullup(struct usb_gadget *gadget, int is_on)
  1275. {
  1276. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1277. unsigned long flags;
  1278. spin_lock_irqsave(&r8a66597->lock, flags);
  1279. if (is_on)
  1280. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  1281. else
  1282. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  1283. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1284. return 0;
  1285. }
  1286. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1287. .get_frame = r8a66597_get_frame,
  1288. .start = r8a66597_start,
  1289. .stop = r8a66597_stop,
  1290. .pullup = r8a66597_pullup,
  1291. };
  1292. static int __exit r8a66597_remove(struct platform_device *pdev)
  1293. {
  1294. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1295. usb_del_gadget_udc(&r8a66597->gadget);
  1296. del_timer_sync(&r8a66597->timer);
  1297. iounmap(r8a66597->reg);
  1298. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1299. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1300. #ifdef CONFIG_HAVE_CLK
  1301. if (r8a66597->pdata->on_chip) {
  1302. clk_disable(r8a66597->clk);
  1303. clk_put(r8a66597->clk);
  1304. }
  1305. #endif
  1306. kfree(r8a66597);
  1307. return 0;
  1308. }
  1309. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1310. {
  1311. }
  1312. static int __init r8a66597_probe(struct platform_device *pdev)
  1313. {
  1314. #ifdef CONFIG_HAVE_CLK
  1315. char clk_name[8];
  1316. #endif
  1317. struct resource *res, *ires;
  1318. int irq;
  1319. void __iomem *reg = NULL;
  1320. struct r8a66597 *r8a66597 = NULL;
  1321. int ret = 0;
  1322. int i;
  1323. unsigned long irq_trigger;
  1324. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1325. if (!res) {
  1326. ret = -ENODEV;
  1327. printk(KERN_ERR "platform_get_resource error.\n");
  1328. goto clean_up;
  1329. }
  1330. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1331. irq = ires->start;
  1332. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1333. if (irq < 0) {
  1334. ret = -ENODEV;
  1335. printk(KERN_ERR "platform_get_irq error.\n");
  1336. goto clean_up;
  1337. }
  1338. reg = ioremap(res->start, resource_size(res));
  1339. if (reg == NULL) {
  1340. ret = -ENOMEM;
  1341. printk(KERN_ERR "ioremap error.\n");
  1342. goto clean_up;
  1343. }
  1344. /* initialize ucd */
  1345. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1346. if (r8a66597 == NULL) {
  1347. ret = -ENOMEM;
  1348. printk(KERN_ERR "kzalloc error\n");
  1349. goto clean_up;
  1350. }
  1351. spin_lock_init(&r8a66597->lock);
  1352. dev_set_drvdata(&pdev->dev, r8a66597);
  1353. r8a66597->pdata = pdev->dev.platform_data;
  1354. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1355. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1356. device_initialize(&r8a66597->gadget.dev);
  1357. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1358. r8a66597->gadget.is_dualspeed = 1;
  1359. r8a66597->gadget.dev.parent = &pdev->dev;
  1360. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1361. r8a66597->gadget.dev.release = pdev->dev.release;
  1362. r8a66597->gadget.name = udc_name;
  1363. init_timer(&r8a66597->timer);
  1364. r8a66597->timer.function = r8a66597_timer;
  1365. r8a66597->timer.data = (unsigned long)r8a66597;
  1366. r8a66597->reg = reg;
  1367. #ifdef CONFIG_HAVE_CLK
  1368. if (r8a66597->pdata->on_chip) {
  1369. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1370. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1371. if (IS_ERR(r8a66597->clk)) {
  1372. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1373. clk_name);
  1374. ret = PTR_ERR(r8a66597->clk);
  1375. goto clean_up;
  1376. }
  1377. clk_enable(r8a66597->clk);
  1378. }
  1379. #endif
  1380. disable_controller(r8a66597); /* make sure controller is disabled */
  1381. ret = request_irq(irq, r8a66597_irq, IRQF_SHARED,
  1382. udc_name, r8a66597);
  1383. if (ret < 0) {
  1384. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1385. goto clean_up2;
  1386. }
  1387. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1388. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1389. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1390. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1391. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1392. if (i != 0) {
  1393. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1394. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1395. &r8a66597->gadget.ep_list);
  1396. }
  1397. ep->r8a66597 = r8a66597;
  1398. INIT_LIST_HEAD(&ep->queue);
  1399. ep->ep.name = r8a66597_ep_name[i];
  1400. ep->ep.ops = &r8a66597_ep_ops;
  1401. ep->ep.maxpacket = 512;
  1402. }
  1403. r8a66597->ep[0].ep.maxpacket = 64;
  1404. r8a66597->ep[0].pipenum = 0;
  1405. r8a66597->ep[0].fifoaddr = CFIFO;
  1406. r8a66597->ep[0].fifosel = CFIFOSEL;
  1407. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1408. r8a66597->ep[0].fifotrn = 0;
  1409. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1410. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1411. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1412. the_controller = r8a66597;
  1413. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1414. GFP_KERNEL);
  1415. if (r8a66597->ep0_req == NULL)
  1416. goto clean_up3;
  1417. r8a66597->ep0_req->complete = nop_completion;
  1418. ret = usb_add_gadget_udc(&pdev->dev, &r8a66597->gadget);
  1419. if (ret)
  1420. goto err_add_udc;
  1421. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1422. return 0;
  1423. err_add_udc:
  1424. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1425. clean_up3:
  1426. free_irq(irq, r8a66597);
  1427. clean_up2:
  1428. #ifdef CONFIG_HAVE_CLK
  1429. if (r8a66597->pdata->on_chip) {
  1430. clk_disable(r8a66597->clk);
  1431. clk_put(r8a66597->clk);
  1432. }
  1433. #endif
  1434. clean_up:
  1435. if (r8a66597) {
  1436. if (r8a66597->ep0_req)
  1437. r8a66597_free_request(&r8a66597->ep[0].ep,
  1438. r8a66597->ep0_req);
  1439. kfree(r8a66597);
  1440. }
  1441. if (reg)
  1442. iounmap(reg);
  1443. return ret;
  1444. }
  1445. /*-------------------------------------------------------------------------*/
  1446. static struct platform_driver r8a66597_driver = {
  1447. .remove = __exit_p(r8a66597_remove),
  1448. .driver = {
  1449. .name = (char *) udc_name,
  1450. },
  1451. };
  1452. MODULE_ALIAS("platform:r8a66597_udc");
  1453. static int __init r8a66597_udc_init(void)
  1454. {
  1455. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1456. }
  1457. module_init(r8a66597_udc_init);
  1458. static void __exit r8a66597_udc_cleanup(void)
  1459. {
  1460. platform_driver_unregister(&r8a66597_driver);
  1461. }
  1462. module_exit(r8a66597_udc_cleanup);
  1463. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1464. MODULE_LICENSE("GPL");
  1465. MODULE_AUTHOR("Yoshihiro Shimoda");