pci.c 36 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337
  1. /*
  2. * Support for PCI bridges found on Power Macintoshes.
  3. *
  4. * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
  5. * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/pci.h>
  14. #include <linux/delay.h>
  15. #include <linux/string.h>
  16. #include <linux/init.h>
  17. #include <linux/bootmem.h>
  18. #include <linux/irq.h>
  19. #include <asm/sections.h>
  20. #include <asm/io.h>
  21. #include <asm/prom.h>
  22. #include <asm/pci-bridge.h>
  23. #include <asm/machdep.h>
  24. #include <asm/pmac_feature.h>
  25. #include <asm/grackle.h>
  26. #include <asm/ppc-pci.h>
  27. #undef DEBUG
  28. #ifdef DEBUG
  29. #define DBG(x...) printk(x)
  30. #else
  31. #define DBG(x...)
  32. #endif
  33. static int add_bridge(struct device_node *dev);
  34. /* XXX Could be per-controller, but I don't think we risk anything by
  35. * assuming we won't have both UniNorth and Bandit */
  36. static int has_uninorth;
  37. #ifdef CONFIG_PPC64
  38. static struct pci_controller *u3_agp;
  39. static struct pci_controller *u4_pcie;
  40. static struct pci_controller *u3_ht;
  41. #else
  42. static int has_second_ohare;
  43. #endif /* CONFIG_PPC64 */
  44. extern int pcibios_assign_bus_offset;
  45. struct device_node *k2_skiplist[2];
  46. /*
  47. * Magic constants for enabling cache coherency in the bandit/PSX bridge.
  48. */
  49. #define BANDIT_DEVID_2 8
  50. #define BANDIT_REVID 3
  51. #define BANDIT_DEVNUM 11
  52. #define BANDIT_MAGIC 0x50
  53. #define BANDIT_COHERENT 0x40
  54. static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
  55. {
  56. for (; node != 0;node = node->sibling) {
  57. const int * bus_range;
  58. const unsigned int *class_code;
  59. int len;
  60. /* For PCI<->PCI bridges or CardBus bridges, we go down */
  61. class_code = get_property(node, "class-code", NULL);
  62. if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
  63. (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
  64. continue;
  65. bus_range = get_property(node, "bus-range", &len);
  66. if (bus_range != NULL && len > 2 * sizeof(int)) {
  67. if (bus_range[1] > higher)
  68. higher = bus_range[1];
  69. }
  70. higher = fixup_one_level_bus_range(node->child, higher);
  71. }
  72. return higher;
  73. }
  74. /* This routine fixes the "bus-range" property of all bridges in the
  75. * system since they tend to have their "last" member wrong on macs
  76. *
  77. * Note that the bus numbers manipulated here are OF bus numbers, they
  78. * are not Linux bus numbers.
  79. */
  80. static void __init fixup_bus_range(struct device_node *bridge)
  81. {
  82. int *bus_range, len;
  83. struct property *prop;
  84. /* Lookup the "bus-range" property for the hose */
  85. prop = of_find_property(bridge, "bus-range", &len);
  86. if (prop == NULL || prop->length < 2 * sizeof(int))
  87. return;
  88. bus_range = (int *)prop->value;
  89. bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
  90. }
  91. /*
  92. * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
  93. *
  94. * The "Bandit" version is present in all early PCI PowerMacs,
  95. * and up to the first ones using Grackle. Some machines may
  96. * have 2 bandit controllers (2 PCI busses).
  97. *
  98. * "Chaos" is used in some "Bandit"-type machines as a bridge
  99. * for the separate display bus. It is accessed the same
  100. * way as bandit, but cannot be probed for devices. It therefore
  101. * has its own config access functions.
  102. *
  103. * The "UniNorth" version is present in all Core99 machines
  104. * (iBook, G4, new IMacs, and all the recent Apple machines).
  105. * It contains 3 controllers in one ASIC.
  106. *
  107. * The U3 is the bridge used on G5 machines. It contains an
  108. * AGP bus which is dealt with the old UniNorth access routines
  109. * and a HyperTransport bus which uses its own set of access
  110. * functions.
  111. */
  112. #define MACRISC_CFA0(devfn, off) \
  113. ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
  114. | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
  115. | (((unsigned int)(off)) & 0xFCUL))
  116. #define MACRISC_CFA1(bus, devfn, off) \
  117. ((((unsigned int)(bus)) << 16) \
  118. |(((unsigned int)(devfn)) << 8) \
  119. |(((unsigned int)(off)) & 0xFCUL) \
  120. |1UL)
  121. static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
  122. u8 bus, u8 dev_fn, u8 offset)
  123. {
  124. unsigned int caddr;
  125. if (bus == hose->first_busno) {
  126. if (dev_fn < (11 << 3))
  127. return NULL;
  128. caddr = MACRISC_CFA0(dev_fn, offset);
  129. } else
  130. caddr = MACRISC_CFA1(bus, dev_fn, offset);
  131. /* Uninorth will return garbage if we don't read back the value ! */
  132. do {
  133. out_le32(hose->cfg_addr, caddr);
  134. } while (in_le32(hose->cfg_addr) != caddr);
  135. offset &= has_uninorth ? 0x07 : 0x03;
  136. return hose->cfg_data + offset;
  137. }
  138. static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
  139. int offset, int len, u32 *val)
  140. {
  141. struct pci_controller *hose;
  142. volatile void __iomem *addr;
  143. hose = pci_bus_to_host(bus);
  144. if (hose == NULL)
  145. return PCIBIOS_DEVICE_NOT_FOUND;
  146. if (offset >= 0x100)
  147. return PCIBIOS_BAD_REGISTER_NUMBER;
  148. addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
  149. if (!addr)
  150. return PCIBIOS_DEVICE_NOT_FOUND;
  151. /*
  152. * Note: the caller has already checked that offset is
  153. * suitably aligned and that len is 1, 2 or 4.
  154. */
  155. switch (len) {
  156. case 1:
  157. *val = in_8(addr);
  158. break;
  159. case 2:
  160. *val = in_le16(addr);
  161. break;
  162. default:
  163. *val = in_le32(addr);
  164. break;
  165. }
  166. return PCIBIOS_SUCCESSFUL;
  167. }
  168. static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
  169. int offset, int len, u32 val)
  170. {
  171. struct pci_controller *hose;
  172. volatile void __iomem *addr;
  173. hose = pci_bus_to_host(bus);
  174. if (hose == NULL)
  175. return PCIBIOS_DEVICE_NOT_FOUND;
  176. if (offset >= 0x100)
  177. return PCIBIOS_BAD_REGISTER_NUMBER;
  178. addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
  179. if (!addr)
  180. return PCIBIOS_DEVICE_NOT_FOUND;
  181. /*
  182. * Note: the caller has already checked that offset is
  183. * suitably aligned and that len is 1, 2 or 4.
  184. */
  185. switch (len) {
  186. case 1:
  187. out_8(addr, val);
  188. (void) in_8(addr);
  189. break;
  190. case 2:
  191. out_le16(addr, val);
  192. (void) in_le16(addr);
  193. break;
  194. default:
  195. out_le32(addr, val);
  196. (void) in_le32(addr);
  197. break;
  198. }
  199. return PCIBIOS_SUCCESSFUL;
  200. }
  201. static struct pci_ops macrisc_pci_ops =
  202. {
  203. macrisc_read_config,
  204. macrisc_write_config
  205. };
  206. #ifdef CONFIG_PPC32
  207. /*
  208. * Verify that a specific (bus, dev_fn) exists on chaos
  209. */
  210. static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
  211. {
  212. struct device_node *np;
  213. const u32 *vendor, *device;
  214. if (offset >= 0x100)
  215. return PCIBIOS_BAD_REGISTER_NUMBER;
  216. np = pci_busdev_to_OF_node(bus, devfn);
  217. if (np == NULL)
  218. return PCIBIOS_DEVICE_NOT_FOUND;
  219. vendor = get_property(np, "vendor-id", NULL);
  220. device = get_property(np, "device-id", NULL);
  221. if (vendor == NULL || device == NULL)
  222. return PCIBIOS_DEVICE_NOT_FOUND;
  223. if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
  224. && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
  225. return PCIBIOS_BAD_REGISTER_NUMBER;
  226. return PCIBIOS_SUCCESSFUL;
  227. }
  228. static int
  229. chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
  230. int len, u32 *val)
  231. {
  232. int result = chaos_validate_dev(bus, devfn, offset);
  233. if (result == PCIBIOS_BAD_REGISTER_NUMBER)
  234. *val = ~0U;
  235. if (result != PCIBIOS_SUCCESSFUL)
  236. return result;
  237. return macrisc_read_config(bus, devfn, offset, len, val);
  238. }
  239. static int
  240. chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
  241. int len, u32 val)
  242. {
  243. int result = chaos_validate_dev(bus, devfn, offset);
  244. if (result != PCIBIOS_SUCCESSFUL)
  245. return result;
  246. return macrisc_write_config(bus, devfn, offset, len, val);
  247. }
  248. static struct pci_ops chaos_pci_ops =
  249. {
  250. chaos_read_config,
  251. chaos_write_config
  252. };
  253. static void __init setup_chaos(struct pci_controller *hose,
  254. struct resource *addr)
  255. {
  256. /* assume a `chaos' bridge */
  257. hose->ops = &chaos_pci_ops;
  258. hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
  259. hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
  260. }
  261. #endif /* CONFIG_PPC32 */
  262. #ifdef CONFIG_PPC64
  263. /*
  264. * These versions of U3 HyperTransport config space access ops do not
  265. * implement self-view of the HT host yet
  266. */
  267. /*
  268. * This function deals with some "special cases" devices.
  269. *
  270. * 0 -> No special case
  271. * 1 -> Skip the device but act as if the access was successfull
  272. * (return 0xff's on reads, eventually, cache config space
  273. * accesses in a later version)
  274. * -1 -> Hide the device (unsuccessful acess)
  275. */
  276. static int u3_ht_skip_device(struct pci_controller *hose,
  277. struct pci_bus *bus, unsigned int devfn)
  278. {
  279. struct device_node *busdn, *dn;
  280. int i;
  281. /* We only allow config cycles to devices that are in OF device-tree
  282. * as we are apparently having some weird things going on with some
  283. * revs of K2 on recent G5s
  284. */
  285. if (bus->self)
  286. busdn = pci_device_to_OF_node(bus->self);
  287. else
  288. busdn = hose->arch_data;
  289. for (dn = busdn->child; dn; dn = dn->sibling)
  290. if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
  291. break;
  292. if (dn == NULL)
  293. return -1;
  294. /*
  295. * When a device in K2 is powered down, we die on config
  296. * cycle accesses. Fix that here.
  297. */
  298. for (i=0; i<2; i++)
  299. if (k2_skiplist[i] == dn)
  300. return 1;
  301. return 0;
  302. }
  303. #define U3_HT_CFA0(devfn, off) \
  304. ((((unsigned int)devfn) << 8) | offset)
  305. #define U3_HT_CFA1(bus, devfn, off) \
  306. (U3_HT_CFA0(devfn, off) \
  307. + (((unsigned int)bus) << 16) \
  308. + 0x01000000UL)
  309. static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
  310. u8 bus, u8 devfn, u8 offset)
  311. {
  312. if (bus == hose->first_busno) {
  313. /* For now, we don't self probe U3 HT bridge */
  314. if (PCI_SLOT(devfn) == 0)
  315. return NULL;
  316. return hose->cfg_data + U3_HT_CFA0(devfn, offset);
  317. } else
  318. return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
  319. }
  320. static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
  321. int offset, int len, u32 *val)
  322. {
  323. struct pci_controller *hose;
  324. volatile void __iomem *addr;
  325. hose = pci_bus_to_host(bus);
  326. if (hose == NULL)
  327. return PCIBIOS_DEVICE_NOT_FOUND;
  328. if (offset >= 0x100)
  329. return PCIBIOS_BAD_REGISTER_NUMBER;
  330. addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
  331. if (!addr)
  332. return PCIBIOS_DEVICE_NOT_FOUND;
  333. switch (u3_ht_skip_device(hose, bus, devfn)) {
  334. case 0:
  335. break;
  336. case 1:
  337. switch (len) {
  338. case 1:
  339. *val = 0xff; break;
  340. case 2:
  341. *val = 0xffff; break;
  342. default:
  343. *val = 0xfffffffful; break;
  344. }
  345. return PCIBIOS_SUCCESSFUL;
  346. default:
  347. return PCIBIOS_DEVICE_NOT_FOUND;
  348. }
  349. /*
  350. * Note: the caller has already checked that offset is
  351. * suitably aligned and that len is 1, 2 or 4.
  352. */
  353. switch (len) {
  354. case 1:
  355. *val = in_8(addr);
  356. break;
  357. case 2:
  358. *val = in_le16(addr);
  359. break;
  360. default:
  361. *val = in_le32(addr);
  362. break;
  363. }
  364. return PCIBIOS_SUCCESSFUL;
  365. }
  366. static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
  367. int offset, int len, u32 val)
  368. {
  369. struct pci_controller *hose;
  370. volatile void __iomem *addr;
  371. hose = pci_bus_to_host(bus);
  372. if (hose == NULL)
  373. return PCIBIOS_DEVICE_NOT_FOUND;
  374. if (offset >= 0x100)
  375. return PCIBIOS_BAD_REGISTER_NUMBER;
  376. addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
  377. if (!addr)
  378. return PCIBIOS_DEVICE_NOT_FOUND;
  379. switch (u3_ht_skip_device(hose, bus, devfn)) {
  380. case 0:
  381. break;
  382. case 1:
  383. return PCIBIOS_SUCCESSFUL;
  384. default:
  385. return PCIBIOS_DEVICE_NOT_FOUND;
  386. }
  387. /*
  388. * Note: the caller has already checked that offset is
  389. * suitably aligned and that len is 1, 2 or 4.
  390. */
  391. switch (len) {
  392. case 1:
  393. out_8(addr, val);
  394. (void) in_8(addr);
  395. break;
  396. case 2:
  397. out_le16(addr, val);
  398. (void) in_le16(addr);
  399. break;
  400. default:
  401. out_le32((u32 __iomem *)addr, val);
  402. (void) in_le32(addr);
  403. break;
  404. }
  405. return PCIBIOS_SUCCESSFUL;
  406. }
  407. static struct pci_ops u3_ht_pci_ops =
  408. {
  409. u3_ht_read_config,
  410. u3_ht_write_config
  411. };
  412. #define U4_PCIE_CFA0(devfn, off) \
  413. ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
  414. | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
  415. | ((((unsigned int)(off)) >> 8) << 28) \
  416. | (((unsigned int)(off)) & 0xfcU))
  417. #define U4_PCIE_CFA1(bus, devfn, off) \
  418. ((((unsigned int)(bus)) << 16) \
  419. |(((unsigned int)(devfn)) << 8) \
  420. | ((((unsigned int)(off)) >> 8) << 28) \
  421. |(((unsigned int)(off)) & 0xfcU) \
  422. |1UL)
  423. static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
  424. u8 bus, u8 dev_fn, int offset)
  425. {
  426. unsigned int caddr;
  427. if (bus == hose->first_busno) {
  428. caddr = U4_PCIE_CFA0(dev_fn, offset);
  429. } else
  430. caddr = U4_PCIE_CFA1(bus, dev_fn, offset);
  431. /* Uninorth will return garbage if we don't read back the value ! */
  432. do {
  433. out_le32(hose->cfg_addr, caddr);
  434. } while (in_le32(hose->cfg_addr) != caddr);
  435. offset &= 0x03;
  436. return hose->cfg_data + offset;
  437. }
  438. static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
  439. int offset, int len, u32 *val)
  440. {
  441. struct pci_controller *hose;
  442. volatile void __iomem *addr;
  443. hose = pci_bus_to_host(bus);
  444. if (hose == NULL)
  445. return PCIBIOS_DEVICE_NOT_FOUND;
  446. if (offset >= 0x1000)
  447. return PCIBIOS_BAD_REGISTER_NUMBER;
  448. addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
  449. if (!addr)
  450. return PCIBIOS_DEVICE_NOT_FOUND;
  451. /*
  452. * Note: the caller has already checked that offset is
  453. * suitably aligned and that len is 1, 2 or 4.
  454. */
  455. switch (len) {
  456. case 1:
  457. *val = in_8(addr);
  458. break;
  459. case 2:
  460. *val = in_le16(addr);
  461. break;
  462. default:
  463. *val = in_le32(addr);
  464. break;
  465. }
  466. return PCIBIOS_SUCCESSFUL;
  467. }
  468. static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
  469. int offset, int len, u32 val)
  470. {
  471. struct pci_controller *hose;
  472. volatile void __iomem *addr;
  473. hose = pci_bus_to_host(bus);
  474. if (hose == NULL)
  475. return PCIBIOS_DEVICE_NOT_FOUND;
  476. if (offset >= 0x1000)
  477. return PCIBIOS_BAD_REGISTER_NUMBER;
  478. addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
  479. if (!addr)
  480. return PCIBIOS_DEVICE_NOT_FOUND;
  481. /*
  482. * Note: the caller has already checked that offset is
  483. * suitably aligned and that len is 1, 2 or 4.
  484. */
  485. switch (len) {
  486. case 1:
  487. out_8(addr, val);
  488. (void) in_8(addr);
  489. break;
  490. case 2:
  491. out_le16(addr, val);
  492. (void) in_le16(addr);
  493. break;
  494. default:
  495. out_le32(addr, val);
  496. (void) in_le32(addr);
  497. break;
  498. }
  499. return PCIBIOS_SUCCESSFUL;
  500. }
  501. static struct pci_ops u4_pcie_pci_ops =
  502. {
  503. u4_pcie_read_config,
  504. u4_pcie_write_config
  505. };
  506. #endif /* CONFIG_PPC64 */
  507. #ifdef CONFIG_PPC32
  508. /*
  509. * For a bandit bridge, turn on cache coherency if necessary.
  510. * N.B. we could clean this up using the hose ops directly.
  511. */
  512. static void __init init_bandit(struct pci_controller *bp)
  513. {
  514. unsigned int vendev, magic;
  515. int rev;
  516. /* read the word at offset 0 in config space for device 11 */
  517. out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
  518. udelay(2);
  519. vendev = in_le32(bp->cfg_data);
  520. if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
  521. PCI_VENDOR_ID_APPLE) {
  522. /* read the revision id */
  523. out_le32(bp->cfg_addr,
  524. (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
  525. udelay(2);
  526. rev = in_8(bp->cfg_data);
  527. if (rev != BANDIT_REVID)
  528. printk(KERN_WARNING
  529. "Unknown revision %d for bandit\n", rev);
  530. } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
  531. printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
  532. return;
  533. }
  534. /* read the word at offset 0x50 */
  535. out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
  536. udelay(2);
  537. magic = in_le32(bp->cfg_data);
  538. if ((magic & BANDIT_COHERENT) != 0)
  539. return;
  540. magic |= BANDIT_COHERENT;
  541. udelay(2);
  542. out_le32(bp->cfg_data, magic);
  543. printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
  544. }
  545. /*
  546. * Tweak the PCI-PCI bridge chip on the blue & white G3s.
  547. */
  548. static void __init init_p2pbridge(void)
  549. {
  550. struct device_node *p2pbridge;
  551. struct pci_controller* hose;
  552. u8 bus, devfn;
  553. u16 val;
  554. /* XXX it would be better here to identify the specific
  555. PCI-PCI bridge chip we have. */
  556. if ((p2pbridge = find_devices("pci-bridge")) == 0
  557. || p2pbridge->parent == NULL
  558. || strcmp(p2pbridge->parent->name, "pci") != 0)
  559. return;
  560. if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
  561. DBG("Can't find PCI infos for PCI<->PCI bridge\n");
  562. return;
  563. }
  564. /* Warning: At this point, we have not yet renumbered all busses.
  565. * So we must use OF walking to find out hose
  566. */
  567. hose = pci_find_hose_for_OF_device(p2pbridge);
  568. if (!hose) {
  569. DBG("Can't find hose for PCI<->PCI bridge\n");
  570. return;
  571. }
  572. if (early_read_config_word(hose, bus, devfn,
  573. PCI_BRIDGE_CONTROL, &val) < 0) {
  574. printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
  575. " control\n");
  576. return;
  577. }
  578. val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
  579. early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
  580. }
  581. static void __init init_second_ohare(void)
  582. {
  583. struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
  584. unsigned char bus, devfn;
  585. unsigned short cmd;
  586. if (np == NULL)
  587. return;
  588. /* This must run before we initialize the PICs since the second
  589. * ohare hosts a PIC that will be accessed there.
  590. */
  591. if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
  592. struct pci_controller* hose =
  593. pci_find_hose_for_OF_device(np);
  594. if (!hose) {
  595. printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
  596. return;
  597. }
  598. early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
  599. cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  600. cmd &= ~PCI_COMMAND_IO;
  601. early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
  602. }
  603. has_second_ohare = 1;
  604. }
  605. /*
  606. * Some Apple desktop machines have a NEC PD720100A USB2 controller
  607. * on the motherboard. Open Firmware, on these, will disable the
  608. * EHCI part of it so it behaves like a pair of OHCI's. This fixup
  609. * code re-enables it ;)
  610. */
  611. static void __init fixup_nec_usb2(void)
  612. {
  613. struct device_node *nec;
  614. for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
  615. struct pci_controller *hose;
  616. u32 data;
  617. const u32 *prop;
  618. u8 bus, devfn;
  619. prop = get_property(nec, "vendor-id", NULL);
  620. if (prop == NULL)
  621. continue;
  622. if (0x1033 != *prop)
  623. continue;
  624. prop = get_property(nec, "device-id", NULL);
  625. if (prop == NULL)
  626. continue;
  627. if (0x0035 != *prop)
  628. continue;
  629. prop = get_property(nec, "reg", NULL);
  630. if (prop == NULL)
  631. continue;
  632. devfn = (prop[0] >> 8) & 0xff;
  633. bus = (prop[0] >> 16) & 0xff;
  634. if (PCI_FUNC(devfn) != 0)
  635. continue;
  636. hose = pci_find_hose_for_OF_device(nec);
  637. if (!hose)
  638. continue;
  639. early_read_config_dword(hose, bus, devfn, 0xe4, &data);
  640. if (data & 1UL) {
  641. printk("Found NEC PD720100A USB2 chip with disabled"
  642. " EHCI, fixing up...\n");
  643. data &= ~1UL;
  644. early_write_config_dword(hose, bus, devfn, 0xe4, data);
  645. }
  646. }
  647. }
  648. static void __init setup_bandit(struct pci_controller *hose,
  649. struct resource *addr)
  650. {
  651. hose->ops = &macrisc_pci_ops;
  652. hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
  653. hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
  654. init_bandit(hose);
  655. }
  656. static int __init setup_uninorth(struct pci_controller *hose,
  657. struct resource *addr)
  658. {
  659. pci_assign_all_buses = 1;
  660. has_uninorth = 1;
  661. hose->ops = &macrisc_pci_ops;
  662. hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
  663. hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
  664. /* We "know" that the bridge at f2000000 has the PCI slots. */
  665. return addr->start == 0xf2000000;
  666. }
  667. #endif /* CONFIG_PPC32 */
  668. #ifdef CONFIG_PPC64
  669. static void __init setup_u3_agp(struct pci_controller* hose)
  670. {
  671. /* On G5, we move AGP up to high bus number so we don't need
  672. * to reassign bus numbers for HT. If we ever have P2P bridges
  673. * on AGP, we'll have to move pci_assign_all_busses to the
  674. * pci_controller structure so we enable it for AGP and not for
  675. * HT childs.
  676. * We hard code the address because of the different size of
  677. * the reg address cell, we shall fix that by killing struct
  678. * reg_property and using some accessor functions instead
  679. */
  680. hose->first_busno = 0xf0;
  681. hose->last_busno = 0xff;
  682. has_uninorth = 1;
  683. hose->ops = &macrisc_pci_ops;
  684. hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
  685. hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
  686. u3_agp = hose;
  687. }
  688. static void __init setup_u4_pcie(struct pci_controller* hose)
  689. {
  690. /* We currently only implement the "non-atomic" config space, to
  691. * be optimised later.
  692. */
  693. hose->ops = &u4_pcie_pci_ops;
  694. hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
  695. hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
  696. /* The bus contains a bridge from root -> device, we need to
  697. * make it visible on bus 0 so that we pick the right type
  698. * of config cycles. If we didn't, we would have to force all
  699. * config cycles to be type 1. So we override the "bus-range"
  700. * property here
  701. */
  702. hose->first_busno = 0x00;
  703. hose->last_busno = 0xff;
  704. u4_pcie = hose;
  705. }
  706. static void __init setup_u3_ht(struct pci_controller* hose)
  707. {
  708. struct device_node *np = (struct device_node *)hose->arch_data;
  709. struct pci_controller *other = NULL;
  710. int i, cur;
  711. hose->ops = &u3_ht_pci_ops;
  712. /* We hard code the address because of the different size of
  713. * the reg address cell, we shall fix that by killing struct
  714. * reg_property and using some accessor functions instead
  715. */
  716. hose->cfg_data = ioremap(0xf2000000, 0x02000000);
  717. /*
  718. * /ht node doesn't expose a "ranges" property, so we "remove"
  719. * regions that have been allocated to AGP. So far, this version of
  720. * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions
  721. * to /ht. We need to fix that sooner or later by either parsing all
  722. * child "ranges" properties or figuring out the U3 address space
  723. * decoding logic and then read its configuration register (if any).
  724. */
  725. hose->io_base_phys = 0xf4000000;
  726. hose->pci_io_size = 0x00400000;
  727. hose->io_resource.name = np->full_name;
  728. hose->io_resource.start = 0;
  729. hose->io_resource.end = 0x003fffff;
  730. hose->io_resource.flags = IORESOURCE_IO;
  731. hose->pci_mem_offset = 0;
  732. hose->first_busno = 0;
  733. hose->last_busno = 0xef;
  734. hose->mem_resources[0].name = np->full_name;
  735. hose->mem_resources[0].start = 0x80000000;
  736. hose->mem_resources[0].end = 0xefffffff;
  737. hose->mem_resources[0].flags = IORESOURCE_MEM;
  738. u3_ht = hose;
  739. if (u3_agp != NULL)
  740. other = u3_agp;
  741. else if (u4_pcie != NULL)
  742. other = u4_pcie;
  743. if (other == NULL) {
  744. DBG("U3/4 has no AGP/PCIE, using full resource range\n");
  745. return;
  746. }
  747. /* Fixup bus range vs. PCIE */
  748. if (u4_pcie)
  749. hose->last_busno = u4_pcie->first_busno - 1;
  750. /* We "remove" the AGP resources from the resources allocated to HT,
  751. * that is we create "holes". However, that code does assumptions
  752. * that so far happen to be true (cross fingers...), typically that
  753. * resources in the AGP node are properly ordered
  754. */
  755. cur = 0;
  756. for (i=0; i<3; i++) {
  757. struct resource *res = &other->mem_resources[i];
  758. if (res->flags != IORESOURCE_MEM)
  759. continue;
  760. /* We don't care about "fine" resources */
  761. if (res->start >= 0xf0000000)
  762. continue;
  763. /* Check if it's just a matter of "shrinking" us in one
  764. * direction
  765. */
  766. if (hose->mem_resources[cur].start == res->start) {
  767. DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
  768. cur, hose->mem_resources[cur].start,
  769. res->end + 1);
  770. hose->mem_resources[cur].start = res->end + 1;
  771. continue;
  772. }
  773. if (hose->mem_resources[cur].end == res->end) {
  774. DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
  775. cur, hose->mem_resources[cur].end,
  776. res->start - 1);
  777. hose->mem_resources[cur].end = res->start - 1;
  778. continue;
  779. }
  780. /* No, it's not the case, we need a hole */
  781. if (cur == 2) {
  782. /* not enough resources for a hole, we drop part
  783. * of the range
  784. */
  785. printk(KERN_WARNING "Running out of resources"
  786. " for /ht host !\n");
  787. hose->mem_resources[cur].end = res->start - 1;
  788. continue;
  789. }
  790. cur++;
  791. DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
  792. cur-1, res->start - 1, cur, res->end + 1);
  793. hose->mem_resources[cur].name = np->full_name;
  794. hose->mem_resources[cur].flags = IORESOURCE_MEM;
  795. hose->mem_resources[cur].start = res->end + 1;
  796. hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
  797. hose->mem_resources[cur-1].end = res->start - 1;
  798. }
  799. }
  800. #endif /* CONFIG_PPC64 */
  801. /*
  802. * We assume that if we have a G3 powermac, we have one bridge called
  803. * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
  804. * if we have one or more bandit or chaos bridges, we don't have a MPC106.
  805. */
  806. static int __init add_bridge(struct device_node *dev)
  807. {
  808. int len;
  809. struct pci_controller *hose;
  810. struct resource rsrc;
  811. char *disp_name;
  812. const int *bus_range;
  813. int primary = 1, has_address = 0;
  814. DBG("Adding PCI host bridge %s\n", dev->full_name);
  815. /* Fetch host bridge registers address */
  816. has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
  817. /* Get bus range if any */
  818. bus_range = get_property(dev, "bus-range", &len);
  819. if (bus_range == NULL || len < 2 * sizeof(int)) {
  820. printk(KERN_WARNING "Can't get bus-range for %s, assume"
  821. " bus 0\n", dev->full_name);
  822. }
  823. /* XXX Different prototypes, to be merged */
  824. #ifdef CONFIG_PPC64
  825. hose = pcibios_alloc_controller(dev);
  826. #else
  827. hose = pcibios_alloc_controller();
  828. #endif
  829. if (!hose)
  830. return -ENOMEM;
  831. hose->arch_data = dev;
  832. hose->first_busno = bus_range ? bus_range[0] : 0;
  833. hose->last_busno = bus_range ? bus_range[1] : 0xff;
  834. disp_name = NULL;
  835. /* 64 bits only bridges */
  836. #ifdef CONFIG_PPC64
  837. if (device_is_compatible(dev, "u3-agp")) {
  838. setup_u3_agp(hose);
  839. disp_name = "U3-AGP";
  840. primary = 0;
  841. } else if (device_is_compatible(dev, "u3-ht")) {
  842. setup_u3_ht(hose);
  843. disp_name = "U3-HT";
  844. primary = 1;
  845. } else if (device_is_compatible(dev, "u4-pcie")) {
  846. setup_u4_pcie(hose);
  847. disp_name = "U4-PCIE";
  848. primary = 0;
  849. }
  850. printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
  851. " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
  852. #endif /* CONFIG_PPC64 */
  853. /* 32 bits only bridges */
  854. #ifdef CONFIG_PPC32
  855. if (device_is_compatible(dev, "uni-north")) {
  856. primary = setup_uninorth(hose, &rsrc);
  857. disp_name = "UniNorth";
  858. } else if (strcmp(dev->name, "pci") == 0) {
  859. /* XXX assume this is a mpc106 (grackle) */
  860. setup_grackle(hose);
  861. disp_name = "Grackle (MPC106)";
  862. } else if (strcmp(dev->name, "bandit") == 0) {
  863. setup_bandit(hose, &rsrc);
  864. disp_name = "Bandit";
  865. } else if (strcmp(dev->name, "chaos") == 0) {
  866. setup_chaos(hose, &rsrc);
  867. disp_name = "Chaos";
  868. primary = 0;
  869. }
  870. printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
  871. "Firmware bus number: %d->%d\n",
  872. disp_name, (unsigned long long)rsrc.start, hose->first_busno,
  873. hose->last_busno);
  874. #endif /* CONFIG_PPC32 */
  875. DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
  876. hose, hose->cfg_addr, hose->cfg_data);
  877. /* Interpret the "ranges" property */
  878. /* This also maps the I/O region and sets isa_io/mem_base */
  879. pci_process_bridge_OF_ranges(hose, dev, primary);
  880. /* Fixup "bus-range" OF property */
  881. fixup_bus_range(dev);
  882. return 0;
  883. }
  884. void __devinit pmac_pci_irq_fixup(struct pci_dev *dev)
  885. {
  886. #ifdef CONFIG_PPC32
  887. /* Fixup interrupt for the modem/ethernet combo controller.
  888. * on machines with a second ohare chip.
  889. * The number in the device tree (27) is bogus (correct for
  890. * the ethernet-only board but not the combo ethernet/modem
  891. * board). The real interrupt is 28 on the second controller
  892. * -> 28+32 = 60.
  893. */
  894. if (has_second_ohare &&
  895. dev->vendor == PCI_VENDOR_ID_DEC &&
  896. dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
  897. dev->irq = irq_create_mapping(NULL, 60);
  898. set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
  899. }
  900. #endif /* CONFIG_PPC32 */
  901. }
  902. #ifdef CONFIG_PPC64
  903. static void __init pmac_fixup_phb_resources(void)
  904. {
  905. struct pci_controller *hose, *tmp;
  906. list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
  907. printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
  908. hose->global_number,
  909. hose->io_resource.start, hose->io_resource.end);
  910. }
  911. }
  912. #endif
  913. void __init pmac_pci_init(void)
  914. {
  915. struct device_node *np, *root;
  916. struct device_node *ht = NULL;
  917. root = of_find_node_by_path("/");
  918. if (root == NULL) {
  919. printk(KERN_CRIT "pmac_pci_init: can't find root "
  920. "of device tree\n");
  921. return;
  922. }
  923. for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
  924. if (np->name == NULL)
  925. continue;
  926. if (strcmp(np->name, "bandit") == 0
  927. || strcmp(np->name, "chaos") == 0
  928. || strcmp(np->name, "pci") == 0) {
  929. if (add_bridge(np) == 0)
  930. of_node_get(np);
  931. }
  932. if (strcmp(np->name, "ht") == 0) {
  933. of_node_get(np);
  934. ht = np;
  935. }
  936. }
  937. of_node_put(root);
  938. #ifdef CONFIG_PPC64
  939. /* Probe HT last as it relies on the agp resources to be already
  940. * setup
  941. */
  942. if (ht && add_bridge(ht) != 0)
  943. of_node_put(ht);
  944. /*
  945. * We need to call pci_setup_phb_io for the HT bridge first
  946. * so it gets the I/O port numbers starting at 0, and we
  947. * need to call it for the AGP bridge after that so it gets
  948. * small positive I/O port numbers.
  949. */
  950. if (u3_ht)
  951. pci_setup_phb_io(u3_ht, 1);
  952. if (u3_agp)
  953. pci_setup_phb_io(u3_agp, 0);
  954. if (u4_pcie)
  955. pci_setup_phb_io(u4_pcie, 0);
  956. /*
  957. * On ppc64, fixup the IO resources on our host bridges as
  958. * the common code does it only for children of the host bridges
  959. */
  960. pmac_fixup_phb_resources();
  961. /* Setup the linkage between OF nodes and PHBs */
  962. pci_devs_phb_init();
  963. /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
  964. * assume there is no P2P bridge on the AGP bus, which should be a
  965. * safe assumptions for now. We should do something better in the
  966. * future though
  967. */
  968. if (u3_agp) {
  969. struct device_node *np = u3_agp->arch_data;
  970. PCI_DN(np)->busno = 0xf0;
  971. for (np = np->child; np; np = np->sibling)
  972. PCI_DN(np)->busno = 0xf0;
  973. }
  974. /* pmac_check_ht_link(); */
  975. /* Tell pci.c to not use the common resource allocation mechanism */
  976. pci_probe_only = 1;
  977. #else /* CONFIG_PPC64 */
  978. init_p2pbridge();
  979. init_second_ohare();
  980. fixup_nec_usb2();
  981. /* We are still having some issues with the Xserve G4, enabling
  982. * some offset between bus number and domains for now when we
  983. * assign all busses should help for now
  984. */
  985. if (pci_assign_all_buses)
  986. pcibios_assign_bus_offset = 0x10;
  987. #endif
  988. }
  989. int
  990. pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
  991. {
  992. struct device_node* node;
  993. int updatecfg = 0;
  994. int uninorth_child;
  995. node = pci_device_to_OF_node(dev);
  996. /* We don't want to enable USB controllers absent from the OF tree
  997. * (iBook second controller)
  998. */
  999. if (dev->vendor == PCI_VENDOR_ID_APPLE
  1000. && dev->class == PCI_CLASS_SERIAL_USB_OHCI
  1001. && !node) {
  1002. printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
  1003. pci_name(dev));
  1004. return -EINVAL;
  1005. }
  1006. if (!node)
  1007. return 0;
  1008. uninorth_child = node->parent &&
  1009. device_is_compatible(node->parent, "uni-north");
  1010. /* Firewire & GMAC were disabled after PCI probe, the driver is
  1011. * claiming them, we must re-enable them now.
  1012. */
  1013. if (uninorth_child && !strcmp(node->name, "firewire") &&
  1014. (device_is_compatible(node, "pci106b,18") ||
  1015. device_is_compatible(node, "pci106b,30") ||
  1016. device_is_compatible(node, "pci11c1,5811"))) {
  1017. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
  1018. pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
  1019. updatecfg = 1;
  1020. }
  1021. if (uninorth_child && !strcmp(node->name, "ethernet") &&
  1022. device_is_compatible(node, "gmac")) {
  1023. pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
  1024. updatecfg = 1;
  1025. }
  1026. if (updatecfg) {
  1027. u16 cmd;
  1028. /*
  1029. * Make sure PCI is correctly configured
  1030. *
  1031. * We use old pci_bios versions of the function since, by
  1032. * default, gmac is not powered up, and so will be absent
  1033. * from the kernel initial PCI lookup.
  1034. *
  1035. * Should be replaced by 2.4 new PCI mechanisms and really
  1036. * register the device.
  1037. */
  1038. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1039. cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  1040. | PCI_COMMAND_INVALIDATE;
  1041. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1042. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
  1043. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
  1044. L1_CACHE_BYTES >> 2);
  1045. }
  1046. return 0;
  1047. }
  1048. /* We power down some devices after they have been probed. They'll
  1049. * be powered back on later on
  1050. */
  1051. void __init pmac_pcibios_after_init(void)
  1052. {
  1053. struct device_node* nd;
  1054. #ifdef CONFIG_BLK_DEV_IDE
  1055. struct pci_dev *dev = NULL;
  1056. /* OF fails to initialize IDE controllers on macs
  1057. * (and maybe other machines)
  1058. *
  1059. * Ideally, this should be moved to the IDE layer, but we need
  1060. * to check specifically with Andre Hedrick how to do it cleanly
  1061. * since the common IDE code seem to care about the fact that the
  1062. * BIOS may have disabled a controller.
  1063. *
  1064. * -- BenH
  1065. */
  1066. for_each_pci_dev(dev) {
  1067. if ((dev->class >> 16) != PCI_BASE_CLASS_STORAGE)
  1068. continue;
  1069. if (pci_enable_device(dev))
  1070. printk(KERN_WARNING
  1071. "pci: Failed to enable %s\n", pci_name(dev));
  1072. }
  1073. #endif /* CONFIG_BLK_DEV_IDE */
  1074. nd = find_devices("firewire");
  1075. while (nd) {
  1076. if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
  1077. device_is_compatible(nd, "pci106b,30") ||
  1078. device_is_compatible(nd, "pci11c1,5811"))
  1079. && device_is_compatible(nd->parent, "uni-north")) {
  1080. pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
  1081. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
  1082. }
  1083. nd = nd->next;
  1084. }
  1085. nd = find_devices("ethernet");
  1086. while (nd) {
  1087. if (nd->parent && device_is_compatible(nd, "gmac")
  1088. && device_is_compatible(nd->parent, "uni-north"))
  1089. pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
  1090. nd = nd->next;
  1091. }
  1092. }
  1093. #ifdef CONFIG_PPC32
  1094. void pmac_pci_fixup_cardbus(struct pci_dev* dev)
  1095. {
  1096. if (!machine_is(powermac))
  1097. return;
  1098. /*
  1099. * Fix the interrupt routing on the various cardbus bridges
  1100. * used on powerbooks
  1101. */
  1102. if (dev->vendor != PCI_VENDOR_ID_TI)
  1103. return;
  1104. if (dev->device == PCI_DEVICE_ID_TI_1130 ||
  1105. dev->device == PCI_DEVICE_ID_TI_1131) {
  1106. u8 val;
  1107. /* Enable PCI interrupt */
  1108. if (pci_read_config_byte(dev, 0x91, &val) == 0)
  1109. pci_write_config_byte(dev, 0x91, val | 0x30);
  1110. /* Disable ISA interrupt mode */
  1111. if (pci_read_config_byte(dev, 0x92, &val) == 0)
  1112. pci_write_config_byte(dev, 0x92, val & ~0x06);
  1113. }
  1114. if (dev->device == PCI_DEVICE_ID_TI_1210 ||
  1115. dev->device == PCI_DEVICE_ID_TI_1211 ||
  1116. dev->device == PCI_DEVICE_ID_TI_1410 ||
  1117. dev->device == PCI_DEVICE_ID_TI_1510) {
  1118. u8 val;
  1119. /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
  1120. signal out the MFUNC0 pin */
  1121. if (pci_read_config_byte(dev, 0x8c, &val) == 0)
  1122. pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
  1123. /* Disable ISA interrupt mode */
  1124. if (pci_read_config_byte(dev, 0x92, &val) == 0)
  1125. pci_write_config_byte(dev, 0x92, val & ~0x06);
  1126. }
  1127. }
  1128. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
  1129. void pmac_pci_fixup_pciata(struct pci_dev* dev)
  1130. {
  1131. u8 progif = 0;
  1132. /*
  1133. * On PowerMacs, we try to switch any PCI ATA controller to
  1134. * fully native mode
  1135. */
  1136. if (!machine_is(powermac))
  1137. return;
  1138. /* Some controllers don't have the class IDE */
  1139. if (dev->vendor == PCI_VENDOR_ID_PROMISE)
  1140. switch(dev->device) {
  1141. case PCI_DEVICE_ID_PROMISE_20246:
  1142. case PCI_DEVICE_ID_PROMISE_20262:
  1143. case PCI_DEVICE_ID_PROMISE_20263:
  1144. case PCI_DEVICE_ID_PROMISE_20265:
  1145. case PCI_DEVICE_ID_PROMISE_20267:
  1146. case PCI_DEVICE_ID_PROMISE_20268:
  1147. case PCI_DEVICE_ID_PROMISE_20269:
  1148. case PCI_DEVICE_ID_PROMISE_20270:
  1149. case PCI_DEVICE_ID_PROMISE_20271:
  1150. case PCI_DEVICE_ID_PROMISE_20275:
  1151. case PCI_DEVICE_ID_PROMISE_20276:
  1152. case PCI_DEVICE_ID_PROMISE_20277:
  1153. goto good;
  1154. }
  1155. /* Others, check PCI class */
  1156. if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
  1157. return;
  1158. good:
  1159. pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
  1160. if ((progif & 5) != 5) {
  1161. printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n",
  1162. pci_name(dev));
  1163. (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
  1164. if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
  1165. (progif & 5) != 5)
  1166. printk(KERN_ERR "Rewrite of PROGIF failed !\n");
  1167. }
  1168. }
  1169. DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
  1170. #endif
  1171. /*
  1172. * Disable second function on K2-SATA, it's broken
  1173. * and disable IO BARs on first one
  1174. */
  1175. static void fixup_k2_sata(struct pci_dev* dev)
  1176. {
  1177. int i;
  1178. u16 cmd;
  1179. if (PCI_FUNC(dev->devfn) > 0) {
  1180. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1181. cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
  1182. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1183. for (i = 0; i < 6; i++) {
  1184. dev->resource[i].start = dev->resource[i].end = 0;
  1185. dev->resource[i].flags = 0;
  1186. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
  1187. 0);
  1188. }
  1189. } else {
  1190. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  1191. cmd &= ~PCI_COMMAND_IO;
  1192. pci_write_config_word(dev, PCI_COMMAND, cmd);
  1193. for (i = 0; i < 5; i++) {
  1194. dev->resource[i].start = dev->resource[i].end = 0;
  1195. dev->resource[i].flags = 0;
  1196. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
  1197. 0);
  1198. }
  1199. }
  1200. }
  1201. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);