ymfpci_main.c 72 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/delay.h>
  21. #include <linux/firmware.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/sched.h>
  26. #include <linux/slab.h>
  27. #include <linux/vmalloc.h>
  28. #include <sound/core.h>
  29. #include <sound/control.h>
  30. #include <sound/info.h>
  31. #include <sound/tlv.h>
  32. #include <sound/ymfpci.h>
  33. #include <sound/asoundef.h>
  34. #include <sound/mpu401.h>
  35. #include <asm/io.h>
  36. #include <asm/byteorder.h>
  37. /*
  38. * common I/O routines
  39. */
  40. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  41. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  42. {
  43. return readb(chip->reg_area_virt + offset);
  44. }
  45. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  46. {
  47. writeb(val, chip->reg_area_virt + offset);
  48. }
  49. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  50. {
  51. return readw(chip->reg_area_virt + offset);
  52. }
  53. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  54. {
  55. writew(val, chip->reg_area_virt + offset);
  56. }
  57. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  58. {
  59. return readl(chip->reg_area_virt + offset);
  60. }
  61. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  62. {
  63. writel(val, chip->reg_area_virt + offset);
  64. }
  65. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  66. {
  67. unsigned long end_time;
  68. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  69. end_time = jiffies + msecs_to_jiffies(750);
  70. do {
  71. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  72. return 0;
  73. schedule_timeout_uninterruptible(1);
  74. } while (time_before(jiffies, end_time));
  75. snd_printk(KERN_ERR "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  76. return -EBUSY;
  77. }
  78. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  79. {
  80. struct snd_ymfpci *chip = ac97->private_data;
  81. u32 cmd;
  82. snd_ymfpci_codec_ready(chip, 0);
  83. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  84. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  85. }
  86. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  87. {
  88. struct snd_ymfpci *chip = ac97->private_data;
  89. if (snd_ymfpci_codec_ready(chip, 0))
  90. return ~0;
  91. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  92. if (snd_ymfpci_codec_ready(chip, 0))
  93. return ~0;
  94. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  95. int i;
  96. for (i = 0; i < 600; i++)
  97. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  98. }
  99. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  100. }
  101. /*
  102. * Misc routines
  103. */
  104. static u32 snd_ymfpci_calc_delta(u32 rate)
  105. {
  106. switch (rate) {
  107. case 8000: return 0x02aaab00;
  108. case 11025: return 0x03accd00;
  109. case 16000: return 0x05555500;
  110. case 22050: return 0x07599a00;
  111. case 32000: return 0x0aaaab00;
  112. case 44100: return 0x0eb33300;
  113. default: return ((rate << 16) / 375) << 5;
  114. }
  115. }
  116. static u32 def_rate[8] = {
  117. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  118. };
  119. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  120. {
  121. u32 i;
  122. static u32 val[8] = {
  123. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  124. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  125. };
  126. if (rate == 44100)
  127. return 0x40000000; /* FIXME: What's the right value? */
  128. for (i = 0; i < 8; i++)
  129. if (rate <= def_rate[i])
  130. return val[i];
  131. return val[0];
  132. }
  133. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  134. {
  135. u32 i;
  136. static u32 val[8] = {
  137. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  138. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  139. };
  140. if (rate == 44100)
  141. return 0x370A0000;
  142. for (i = 0; i < 8; i++)
  143. if (rate <= def_rate[i])
  144. return val[i];
  145. return val[0];
  146. }
  147. /*
  148. * Hardware start management
  149. */
  150. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  151. {
  152. unsigned long flags;
  153. spin_lock_irqsave(&chip->reg_lock, flags);
  154. if (chip->start_count++ > 0)
  155. goto __end;
  156. snd_ymfpci_writel(chip, YDSXGR_MODE,
  157. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  158. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  159. __end:
  160. spin_unlock_irqrestore(&chip->reg_lock, flags);
  161. }
  162. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  163. {
  164. unsigned long flags;
  165. long timeout = 1000;
  166. spin_lock_irqsave(&chip->reg_lock, flags);
  167. if (--chip->start_count > 0)
  168. goto __end;
  169. snd_ymfpci_writel(chip, YDSXGR_MODE,
  170. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  171. while (timeout-- > 0) {
  172. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  173. break;
  174. }
  175. if (atomic_read(&chip->interrupt_sleep_count)) {
  176. atomic_set(&chip->interrupt_sleep_count, 0);
  177. wake_up(&chip->interrupt_sleep);
  178. }
  179. __end:
  180. spin_unlock_irqrestore(&chip->reg_lock, flags);
  181. }
  182. /*
  183. * Playback voice management
  184. */
  185. static int voice_alloc(struct snd_ymfpci *chip,
  186. enum snd_ymfpci_voice_type type, int pair,
  187. struct snd_ymfpci_voice **rvoice)
  188. {
  189. struct snd_ymfpci_voice *voice, *voice2;
  190. int idx;
  191. *rvoice = NULL;
  192. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  193. voice = &chip->voices[idx];
  194. voice2 = pair ? &chip->voices[idx+1] : NULL;
  195. if (voice->use || (voice2 && voice2->use))
  196. continue;
  197. voice->use = 1;
  198. if (voice2)
  199. voice2->use = 1;
  200. switch (type) {
  201. case YMFPCI_PCM:
  202. voice->pcm = 1;
  203. if (voice2)
  204. voice2->pcm = 1;
  205. break;
  206. case YMFPCI_SYNTH:
  207. voice->synth = 1;
  208. break;
  209. case YMFPCI_MIDI:
  210. voice->midi = 1;
  211. break;
  212. }
  213. snd_ymfpci_hw_start(chip);
  214. if (voice2)
  215. snd_ymfpci_hw_start(chip);
  216. *rvoice = voice;
  217. return 0;
  218. }
  219. return -ENOMEM;
  220. }
  221. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  222. enum snd_ymfpci_voice_type type, int pair,
  223. struct snd_ymfpci_voice **rvoice)
  224. {
  225. unsigned long flags;
  226. int result;
  227. snd_assert(rvoice != NULL, return -EINVAL);
  228. snd_assert(!pair || type == YMFPCI_PCM, return -EINVAL);
  229. spin_lock_irqsave(&chip->voice_lock, flags);
  230. for (;;) {
  231. result = voice_alloc(chip, type, pair, rvoice);
  232. if (result == 0 || type != YMFPCI_PCM)
  233. break;
  234. /* TODO: synth/midi voice deallocation */
  235. break;
  236. }
  237. spin_unlock_irqrestore(&chip->voice_lock, flags);
  238. return result;
  239. }
  240. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  241. {
  242. unsigned long flags;
  243. snd_assert(pvoice != NULL, return -EINVAL);
  244. snd_ymfpci_hw_stop(chip);
  245. spin_lock_irqsave(&chip->voice_lock, flags);
  246. if (pvoice->number == chip->src441_used) {
  247. chip->src441_used = -1;
  248. pvoice->ypcm->use_441_slot = 0;
  249. }
  250. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  251. pvoice->ypcm = NULL;
  252. pvoice->interrupt = NULL;
  253. spin_unlock_irqrestore(&chip->voice_lock, flags);
  254. return 0;
  255. }
  256. /*
  257. * PCM part
  258. */
  259. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  260. {
  261. struct snd_ymfpci_pcm *ypcm;
  262. u32 pos, delta;
  263. if ((ypcm = voice->ypcm) == NULL)
  264. return;
  265. if (ypcm->substream == NULL)
  266. return;
  267. spin_lock(&chip->reg_lock);
  268. if (ypcm->running) {
  269. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  270. if (pos < ypcm->last_pos)
  271. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  272. else
  273. delta = pos - ypcm->last_pos;
  274. ypcm->period_pos += delta;
  275. ypcm->last_pos = pos;
  276. if (ypcm->period_pos >= ypcm->period_size) {
  277. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  278. ypcm->period_pos %= ypcm->period_size;
  279. spin_unlock(&chip->reg_lock);
  280. snd_pcm_period_elapsed(ypcm->substream);
  281. spin_lock(&chip->reg_lock);
  282. }
  283. if (unlikely(ypcm->update_pcm_vol)) {
  284. unsigned int subs = ypcm->substream->number;
  285. unsigned int next_bank = 1 - chip->active_bank;
  286. struct snd_ymfpci_playback_bank *bank;
  287. u32 volume;
  288. bank = &voice->bank[next_bank];
  289. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  290. bank->left_gain_end = volume;
  291. if (ypcm->output_rear)
  292. bank->eff2_gain_end = volume;
  293. if (ypcm->voices[1])
  294. bank = &ypcm->voices[1]->bank[next_bank];
  295. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  296. bank->right_gain_end = volume;
  297. if (ypcm->output_rear)
  298. bank->eff3_gain_end = volume;
  299. ypcm->update_pcm_vol--;
  300. }
  301. }
  302. spin_unlock(&chip->reg_lock);
  303. }
  304. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  305. {
  306. struct snd_pcm_runtime *runtime = substream->runtime;
  307. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  308. struct snd_ymfpci *chip = ypcm->chip;
  309. u32 pos, delta;
  310. spin_lock(&chip->reg_lock);
  311. if (ypcm->running) {
  312. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  313. if (pos < ypcm->last_pos)
  314. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  315. else
  316. delta = pos - ypcm->last_pos;
  317. ypcm->period_pos += delta;
  318. ypcm->last_pos = pos;
  319. if (ypcm->period_pos >= ypcm->period_size) {
  320. ypcm->period_pos %= ypcm->period_size;
  321. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  322. spin_unlock(&chip->reg_lock);
  323. snd_pcm_period_elapsed(substream);
  324. spin_lock(&chip->reg_lock);
  325. }
  326. }
  327. spin_unlock(&chip->reg_lock);
  328. }
  329. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  330. int cmd)
  331. {
  332. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  333. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  334. struct snd_kcontrol *kctl = NULL;
  335. int result = 0;
  336. spin_lock(&chip->reg_lock);
  337. if (ypcm->voices[0] == NULL) {
  338. result = -EINVAL;
  339. goto __unlock;
  340. }
  341. switch (cmd) {
  342. case SNDRV_PCM_TRIGGER_START:
  343. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  344. case SNDRV_PCM_TRIGGER_RESUME:
  345. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  346. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  347. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  348. ypcm->running = 1;
  349. break;
  350. case SNDRV_PCM_TRIGGER_STOP:
  351. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  352. kctl = chip->pcm_mixer[substream->number].ctl;
  353. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  354. }
  355. /* fall through */
  356. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  357. case SNDRV_PCM_TRIGGER_SUSPEND:
  358. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  359. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  360. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  361. ypcm->running = 0;
  362. break;
  363. default:
  364. result = -EINVAL;
  365. break;
  366. }
  367. __unlock:
  368. spin_unlock(&chip->reg_lock);
  369. if (kctl)
  370. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  371. return result;
  372. }
  373. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  374. int cmd)
  375. {
  376. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  377. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  378. int result = 0;
  379. u32 tmp;
  380. spin_lock(&chip->reg_lock);
  381. switch (cmd) {
  382. case SNDRV_PCM_TRIGGER_START:
  383. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  384. case SNDRV_PCM_TRIGGER_RESUME:
  385. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  386. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  387. ypcm->running = 1;
  388. break;
  389. case SNDRV_PCM_TRIGGER_STOP:
  390. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  391. case SNDRV_PCM_TRIGGER_SUSPEND:
  392. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  393. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  394. ypcm->running = 0;
  395. break;
  396. default:
  397. result = -EINVAL;
  398. break;
  399. }
  400. spin_unlock(&chip->reg_lock);
  401. return result;
  402. }
  403. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  404. {
  405. int err;
  406. if (ypcm->voices[1] != NULL && voices < 2) {
  407. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  408. ypcm->voices[1] = NULL;
  409. }
  410. if (voices == 1 && ypcm->voices[0] != NULL)
  411. return 0; /* already allocated */
  412. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  413. return 0; /* already allocated */
  414. if (voices > 1) {
  415. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  416. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  417. ypcm->voices[0] = NULL;
  418. }
  419. }
  420. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  421. if (err < 0)
  422. return err;
  423. ypcm->voices[0]->ypcm = ypcm;
  424. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  425. if (voices > 1) {
  426. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  427. ypcm->voices[1]->ypcm = ypcm;
  428. }
  429. return 0;
  430. }
  431. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  432. struct snd_pcm_runtime *runtime,
  433. int has_pcm_volume)
  434. {
  435. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  436. u32 format;
  437. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  438. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  439. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  440. struct snd_ymfpci_playback_bank *bank;
  441. unsigned int nbank;
  442. u32 vol_left, vol_right;
  443. u8 use_left, use_right;
  444. unsigned long flags;
  445. snd_assert(voice != NULL, return);
  446. if (runtime->channels == 1) {
  447. use_left = 1;
  448. use_right = 1;
  449. } else {
  450. use_left = (voiceidx & 1) == 0;
  451. use_right = !use_left;
  452. }
  453. if (has_pcm_volume) {
  454. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  455. [ypcm->substream->number].left << 15);
  456. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  457. [ypcm->substream->number].right << 15);
  458. } else {
  459. vol_left = cpu_to_le32(0x40000000);
  460. vol_right = cpu_to_le32(0x40000000);
  461. }
  462. spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
  463. format = runtime->channels == 2 ? 0x00010000 : 0;
  464. if (snd_pcm_format_width(runtime->format) == 8)
  465. format |= 0x80000000;
  466. else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  467. runtime->rate == 44100 && runtime->channels == 2 &&
  468. voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
  469. ypcm->chip->src441_used == voice->number)) {
  470. ypcm->chip->src441_used = voice->number;
  471. ypcm->use_441_slot = 1;
  472. format |= 0x10000000;
  473. }
  474. if (ypcm->chip->src441_used == voice->number &&
  475. (format & 0x10000000) == 0) {
  476. ypcm->chip->src441_used = -1;
  477. ypcm->use_441_slot = 0;
  478. }
  479. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  480. format |= 1;
  481. spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
  482. for (nbank = 0; nbank < 2; nbank++) {
  483. bank = &voice->bank[nbank];
  484. memset(bank, 0, sizeof(*bank));
  485. bank->format = cpu_to_le32(format);
  486. bank->base = cpu_to_le32(runtime->dma_addr);
  487. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  488. bank->lpfQ = cpu_to_le32(lpfQ);
  489. bank->delta =
  490. bank->delta_end = cpu_to_le32(delta);
  491. bank->lpfK =
  492. bank->lpfK_end = cpu_to_le32(lpfK);
  493. bank->eg_gain =
  494. bank->eg_gain_end = cpu_to_le32(0x40000000);
  495. if (ypcm->output_front) {
  496. if (use_left) {
  497. bank->left_gain =
  498. bank->left_gain_end = vol_left;
  499. }
  500. if (use_right) {
  501. bank->right_gain =
  502. bank->right_gain_end = vol_right;
  503. }
  504. }
  505. if (ypcm->output_rear) {
  506. if (!ypcm->swap_rear) {
  507. if (use_left) {
  508. bank->eff2_gain =
  509. bank->eff2_gain_end = vol_left;
  510. }
  511. if (use_right) {
  512. bank->eff3_gain =
  513. bank->eff3_gain_end = vol_right;
  514. }
  515. } else {
  516. /* The SPDIF out channels seem to be swapped, so we have
  517. * to swap them here, too. The rear analog out channels
  518. * will be wrong, but otherwise AC3 would not work.
  519. */
  520. if (use_left) {
  521. bank->eff3_gain =
  522. bank->eff3_gain_end = vol_left;
  523. }
  524. if (use_right) {
  525. bank->eff2_gain =
  526. bank->eff2_gain_end = vol_right;
  527. }
  528. }
  529. }
  530. }
  531. }
  532. static int __devinit snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  533. {
  534. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  535. 4096, &chip->ac3_tmp_base) < 0)
  536. return -ENOMEM;
  537. chip->bank_effect[3][0]->base =
  538. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  539. chip->bank_effect[3][0]->loop_end =
  540. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  541. chip->bank_effect[4][0]->base =
  542. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  543. chip->bank_effect[4][0]->loop_end =
  544. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  545. spin_lock_irq(&chip->reg_lock);
  546. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  547. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  548. spin_unlock_irq(&chip->reg_lock);
  549. return 0;
  550. }
  551. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  552. {
  553. spin_lock_irq(&chip->reg_lock);
  554. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  555. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  556. spin_unlock_irq(&chip->reg_lock);
  557. // snd_ymfpci_irq_wait(chip);
  558. if (chip->ac3_tmp_base.area) {
  559. snd_dma_free_pages(&chip->ac3_tmp_base);
  560. chip->ac3_tmp_base.area = NULL;
  561. }
  562. return 0;
  563. }
  564. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  565. struct snd_pcm_hw_params *hw_params)
  566. {
  567. struct snd_pcm_runtime *runtime = substream->runtime;
  568. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  569. int err;
  570. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  571. return err;
  572. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  573. return err;
  574. return 0;
  575. }
  576. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  577. {
  578. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  579. struct snd_pcm_runtime *runtime = substream->runtime;
  580. struct snd_ymfpci_pcm *ypcm;
  581. if (runtime->private_data == NULL)
  582. return 0;
  583. ypcm = runtime->private_data;
  584. /* wait, until the PCI operations are not finished */
  585. snd_ymfpci_irq_wait(chip);
  586. snd_pcm_lib_free_pages(substream);
  587. if (ypcm->voices[1]) {
  588. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  589. ypcm->voices[1] = NULL;
  590. }
  591. if (ypcm->voices[0]) {
  592. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  593. ypcm->voices[0] = NULL;
  594. }
  595. return 0;
  596. }
  597. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  598. {
  599. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  600. struct snd_pcm_runtime *runtime = substream->runtime;
  601. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  602. struct snd_kcontrol *kctl;
  603. unsigned int nvoice;
  604. ypcm->period_size = runtime->period_size;
  605. ypcm->buffer_size = runtime->buffer_size;
  606. ypcm->period_pos = 0;
  607. ypcm->last_pos = 0;
  608. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  609. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  610. substream->pcm == chip->pcm);
  611. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  612. kctl = chip->pcm_mixer[substream->number].ctl;
  613. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  614. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  615. }
  616. return 0;
  617. }
  618. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  619. struct snd_pcm_hw_params *hw_params)
  620. {
  621. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  622. }
  623. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  624. {
  625. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  626. /* wait, until the PCI operations are not finished */
  627. snd_ymfpci_irq_wait(chip);
  628. return snd_pcm_lib_free_pages(substream);
  629. }
  630. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  631. {
  632. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  633. struct snd_pcm_runtime *runtime = substream->runtime;
  634. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  635. struct snd_ymfpci_capture_bank * bank;
  636. int nbank;
  637. u32 rate, format;
  638. ypcm->period_size = runtime->period_size;
  639. ypcm->buffer_size = runtime->buffer_size;
  640. ypcm->period_pos = 0;
  641. ypcm->last_pos = 0;
  642. ypcm->shift = 0;
  643. rate = ((48000 * 4096) / runtime->rate) - 1;
  644. format = 0;
  645. if (runtime->channels == 2) {
  646. format |= 2;
  647. ypcm->shift++;
  648. }
  649. if (snd_pcm_format_width(runtime->format) == 8)
  650. format |= 1;
  651. else
  652. ypcm->shift++;
  653. switch (ypcm->capture_bank_number) {
  654. case 0:
  655. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  656. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  657. break;
  658. case 1:
  659. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  660. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  661. break;
  662. }
  663. for (nbank = 0; nbank < 2; nbank++) {
  664. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  665. bank->base = cpu_to_le32(runtime->dma_addr);
  666. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  667. bank->start = 0;
  668. bank->num_of_loops = 0;
  669. }
  670. return 0;
  671. }
  672. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  673. {
  674. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  675. struct snd_pcm_runtime *runtime = substream->runtime;
  676. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  677. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  678. if (!(ypcm->running && voice))
  679. return 0;
  680. return le32_to_cpu(voice->bank[chip->active_bank].start);
  681. }
  682. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  683. {
  684. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  685. struct snd_pcm_runtime *runtime = substream->runtime;
  686. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  687. if (!ypcm->running)
  688. return 0;
  689. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  690. }
  691. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  692. {
  693. wait_queue_t wait;
  694. int loops = 4;
  695. while (loops-- > 0) {
  696. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  697. continue;
  698. init_waitqueue_entry(&wait, current);
  699. add_wait_queue(&chip->interrupt_sleep, &wait);
  700. atomic_inc(&chip->interrupt_sleep_count);
  701. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  702. remove_wait_queue(&chip->interrupt_sleep, &wait);
  703. }
  704. }
  705. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  706. {
  707. struct snd_ymfpci *chip = dev_id;
  708. u32 status, nvoice, mode;
  709. struct snd_ymfpci_voice *voice;
  710. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  711. if (status & 0x80000000) {
  712. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  713. spin_lock(&chip->voice_lock);
  714. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  715. voice = &chip->voices[nvoice];
  716. if (voice->interrupt)
  717. voice->interrupt(chip, voice);
  718. }
  719. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  720. if (chip->capture_substream[nvoice])
  721. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  722. }
  723. #if 0
  724. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  725. if (chip->effect_substream[nvoice])
  726. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  727. }
  728. #endif
  729. spin_unlock(&chip->voice_lock);
  730. spin_lock(&chip->reg_lock);
  731. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  732. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  733. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  734. spin_unlock(&chip->reg_lock);
  735. if (atomic_read(&chip->interrupt_sleep_count)) {
  736. atomic_set(&chip->interrupt_sleep_count, 0);
  737. wake_up(&chip->interrupt_sleep);
  738. }
  739. }
  740. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  741. if (status & 1) {
  742. if (chip->timer)
  743. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  744. }
  745. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  746. if (chip->rawmidi)
  747. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  748. return IRQ_HANDLED;
  749. }
  750. static struct snd_pcm_hardware snd_ymfpci_playback =
  751. {
  752. .info = (SNDRV_PCM_INFO_MMAP |
  753. SNDRV_PCM_INFO_MMAP_VALID |
  754. SNDRV_PCM_INFO_INTERLEAVED |
  755. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  756. SNDRV_PCM_INFO_PAUSE |
  757. SNDRV_PCM_INFO_RESUME),
  758. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  759. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  760. .rate_min = 8000,
  761. .rate_max = 48000,
  762. .channels_min = 1,
  763. .channels_max = 2,
  764. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  765. .period_bytes_min = 64,
  766. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  767. .periods_min = 3,
  768. .periods_max = 1024,
  769. .fifo_size = 0,
  770. };
  771. static struct snd_pcm_hardware snd_ymfpci_capture =
  772. {
  773. .info = (SNDRV_PCM_INFO_MMAP |
  774. SNDRV_PCM_INFO_MMAP_VALID |
  775. SNDRV_PCM_INFO_INTERLEAVED |
  776. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  777. SNDRV_PCM_INFO_PAUSE |
  778. SNDRV_PCM_INFO_RESUME),
  779. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  780. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  781. .rate_min = 8000,
  782. .rate_max = 48000,
  783. .channels_min = 1,
  784. .channels_max = 2,
  785. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  786. .period_bytes_min = 64,
  787. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  788. .periods_min = 3,
  789. .periods_max = 1024,
  790. .fifo_size = 0,
  791. };
  792. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  793. {
  794. kfree(runtime->private_data);
  795. }
  796. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  797. {
  798. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  799. struct snd_pcm_runtime *runtime = substream->runtime;
  800. struct snd_ymfpci_pcm *ypcm;
  801. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  802. if (ypcm == NULL)
  803. return -ENOMEM;
  804. ypcm->chip = chip;
  805. ypcm->type = PLAYBACK_VOICE;
  806. ypcm->substream = substream;
  807. runtime->hw = snd_ymfpci_playback;
  808. runtime->private_data = ypcm;
  809. runtime->private_free = snd_ymfpci_pcm_free_substream;
  810. /* FIXME? True value is 256/48 = 5.33333 ms */
  811. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  812. return 0;
  813. }
  814. /* call with spinlock held */
  815. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  816. {
  817. if (! chip->rear_opened) {
  818. if (! chip->spdif_opened) /* set AC3 */
  819. snd_ymfpci_writel(chip, YDSXGR_MODE,
  820. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  821. /* enable second codec (4CHEN) */
  822. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  823. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  824. }
  825. }
  826. /* call with spinlock held */
  827. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  828. {
  829. if (! chip->rear_opened) {
  830. if (! chip->spdif_opened)
  831. snd_ymfpci_writel(chip, YDSXGR_MODE,
  832. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  833. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  834. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  835. }
  836. }
  837. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  838. {
  839. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  840. struct snd_pcm_runtime *runtime = substream->runtime;
  841. struct snd_ymfpci_pcm *ypcm;
  842. int err;
  843. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  844. return err;
  845. ypcm = runtime->private_data;
  846. ypcm->output_front = 1;
  847. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  848. ypcm->swap_rear = 0;
  849. spin_lock_irq(&chip->reg_lock);
  850. if (ypcm->output_rear) {
  851. ymfpci_open_extension(chip);
  852. chip->rear_opened++;
  853. }
  854. spin_unlock_irq(&chip->reg_lock);
  855. return 0;
  856. }
  857. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  858. {
  859. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  860. struct snd_pcm_runtime *runtime = substream->runtime;
  861. struct snd_ymfpci_pcm *ypcm;
  862. int err;
  863. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  864. return err;
  865. ypcm = runtime->private_data;
  866. ypcm->output_front = 0;
  867. ypcm->output_rear = 1;
  868. ypcm->swap_rear = 1;
  869. spin_lock_irq(&chip->reg_lock);
  870. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  871. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  872. ymfpci_open_extension(chip);
  873. chip->spdif_pcm_bits = chip->spdif_bits;
  874. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  875. chip->spdif_opened++;
  876. spin_unlock_irq(&chip->reg_lock);
  877. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  878. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  879. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  880. return 0;
  881. }
  882. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  883. {
  884. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  885. struct snd_pcm_runtime *runtime = substream->runtime;
  886. struct snd_ymfpci_pcm *ypcm;
  887. int err;
  888. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  889. return err;
  890. ypcm = runtime->private_data;
  891. ypcm->output_front = 0;
  892. ypcm->output_rear = 1;
  893. ypcm->swap_rear = 0;
  894. spin_lock_irq(&chip->reg_lock);
  895. ymfpci_open_extension(chip);
  896. chip->rear_opened++;
  897. spin_unlock_irq(&chip->reg_lock);
  898. return 0;
  899. }
  900. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  901. u32 capture_bank_number)
  902. {
  903. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  904. struct snd_pcm_runtime *runtime = substream->runtime;
  905. struct snd_ymfpci_pcm *ypcm;
  906. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  907. if (ypcm == NULL)
  908. return -ENOMEM;
  909. ypcm->chip = chip;
  910. ypcm->type = capture_bank_number + CAPTURE_REC;
  911. ypcm->substream = substream;
  912. ypcm->capture_bank_number = capture_bank_number;
  913. chip->capture_substream[capture_bank_number] = substream;
  914. runtime->hw = snd_ymfpci_capture;
  915. /* FIXME? True value is 256/48 = 5.33333 ms */
  916. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  917. runtime->private_data = ypcm;
  918. runtime->private_free = snd_ymfpci_pcm_free_substream;
  919. snd_ymfpci_hw_start(chip);
  920. return 0;
  921. }
  922. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  923. {
  924. return snd_ymfpci_capture_open(substream, 0);
  925. }
  926. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  927. {
  928. return snd_ymfpci_capture_open(substream, 1);
  929. }
  930. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  931. {
  932. return 0;
  933. }
  934. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  935. {
  936. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  937. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  938. spin_lock_irq(&chip->reg_lock);
  939. if (ypcm->output_rear && chip->rear_opened > 0) {
  940. chip->rear_opened--;
  941. ymfpci_close_extension(chip);
  942. }
  943. spin_unlock_irq(&chip->reg_lock);
  944. return snd_ymfpci_playback_close_1(substream);
  945. }
  946. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  947. {
  948. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  949. spin_lock_irq(&chip->reg_lock);
  950. chip->spdif_opened = 0;
  951. ymfpci_close_extension(chip);
  952. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  953. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  954. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  955. spin_unlock_irq(&chip->reg_lock);
  956. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  957. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  958. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  959. return snd_ymfpci_playback_close_1(substream);
  960. }
  961. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  962. {
  963. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  964. spin_lock_irq(&chip->reg_lock);
  965. if (chip->rear_opened > 0) {
  966. chip->rear_opened--;
  967. ymfpci_close_extension(chip);
  968. }
  969. spin_unlock_irq(&chip->reg_lock);
  970. return snd_ymfpci_playback_close_1(substream);
  971. }
  972. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  973. {
  974. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  975. struct snd_pcm_runtime *runtime = substream->runtime;
  976. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  977. if (ypcm != NULL) {
  978. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  979. snd_ymfpci_hw_stop(chip);
  980. }
  981. return 0;
  982. }
  983. static struct snd_pcm_ops snd_ymfpci_playback_ops = {
  984. .open = snd_ymfpci_playback_open,
  985. .close = snd_ymfpci_playback_close,
  986. .ioctl = snd_pcm_lib_ioctl,
  987. .hw_params = snd_ymfpci_playback_hw_params,
  988. .hw_free = snd_ymfpci_playback_hw_free,
  989. .prepare = snd_ymfpci_playback_prepare,
  990. .trigger = snd_ymfpci_playback_trigger,
  991. .pointer = snd_ymfpci_playback_pointer,
  992. };
  993. static struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  994. .open = snd_ymfpci_capture_rec_open,
  995. .close = snd_ymfpci_capture_close,
  996. .ioctl = snd_pcm_lib_ioctl,
  997. .hw_params = snd_ymfpci_capture_hw_params,
  998. .hw_free = snd_ymfpci_capture_hw_free,
  999. .prepare = snd_ymfpci_capture_prepare,
  1000. .trigger = snd_ymfpci_capture_trigger,
  1001. .pointer = snd_ymfpci_capture_pointer,
  1002. };
  1003. int __devinit snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1004. {
  1005. struct snd_pcm *pcm;
  1006. int err;
  1007. if (rpcm)
  1008. *rpcm = NULL;
  1009. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  1010. return err;
  1011. pcm->private_data = chip;
  1012. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  1013. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  1014. /* global setup */
  1015. pcm->info_flags = 0;
  1016. strcpy(pcm->name, "YMFPCI");
  1017. chip->pcm = pcm;
  1018. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1019. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1020. if (rpcm)
  1021. *rpcm = pcm;
  1022. return 0;
  1023. }
  1024. static struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1025. .open = snd_ymfpci_capture_ac97_open,
  1026. .close = snd_ymfpci_capture_close,
  1027. .ioctl = snd_pcm_lib_ioctl,
  1028. .hw_params = snd_ymfpci_capture_hw_params,
  1029. .hw_free = snd_ymfpci_capture_hw_free,
  1030. .prepare = snd_ymfpci_capture_prepare,
  1031. .trigger = snd_ymfpci_capture_trigger,
  1032. .pointer = snd_ymfpci_capture_pointer,
  1033. };
  1034. int __devinit snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1035. {
  1036. struct snd_pcm *pcm;
  1037. int err;
  1038. if (rpcm)
  1039. *rpcm = NULL;
  1040. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1041. return err;
  1042. pcm->private_data = chip;
  1043. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1044. /* global setup */
  1045. pcm->info_flags = 0;
  1046. sprintf(pcm->name, "YMFPCI - %s",
  1047. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1048. chip->pcm2 = pcm;
  1049. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1050. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1051. if (rpcm)
  1052. *rpcm = pcm;
  1053. return 0;
  1054. }
  1055. static struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1056. .open = snd_ymfpci_playback_spdif_open,
  1057. .close = snd_ymfpci_playback_spdif_close,
  1058. .ioctl = snd_pcm_lib_ioctl,
  1059. .hw_params = snd_ymfpci_playback_hw_params,
  1060. .hw_free = snd_ymfpci_playback_hw_free,
  1061. .prepare = snd_ymfpci_playback_prepare,
  1062. .trigger = snd_ymfpci_playback_trigger,
  1063. .pointer = snd_ymfpci_playback_pointer,
  1064. };
  1065. int __devinit snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1066. {
  1067. struct snd_pcm *pcm;
  1068. int err;
  1069. if (rpcm)
  1070. *rpcm = NULL;
  1071. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1072. return err;
  1073. pcm->private_data = chip;
  1074. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1075. /* global setup */
  1076. pcm->info_flags = 0;
  1077. strcpy(pcm->name, "YMFPCI - IEC958");
  1078. chip->pcm_spdif = pcm;
  1079. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1080. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1081. if (rpcm)
  1082. *rpcm = pcm;
  1083. return 0;
  1084. }
  1085. static struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1086. .open = snd_ymfpci_playback_4ch_open,
  1087. .close = snd_ymfpci_playback_4ch_close,
  1088. .ioctl = snd_pcm_lib_ioctl,
  1089. .hw_params = snd_ymfpci_playback_hw_params,
  1090. .hw_free = snd_ymfpci_playback_hw_free,
  1091. .prepare = snd_ymfpci_playback_prepare,
  1092. .trigger = snd_ymfpci_playback_trigger,
  1093. .pointer = snd_ymfpci_playback_pointer,
  1094. };
  1095. int __devinit snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1096. {
  1097. struct snd_pcm *pcm;
  1098. int err;
  1099. if (rpcm)
  1100. *rpcm = NULL;
  1101. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1102. return err;
  1103. pcm->private_data = chip;
  1104. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1105. /* global setup */
  1106. pcm->info_flags = 0;
  1107. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1108. chip->pcm_4ch = pcm;
  1109. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1110. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1111. if (rpcm)
  1112. *rpcm = pcm;
  1113. return 0;
  1114. }
  1115. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1116. {
  1117. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1118. uinfo->count = 1;
  1119. return 0;
  1120. }
  1121. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1122. struct snd_ctl_elem_value *ucontrol)
  1123. {
  1124. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1125. spin_lock_irq(&chip->reg_lock);
  1126. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1127. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1128. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1129. spin_unlock_irq(&chip->reg_lock);
  1130. return 0;
  1131. }
  1132. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1133. struct snd_ctl_elem_value *ucontrol)
  1134. {
  1135. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1136. unsigned int val;
  1137. int change;
  1138. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1139. (ucontrol->value.iec958.status[1] << 8);
  1140. spin_lock_irq(&chip->reg_lock);
  1141. change = chip->spdif_bits != val;
  1142. chip->spdif_bits = val;
  1143. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1144. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1145. spin_unlock_irq(&chip->reg_lock);
  1146. return change;
  1147. }
  1148. static struct snd_kcontrol_new snd_ymfpci_spdif_default __devinitdata =
  1149. {
  1150. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1151. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1152. .info = snd_ymfpci_spdif_default_info,
  1153. .get = snd_ymfpci_spdif_default_get,
  1154. .put = snd_ymfpci_spdif_default_put
  1155. };
  1156. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1157. {
  1158. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1159. uinfo->count = 1;
  1160. return 0;
  1161. }
  1162. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1163. struct snd_ctl_elem_value *ucontrol)
  1164. {
  1165. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1166. spin_lock_irq(&chip->reg_lock);
  1167. ucontrol->value.iec958.status[0] = 0x3e;
  1168. ucontrol->value.iec958.status[1] = 0xff;
  1169. spin_unlock_irq(&chip->reg_lock);
  1170. return 0;
  1171. }
  1172. static struct snd_kcontrol_new snd_ymfpci_spdif_mask __devinitdata =
  1173. {
  1174. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1175. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1176. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1177. .info = snd_ymfpci_spdif_mask_info,
  1178. .get = snd_ymfpci_spdif_mask_get,
  1179. };
  1180. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1181. {
  1182. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1183. uinfo->count = 1;
  1184. return 0;
  1185. }
  1186. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1187. struct snd_ctl_elem_value *ucontrol)
  1188. {
  1189. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1190. spin_lock_irq(&chip->reg_lock);
  1191. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1192. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1193. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1194. spin_unlock_irq(&chip->reg_lock);
  1195. return 0;
  1196. }
  1197. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1198. struct snd_ctl_elem_value *ucontrol)
  1199. {
  1200. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1201. unsigned int val;
  1202. int change;
  1203. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1204. (ucontrol->value.iec958.status[1] << 8);
  1205. spin_lock_irq(&chip->reg_lock);
  1206. change = chip->spdif_pcm_bits != val;
  1207. chip->spdif_pcm_bits = val;
  1208. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1209. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1210. spin_unlock_irq(&chip->reg_lock);
  1211. return change;
  1212. }
  1213. static struct snd_kcontrol_new snd_ymfpci_spdif_stream __devinitdata =
  1214. {
  1215. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1216. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1217. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1218. .info = snd_ymfpci_spdif_stream_info,
  1219. .get = snd_ymfpci_spdif_stream_get,
  1220. .put = snd_ymfpci_spdif_stream_put
  1221. };
  1222. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1223. {
  1224. static char *texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1225. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1226. info->count = 1;
  1227. info->value.enumerated.items = 3;
  1228. if (info->value.enumerated.item > 2)
  1229. info->value.enumerated.item = 2;
  1230. strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
  1231. return 0;
  1232. }
  1233. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1234. {
  1235. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1236. u16 reg;
  1237. spin_lock_irq(&chip->reg_lock);
  1238. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1239. spin_unlock_irq(&chip->reg_lock);
  1240. if (!(reg & 0x100))
  1241. value->value.enumerated.item[0] = 0;
  1242. else
  1243. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1244. return 0;
  1245. }
  1246. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1247. {
  1248. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1249. u16 reg, old_reg;
  1250. spin_lock_irq(&chip->reg_lock);
  1251. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1252. if (value->value.enumerated.item[0] == 0)
  1253. reg = old_reg & ~0x100;
  1254. else
  1255. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1256. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1257. spin_unlock_irq(&chip->reg_lock);
  1258. return reg != old_reg;
  1259. }
  1260. static struct snd_kcontrol_new snd_ymfpci_drec_source __devinitdata = {
  1261. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1262. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1263. .name = "Direct Recording Source",
  1264. .info = snd_ymfpci_drec_source_info,
  1265. .get = snd_ymfpci_drec_source_get,
  1266. .put = snd_ymfpci_drec_source_put
  1267. };
  1268. /*
  1269. * Mixer controls
  1270. */
  1271. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1272. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1273. .info = snd_ymfpci_info_single, \
  1274. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1275. .private_value = ((reg) | ((shift) << 16)) }
  1276. #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
  1277. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1278. struct snd_ctl_elem_value *ucontrol)
  1279. {
  1280. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1281. int reg = kcontrol->private_value & 0xffff;
  1282. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1283. unsigned int mask = 1;
  1284. switch (reg) {
  1285. case YDSXGR_SPDIFOUTCTRL: break;
  1286. case YDSXGR_SPDIFINCTRL: break;
  1287. default: return -EINVAL;
  1288. }
  1289. ucontrol->value.integer.value[0] =
  1290. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1291. return 0;
  1292. }
  1293. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1294. struct snd_ctl_elem_value *ucontrol)
  1295. {
  1296. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1297. int reg = kcontrol->private_value & 0xffff;
  1298. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1299. unsigned int mask = 1;
  1300. int change;
  1301. unsigned int val, oval;
  1302. switch (reg) {
  1303. case YDSXGR_SPDIFOUTCTRL: break;
  1304. case YDSXGR_SPDIFINCTRL: break;
  1305. default: return -EINVAL;
  1306. }
  1307. val = (ucontrol->value.integer.value[0] & mask);
  1308. val <<= shift;
  1309. spin_lock_irq(&chip->reg_lock);
  1310. oval = snd_ymfpci_readl(chip, reg);
  1311. val = (oval & ~(mask << shift)) | val;
  1312. change = val != oval;
  1313. snd_ymfpci_writel(chip, reg, val);
  1314. spin_unlock_irq(&chip->reg_lock);
  1315. return change;
  1316. }
  1317. static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1318. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1319. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1320. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1321. .info = snd_ymfpci_info_double, \
  1322. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1323. .private_value = reg, \
  1324. .tlv = { .p = db_scale_native } }
  1325. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1326. {
  1327. unsigned int reg = kcontrol->private_value;
  1328. if (reg < 0x80 || reg >= 0xc0)
  1329. return -EINVAL;
  1330. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1331. uinfo->count = 2;
  1332. uinfo->value.integer.min = 0;
  1333. uinfo->value.integer.max = 16383;
  1334. return 0;
  1335. }
  1336. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1337. {
  1338. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1339. unsigned int reg = kcontrol->private_value;
  1340. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1341. unsigned int val;
  1342. if (reg < 0x80 || reg >= 0xc0)
  1343. return -EINVAL;
  1344. spin_lock_irq(&chip->reg_lock);
  1345. val = snd_ymfpci_readl(chip, reg);
  1346. spin_unlock_irq(&chip->reg_lock);
  1347. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1348. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1349. return 0;
  1350. }
  1351. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1352. {
  1353. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1354. unsigned int reg = kcontrol->private_value;
  1355. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1356. int change;
  1357. unsigned int val1, val2, oval;
  1358. if (reg < 0x80 || reg >= 0xc0)
  1359. return -EINVAL;
  1360. val1 = ucontrol->value.integer.value[0] & mask;
  1361. val2 = ucontrol->value.integer.value[1] & mask;
  1362. val1 <<= shift_left;
  1363. val2 <<= shift_right;
  1364. spin_lock_irq(&chip->reg_lock);
  1365. oval = snd_ymfpci_readl(chip, reg);
  1366. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1367. change = val1 != oval;
  1368. snd_ymfpci_writel(chip, reg, val1);
  1369. spin_unlock_irq(&chip->reg_lock);
  1370. return change;
  1371. }
  1372. static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
  1373. struct snd_ctl_elem_value *ucontrol)
  1374. {
  1375. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1376. unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
  1377. unsigned int reg2 = YDSXGR_BUF441OUTVOL;
  1378. int change;
  1379. unsigned int value, oval;
  1380. value = ucontrol->value.integer.value[0] & 0x3fff;
  1381. value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
  1382. spin_lock_irq(&chip->reg_lock);
  1383. oval = snd_ymfpci_readl(chip, reg);
  1384. change = value != oval;
  1385. snd_ymfpci_writel(chip, reg, value);
  1386. snd_ymfpci_writel(chip, reg2, value);
  1387. spin_unlock_irq(&chip->reg_lock);
  1388. return change;
  1389. }
  1390. /*
  1391. * 4ch duplication
  1392. */
  1393. #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
  1394. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1395. {
  1396. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1397. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1398. return 0;
  1399. }
  1400. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1401. {
  1402. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1403. int change;
  1404. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1405. if (change)
  1406. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1407. return change;
  1408. }
  1409. static struct snd_kcontrol_new snd_ymfpci_controls[] __devinitdata = {
  1410. {
  1411. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1412. .name = "Wave Playback Volume",
  1413. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1414. SNDRV_CTL_ELEM_ACCESS_TLV_READ,
  1415. .info = snd_ymfpci_info_double,
  1416. .get = snd_ymfpci_get_double,
  1417. .put = snd_ymfpci_put_nativedacvol,
  1418. .private_value = YDSXGR_NATIVEDACOUTVOL,
  1419. .tlv = { .p = db_scale_native },
  1420. },
  1421. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1422. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1423. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1424. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1425. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1426. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1427. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1428. YMFPCI_DOUBLE("FM Legacy Volume", 0, YDSXGR_LEGACYOUTVOL),
  1429. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1430. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1431. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1432. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1433. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1434. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1435. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1436. {
  1437. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1438. .name = "4ch Duplication",
  1439. .info = snd_ymfpci_info_dup4ch,
  1440. .get = snd_ymfpci_get_dup4ch,
  1441. .put = snd_ymfpci_put_dup4ch,
  1442. },
  1443. };
  1444. /*
  1445. * GPIO
  1446. */
  1447. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1448. {
  1449. u16 reg, mode;
  1450. unsigned long flags;
  1451. spin_lock_irqsave(&chip->reg_lock, flags);
  1452. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1453. reg &= ~(1 << (pin + 8));
  1454. reg |= (1 << pin);
  1455. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1456. /* set the level mode for input line */
  1457. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1458. mode &= ~(3 << (pin * 2));
  1459. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1460. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1461. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1462. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1463. return (mode >> pin) & 1;
  1464. }
  1465. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1466. {
  1467. u16 reg;
  1468. unsigned long flags;
  1469. spin_lock_irqsave(&chip->reg_lock, flags);
  1470. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1471. reg &= ~(1 << pin);
  1472. reg &= ~(1 << (pin + 8));
  1473. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1474. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1475. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1476. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1477. return 0;
  1478. }
  1479. #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
  1480. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1481. {
  1482. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1483. int pin = (int)kcontrol->private_value;
  1484. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1485. return 0;
  1486. }
  1487. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1490. int pin = (int)kcontrol->private_value;
  1491. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1492. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1493. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1494. return 1;
  1495. }
  1496. return 0;
  1497. }
  1498. static struct snd_kcontrol_new snd_ymfpci_rear_shared __devinitdata = {
  1499. .name = "Shared Rear/Line-In Switch",
  1500. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1501. .info = snd_ymfpci_gpio_sw_info,
  1502. .get = snd_ymfpci_gpio_sw_get,
  1503. .put = snd_ymfpci_gpio_sw_put,
  1504. .private_value = 2,
  1505. };
  1506. /*
  1507. * PCM voice volume
  1508. */
  1509. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1510. struct snd_ctl_elem_info *uinfo)
  1511. {
  1512. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1513. uinfo->count = 2;
  1514. uinfo->value.integer.min = 0;
  1515. uinfo->value.integer.max = 0x8000;
  1516. return 0;
  1517. }
  1518. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1519. struct snd_ctl_elem_value *ucontrol)
  1520. {
  1521. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1522. unsigned int subs = kcontrol->id.subdevice;
  1523. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1524. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1525. return 0;
  1526. }
  1527. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1528. struct snd_ctl_elem_value *ucontrol)
  1529. {
  1530. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1531. unsigned int subs = kcontrol->id.subdevice;
  1532. struct snd_pcm_substream *substream;
  1533. unsigned long flags;
  1534. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1535. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1536. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1537. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1538. if (chip->pcm_mixer[subs].left > 0x8000)
  1539. chip->pcm_mixer[subs].left = 0x8000;
  1540. if (chip->pcm_mixer[subs].right > 0x8000)
  1541. chip->pcm_mixer[subs].right = 0x8000;
  1542. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1543. spin_lock_irqsave(&chip->voice_lock, flags);
  1544. if (substream->runtime && substream->runtime->private_data) {
  1545. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1546. if (!ypcm->use_441_slot)
  1547. ypcm->update_pcm_vol = 2;
  1548. }
  1549. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1550. return 1;
  1551. }
  1552. return 0;
  1553. }
  1554. static struct snd_kcontrol_new snd_ymfpci_pcm_volume __devinitdata = {
  1555. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1556. .name = "PCM Playback Volume",
  1557. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1558. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1559. .info = snd_ymfpci_pcm_vol_info,
  1560. .get = snd_ymfpci_pcm_vol_get,
  1561. .put = snd_ymfpci_pcm_vol_put,
  1562. };
  1563. /*
  1564. * Mixer routines
  1565. */
  1566. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1567. {
  1568. struct snd_ymfpci *chip = bus->private_data;
  1569. chip->ac97_bus = NULL;
  1570. }
  1571. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1572. {
  1573. struct snd_ymfpci *chip = ac97->private_data;
  1574. chip->ac97 = NULL;
  1575. }
  1576. int __devinit snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1577. {
  1578. struct snd_ac97_template ac97;
  1579. struct snd_kcontrol *kctl;
  1580. struct snd_pcm_substream *substream;
  1581. unsigned int idx;
  1582. int err;
  1583. static struct snd_ac97_bus_ops ops = {
  1584. .write = snd_ymfpci_codec_write,
  1585. .read = snd_ymfpci_codec_read,
  1586. };
  1587. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1588. return err;
  1589. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1590. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1591. memset(&ac97, 0, sizeof(ac97));
  1592. ac97.private_data = chip;
  1593. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1594. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1595. return err;
  1596. /* to be sure */
  1597. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1598. AC97_EA_VRA|AC97_EA_VRM, 0);
  1599. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1600. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1601. return err;
  1602. }
  1603. /* add S/PDIF control */
  1604. snd_assert(chip->pcm_spdif != NULL, return -EIO);
  1605. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1606. return err;
  1607. kctl->id.device = chip->pcm_spdif->device;
  1608. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1609. return err;
  1610. kctl->id.device = chip->pcm_spdif->device;
  1611. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1612. return err;
  1613. kctl->id.device = chip->pcm_spdif->device;
  1614. chip->spdif_pcm_ctl = kctl;
  1615. /* direct recording source */
  1616. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1617. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1618. return err;
  1619. /*
  1620. * shared rear/line-in
  1621. */
  1622. if (rear_switch) {
  1623. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1624. return err;
  1625. }
  1626. /* per-voice volume */
  1627. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1628. for (idx = 0; idx < 32; ++idx) {
  1629. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1630. if (!kctl)
  1631. return -ENOMEM;
  1632. kctl->id.device = chip->pcm->device;
  1633. kctl->id.subdevice = idx;
  1634. kctl->private_value = (unsigned long)substream;
  1635. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1636. return err;
  1637. chip->pcm_mixer[idx].left = 0x8000;
  1638. chip->pcm_mixer[idx].right = 0x8000;
  1639. chip->pcm_mixer[idx].ctl = kctl;
  1640. substream = substream->next;
  1641. }
  1642. return 0;
  1643. }
  1644. /*
  1645. * timer
  1646. */
  1647. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1648. {
  1649. struct snd_ymfpci *chip;
  1650. unsigned long flags;
  1651. unsigned int count;
  1652. chip = snd_timer_chip(timer);
  1653. count = (timer->sticks << 1) - 1;
  1654. spin_lock_irqsave(&chip->reg_lock, flags);
  1655. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1656. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1657. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1658. return 0;
  1659. }
  1660. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1661. {
  1662. struct snd_ymfpci *chip;
  1663. unsigned long flags;
  1664. chip = snd_timer_chip(timer);
  1665. spin_lock_irqsave(&chip->reg_lock, flags);
  1666. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1667. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1668. return 0;
  1669. }
  1670. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1671. unsigned long *num, unsigned long *den)
  1672. {
  1673. *num = 1;
  1674. *den = 48000;
  1675. return 0;
  1676. }
  1677. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1678. .flags = SNDRV_TIMER_HW_AUTO,
  1679. .resolution = 20833, /* 1/fs = 20.8333...us */
  1680. .ticks = 0x8000,
  1681. .start = snd_ymfpci_timer_start,
  1682. .stop = snd_ymfpci_timer_stop,
  1683. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1684. };
  1685. int __devinit snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1686. {
  1687. struct snd_timer *timer = NULL;
  1688. struct snd_timer_id tid;
  1689. int err;
  1690. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1691. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1692. tid.card = chip->card->number;
  1693. tid.device = device;
  1694. tid.subdevice = 0;
  1695. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1696. strcpy(timer->name, "YMFPCI timer");
  1697. timer->private_data = chip;
  1698. timer->hw = snd_ymfpci_timer_hw;
  1699. }
  1700. chip->timer = timer;
  1701. return err;
  1702. }
  1703. /*
  1704. * proc interface
  1705. */
  1706. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1707. struct snd_info_buffer *buffer)
  1708. {
  1709. struct snd_ymfpci *chip = entry->private_data;
  1710. int i;
  1711. snd_iprintf(buffer, "YMFPCI\n\n");
  1712. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1713. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1714. }
  1715. static int __devinit snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1716. {
  1717. struct snd_info_entry *entry;
  1718. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1719. snd_info_set_text_ops(entry, chip, snd_ymfpci_proc_read);
  1720. return 0;
  1721. }
  1722. /*
  1723. * initialization routines
  1724. */
  1725. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1726. {
  1727. u8 cmd;
  1728. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1729. #if 0 // force to reset
  1730. if (cmd & 0x03) {
  1731. #endif
  1732. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1733. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1734. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1735. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1736. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1737. #if 0
  1738. }
  1739. #endif
  1740. }
  1741. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1742. {
  1743. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1744. }
  1745. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1746. {
  1747. u32 val;
  1748. int timeout = 1000;
  1749. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1750. if (val)
  1751. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1752. while (timeout-- > 0) {
  1753. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1754. if ((val & 0x00000002) == 0)
  1755. break;
  1756. }
  1757. }
  1758. #ifdef CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL
  1759. #include "ymfpci_image.h"
  1760. static struct firmware snd_ymfpci_dsp_microcode = {
  1761. .size = YDSXG_DSPLENGTH,
  1762. .data = (u8 *)DspInst,
  1763. };
  1764. static struct firmware snd_ymfpci_controller_microcode = {
  1765. .size = YDSXG_CTRLLENGTH,
  1766. .data = (u8 *)CntrlInst,
  1767. };
  1768. static struct firmware snd_ymfpci_controller_1e_microcode = {
  1769. .size = YDSXG_CTRLLENGTH,
  1770. .data = (u8 *)CntrlInst1E,
  1771. };
  1772. #endif
  1773. #ifdef CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL
  1774. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1775. {
  1776. chip->dsp_microcode = &snd_ymfpci_dsp_microcode;
  1777. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1778. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1779. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1780. chip->device_id == PCI_DEVICE_ID_YAMAHA_754)
  1781. chip->controller_microcode =
  1782. &snd_ymfpci_controller_1e_microcode;
  1783. else
  1784. chip->controller_microcode =
  1785. &snd_ymfpci_controller_microcode;
  1786. return 0;
  1787. }
  1788. #else /* use fw_loader */
  1789. #ifdef __LITTLE_ENDIAN
  1790. static inline void snd_ymfpci_convert_from_le(const struct firmware *fw) { }
  1791. #else
  1792. static void snd_ymfpci_convert_from_le(const struct firmware *fw)
  1793. {
  1794. int i;
  1795. u32 *data = (u32 *)fw->data;
  1796. for (i = 0; i < fw->size / 4; ++i)
  1797. le32_to_cpus(&data[i]);
  1798. }
  1799. #endif
  1800. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1801. {
  1802. int err, is_1e;
  1803. const char *name;
  1804. err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
  1805. &chip->pci->dev);
  1806. if (err >= 0) {
  1807. if (chip->dsp_microcode->size == YDSXG_DSPLENGTH)
  1808. snd_ymfpci_convert_from_le(chip->dsp_microcode);
  1809. else {
  1810. snd_printk(KERN_ERR "DSP microcode has wrong size\n");
  1811. err = -EINVAL;
  1812. }
  1813. }
  1814. if (err < 0)
  1815. return err;
  1816. is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1817. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1818. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1819. chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
  1820. name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
  1821. err = request_firmware(&chip->controller_microcode, name,
  1822. &chip->pci->dev);
  1823. if (err >= 0) {
  1824. if (chip->controller_microcode->size == YDSXG_CTRLLENGTH)
  1825. snd_ymfpci_convert_from_le(chip->controller_microcode);
  1826. else {
  1827. snd_printk(KERN_ERR "controller microcode"
  1828. " has wrong size\n");
  1829. err = -EINVAL;
  1830. }
  1831. }
  1832. if (err < 0)
  1833. return err;
  1834. return 0;
  1835. }
  1836. MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
  1837. MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
  1838. MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
  1839. #endif
  1840. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1841. {
  1842. int i;
  1843. u16 ctrl;
  1844. u32 *inst;
  1845. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1846. snd_ymfpci_disable_dsp(chip);
  1847. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1848. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1849. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1850. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1851. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1852. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1853. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1854. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1855. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1856. /* setup DSP instruction code */
  1857. inst = (u32 *)chip->dsp_microcode->data;
  1858. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1859. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2), inst[i]);
  1860. /* setup control instruction code */
  1861. inst = (u32 *)chip->controller_microcode->data;
  1862. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1863. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2), inst[i]);
  1864. snd_ymfpci_enable_dsp(chip);
  1865. }
  1866. static int __devinit snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1867. {
  1868. long size, playback_ctrl_size;
  1869. int voice, bank, reg;
  1870. u8 *ptr;
  1871. dma_addr_t ptr_addr;
  1872. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1873. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1874. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1875. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1876. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1877. size = ALIGN(playback_ctrl_size, 0x100) +
  1878. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1879. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1880. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1881. chip->work_size;
  1882. /* work_ptr must be aligned to 256 bytes, but it's already
  1883. covered with the kernel page allocation mechanism */
  1884. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1885. size, &chip->work_ptr) < 0)
  1886. return -ENOMEM;
  1887. ptr = chip->work_ptr.area;
  1888. ptr_addr = chip->work_ptr.addr;
  1889. memset(ptr, 0, size); /* for sure */
  1890. chip->bank_base_playback = ptr;
  1891. chip->bank_base_playback_addr = ptr_addr;
  1892. chip->ctrl_playback = (u32 *)ptr;
  1893. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1894. ptr += ALIGN(playback_ctrl_size, 0x100);
  1895. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1896. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1897. chip->voices[voice].number = voice;
  1898. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1899. chip->voices[voice].bank_addr = ptr_addr;
  1900. for (bank = 0; bank < 2; bank++) {
  1901. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1902. ptr += chip->bank_size_playback;
  1903. ptr_addr += chip->bank_size_playback;
  1904. }
  1905. }
  1906. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1907. ptr_addr = ALIGN(ptr_addr, 0x100);
  1908. chip->bank_base_capture = ptr;
  1909. chip->bank_base_capture_addr = ptr_addr;
  1910. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1911. for (bank = 0; bank < 2; bank++) {
  1912. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1913. ptr += chip->bank_size_capture;
  1914. ptr_addr += chip->bank_size_capture;
  1915. }
  1916. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1917. ptr_addr = ALIGN(ptr_addr, 0x100);
  1918. chip->bank_base_effect = ptr;
  1919. chip->bank_base_effect_addr = ptr_addr;
  1920. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1921. for (bank = 0; bank < 2; bank++) {
  1922. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1923. ptr += chip->bank_size_effect;
  1924. ptr_addr += chip->bank_size_effect;
  1925. }
  1926. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1927. ptr_addr = ALIGN(ptr_addr, 0x100);
  1928. chip->work_base = ptr;
  1929. chip->work_base_addr = ptr_addr;
  1930. snd_assert(ptr + chip->work_size == chip->work_ptr.area + chip->work_ptr.bytes, );
  1931. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1932. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1933. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1934. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1935. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1936. /* S/PDIF output initialization */
  1937. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1938. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1939. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1940. /* S/PDIF input initialization */
  1941. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1942. /* digital mixer setup */
  1943. for (reg = 0x80; reg < 0xc0; reg += 4)
  1944. snd_ymfpci_writel(chip, reg, 0);
  1945. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1946. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
  1947. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1948. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1949. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1950. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1951. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1952. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1953. return 0;
  1954. }
  1955. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1956. {
  1957. u16 ctrl;
  1958. snd_assert(chip != NULL, return -EINVAL);
  1959. if (chip->res_reg_area) { /* don't touch busy hardware */
  1960. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1961. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1962. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1963. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1964. snd_ymfpci_disable_dsp(chip);
  1965. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1966. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1967. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1968. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1969. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1970. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1971. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1972. }
  1973. snd_ymfpci_ac3_done(chip);
  1974. /* Set PCI device to D3 state */
  1975. #if 0
  1976. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1977. * the chip again unless reboot. ACPI bug?
  1978. */
  1979. pci_set_power_state(chip->pci, 3);
  1980. #endif
  1981. #ifdef CONFIG_PM
  1982. vfree(chip->saved_regs);
  1983. #endif
  1984. if (chip->irq >= 0)
  1985. free_irq(chip->irq, chip);
  1986. release_and_free_resource(chip->mpu_res);
  1987. release_and_free_resource(chip->fm_res);
  1988. snd_ymfpci_free_gameport(chip);
  1989. if (chip->reg_area_virt)
  1990. iounmap(chip->reg_area_virt);
  1991. if (chip->work_ptr.area)
  1992. snd_dma_free_pages(&chip->work_ptr);
  1993. release_and_free_resource(chip->res_reg_area);
  1994. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1995. pci_disable_device(chip->pci);
  1996. #ifndef CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL
  1997. release_firmware(chip->dsp_microcode);
  1998. release_firmware(chip->controller_microcode);
  1999. #endif
  2000. kfree(chip);
  2001. return 0;
  2002. }
  2003. static int snd_ymfpci_dev_free(struct snd_device *device)
  2004. {
  2005. struct snd_ymfpci *chip = device->device_data;
  2006. return snd_ymfpci_free(chip);
  2007. }
  2008. #ifdef CONFIG_PM
  2009. static int saved_regs_index[] = {
  2010. /* spdif */
  2011. YDSXGR_SPDIFOUTCTRL,
  2012. YDSXGR_SPDIFOUTSTATUS,
  2013. YDSXGR_SPDIFINCTRL,
  2014. /* volumes */
  2015. YDSXGR_PRIADCLOOPVOL,
  2016. YDSXGR_NATIVEDACINVOL,
  2017. YDSXGR_NATIVEDACOUTVOL,
  2018. YDSXGR_BUF441OUTVOL,
  2019. YDSXGR_NATIVEADCINVOL,
  2020. YDSXGR_SPDIFLOOPVOL,
  2021. YDSXGR_SPDIFOUTVOL,
  2022. YDSXGR_ZVOUTVOL,
  2023. YDSXGR_LEGACYOUTVOL,
  2024. /* address bases */
  2025. YDSXGR_PLAYCTRLBASE,
  2026. YDSXGR_RECCTRLBASE,
  2027. YDSXGR_EFFCTRLBASE,
  2028. YDSXGR_WORKBASE,
  2029. /* capture set up */
  2030. YDSXGR_MAPOFREC,
  2031. YDSXGR_RECFORMAT,
  2032. YDSXGR_RECSLOTSR,
  2033. YDSXGR_ADCFORMAT,
  2034. YDSXGR_ADCSLOTSR,
  2035. };
  2036. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  2037. int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state)
  2038. {
  2039. struct snd_card *card = pci_get_drvdata(pci);
  2040. struct snd_ymfpci *chip = card->private_data;
  2041. unsigned int i;
  2042. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2043. snd_pcm_suspend_all(chip->pcm);
  2044. snd_pcm_suspend_all(chip->pcm2);
  2045. snd_pcm_suspend_all(chip->pcm_spdif);
  2046. snd_pcm_suspend_all(chip->pcm_4ch);
  2047. snd_ac97_suspend(chip->ac97);
  2048. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2049. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  2050. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  2051. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  2052. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  2053. snd_ymfpci_disable_dsp(chip);
  2054. pci_disable_device(pci);
  2055. pci_save_state(pci);
  2056. pci_set_power_state(pci, pci_choose_state(pci, state));
  2057. return 0;
  2058. }
  2059. int snd_ymfpci_resume(struct pci_dev *pci)
  2060. {
  2061. struct snd_card *card = pci_get_drvdata(pci);
  2062. struct snd_ymfpci *chip = card->private_data;
  2063. unsigned int i;
  2064. pci_set_power_state(pci, PCI_D0);
  2065. pci_restore_state(pci);
  2066. if (pci_enable_device(pci) < 0) {
  2067. printk(KERN_ERR "ymfpci: pci_enable_device failed, "
  2068. "disabling device\n");
  2069. snd_card_disconnect(card);
  2070. return -EIO;
  2071. }
  2072. pci_set_master(pci);
  2073. snd_ymfpci_aclink_reset(pci);
  2074. snd_ymfpci_codec_ready(chip, 0);
  2075. snd_ymfpci_download_image(chip);
  2076. udelay(100);
  2077. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2078. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  2079. snd_ac97_resume(chip->ac97);
  2080. /* start hw again */
  2081. if (chip->start_count > 0) {
  2082. spin_lock_irq(&chip->reg_lock);
  2083. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  2084. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  2085. spin_unlock_irq(&chip->reg_lock);
  2086. }
  2087. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2088. return 0;
  2089. }
  2090. #endif /* CONFIG_PM */
  2091. int __devinit snd_ymfpci_create(struct snd_card *card,
  2092. struct pci_dev * pci,
  2093. unsigned short old_legacy_ctrl,
  2094. struct snd_ymfpci ** rchip)
  2095. {
  2096. struct snd_ymfpci *chip;
  2097. int err;
  2098. static struct snd_device_ops ops = {
  2099. .dev_free = snd_ymfpci_dev_free,
  2100. };
  2101. *rchip = NULL;
  2102. /* enable PCI device */
  2103. if ((err = pci_enable_device(pci)) < 0)
  2104. return err;
  2105. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2106. if (chip == NULL) {
  2107. pci_disable_device(pci);
  2108. return -ENOMEM;
  2109. }
  2110. chip->old_legacy_ctrl = old_legacy_ctrl;
  2111. spin_lock_init(&chip->reg_lock);
  2112. spin_lock_init(&chip->voice_lock);
  2113. init_waitqueue_head(&chip->interrupt_sleep);
  2114. atomic_set(&chip->interrupt_sleep_count, 0);
  2115. chip->card = card;
  2116. chip->pci = pci;
  2117. chip->irq = -1;
  2118. chip->device_id = pci->device;
  2119. chip->rev = pci->revision;
  2120. chip->reg_area_phys = pci_resource_start(pci, 0);
  2121. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2122. pci_set_master(pci);
  2123. chip->src441_used = -1;
  2124. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2125. snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2126. snd_ymfpci_free(chip);
  2127. return -EBUSY;
  2128. }
  2129. if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2130. "YMFPCI", chip)) {
  2131. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2132. snd_ymfpci_free(chip);
  2133. return -EBUSY;
  2134. }
  2135. chip->irq = pci->irq;
  2136. snd_ymfpci_aclink_reset(pci);
  2137. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2138. snd_ymfpci_free(chip);
  2139. return -EIO;
  2140. }
  2141. err = snd_ymfpci_request_firmware(chip);
  2142. if (err < 0) {
  2143. snd_printk(KERN_ERR "firmware request failed: %d\n", err);
  2144. snd_ymfpci_free(chip);
  2145. return err;
  2146. }
  2147. snd_ymfpci_download_image(chip);
  2148. udelay(100); /* seems we need a delay after downloading image.. */
  2149. if (snd_ymfpci_memalloc(chip) < 0) {
  2150. snd_ymfpci_free(chip);
  2151. return -EIO;
  2152. }
  2153. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2154. snd_ymfpci_free(chip);
  2155. return err;
  2156. }
  2157. #ifdef CONFIG_PM
  2158. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  2159. if (chip->saved_regs == NULL) {
  2160. snd_ymfpci_free(chip);
  2161. return -ENOMEM;
  2162. }
  2163. #endif
  2164. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2165. snd_ymfpci_free(chip);
  2166. return err;
  2167. }
  2168. snd_ymfpci_proc_init(card, chip);
  2169. snd_card_set_dev(card, &pci->dev);
  2170. *rchip = chip;
  2171. return 0;
  2172. }