islpci_dev.c 27 KB

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  1. /*
  2. * Copyright (C) 2002 Intersil Americas Inc.
  3. * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
  4. * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/module.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/ethtool.h>
  23. #include <linux/pci.h>
  24. #include <linux/sched.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/if_arp.h>
  28. #include <asm/io.h>
  29. #include "prismcompat.h"
  30. #include "isl_38xx.h"
  31. #include "isl_ioctl.h"
  32. #include "islpci_dev.h"
  33. #include "islpci_mgt.h"
  34. #include "islpci_eth.h"
  35. #include "oid_mgt.h"
  36. #define ISL3877_IMAGE_FILE "isl3877"
  37. #define ISL3886_IMAGE_FILE "isl3886"
  38. #define ISL3890_IMAGE_FILE "isl3890"
  39. static int prism54_bring_down(islpci_private *);
  40. static int islpci_alloc_memory(islpci_private *);
  41. /* Temporary dummy MAC address to use until firmware is loaded.
  42. * The idea there is that some tools (such as nameif) may query
  43. * the MAC address before the netdev is 'open'. By using a valid
  44. * OUI prefix, they can process the netdev properly.
  45. * Of course, this is not the final/real MAC address. It doesn't
  46. * matter, as you are suppose to be able to change it anytime via
  47. * ndev->set_mac_address. Jean II */
  48. static const unsigned char dummy_mac[6] = { 0x00, 0x30, 0xB4, 0x00, 0x00, 0x00 };
  49. static int
  50. isl_upload_firmware(islpci_private *priv)
  51. {
  52. u32 reg, rc;
  53. void __iomem *device_base = priv->device_base;
  54. /* clear the RAMBoot and the Reset bit */
  55. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  56. reg &= ~ISL38XX_CTRL_STAT_RESET;
  57. reg &= ~ISL38XX_CTRL_STAT_RAMBOOT;
  58. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  59. wmb();
  60. udelay(ISL38XX_WRITEIO_DELAY);
  61. /* set the Reset bit without reading the register ! */
  62. reg |= ISL38XX_CTRL_STAT_RESET;
  63. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  64. wmb();
  65. udelay(ISL38XX_WRITEIO_DELAY);
  66. /* clear the Reset bit */
  67. reg &= ~ISL38XX_CTRL_STAT_RESET;
  68. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  69. wmb();
  70. /* wait a while for the device to reboot */
  71. mdelay(50);
  72. {
  73. const struct firmware *fw_entry = NULL;
  74. long fw_len;
  75. const u32 *fw_ptr;
  76. rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV);
  77. if (rc) {
  78. printk(KERN_ERR
  79. "%s: request_firmware() failed for '%s'\n",
  80. "prism54", priv->firmware);
  81. return rc;
  82. }
  83. /* prepare the Direct Memory Base register */
  84. reg = ISL38XX_DEV_FIRMWARE_ADDRES;
  85. fw_ptr = (u32 *) fw_entry->data;
  86. fw_len = fw_entry->size;
  87. if (fw_len % 4) {
  88. printk(KERN_ERR
  89. "%s: firmware '%s' size is not multiple of 32bit, aborting!\n",
  90. "prism54", priv->firmware);
  91. release_firmware(fw_entry);
  92. return -EILSEQ; /* Illegal byte sequence */;
  93. }
  94. while (fw_len > 0) {
  95. long _fw_len =
  96. (fw_len >
  97. ISL38XX_MEMORY_WINDOW_SIZE) ?
  98. ISL38XX_MEMORY_WINDOW_SIZE : fw_len;
  99. u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN;
  100. /* set the card's base address for writing the data */
  101. isl38xx_w32_flush(device_base, reg,
  102. ISL38XX_DIR_MEM_BASE_REG);
  103. wmb(); /* be paranoid */
  104. /* increment the write address for next iteration */
  105. reg += _fw_len;
  106. fw_len -= _fw_len;
  107. /* write the data to the Direct Memory Window 32bit-wise */
  108. /* memcpy_toio() doesn't guarantee 32bit writes :-| */
  109. while (_fw_len > 0) {
  110. /* use non-swapping writel() */
  111. __raw_writel(*fw_ptr, dev_fw_ptr);
  112. fw_ptr++, dev_fw_ptr++;
  113. _fw_len -= 4;
  114. }
  115. /* flush PCI posting */
  116. (void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH);
  117. wmb(); /* be paranoid again */
  118. BUG_ON(_fw_len != 0);
  119. }
  120. BUG_ON(fw_len != 0);
  121. /* Firmware version is at offset 40 (also for "newmac") */
  122. printk(KERN_DEBUG "%s: firmware version: %.8s\n",
  123. priv->ndev->name, fw_entry->data + 40);
  124. release_firmware(fw_entry);
  125. }
  126. /* now reset the device
  127. * clear the Reset & ClkRun bit, set the RAMBoot bit */
  128. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  129. reg &= ~ISL38XX_CTRL_STAT_CLKRUN;
  130. reg &= ~ISL38XX_CTRL_STAT_RESET;
  131. reg |= ISL38XX_CTRL_STAT_RAMBOOT;
  132. isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG);
  133. wmb();
  134. udelay(ISL38XX_WRITEIO_DELAY);
  135. /* set the reset bit latches the host override and RAMBoot bits
  136. * into the device for operation when the reset bit is reset */
  137. reg |= ISL38XX_CTRL_STAT_RESET;
  138. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  139. /* don't do flush PCI posting here! */
  140. wmb();
  141. udelay(ISL38XX_WRITEIO_DELAY);
  142. /* clear the reset bit should start the whole circus */
  143. reg &= ~ISL38XX_CTRL_STAT_RESET;
  144. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  145. /* don't do flush PCI posting here! */
  146. wmb();
  147. udelay(ISL38XX_WRITEIO_DELAY);
  148. return 0;
  149. }
  150. /******************************************************************************
  151. Device Interrupt Handler
  152. ******************************************************************************/
  153. irqreturn_t
  154. islpci_interrupt(int irq, void *config)
  155. {
  156. u32 reg;
  157. islpci_private *priv = config;
  158. struct net_device *ndev = priv->ndev;
  159. void __iomem *device = priv->device_base;
  160. int powerstate = ISL38XX_PSM_POWERSAVE_STATE;
  161. /* lock the interrupt handler */
  162. spin_lock(&priv->slock);
  163. /* received an interrupt request on a shared IRQ line
  164. * first check whether the device is in sleep mode */
  165. reg = readl(device + ISL38XX_CTRL_STAT_REG);
  166. if (reg & ISL38XX_CTRL_STAT_SLEEPMODE)
  167. /* device is in sleep mode, IRQ was generated by someone else */
  168. {
  169. #if VERBOSE > SHOW_ERROR_MESSAGES
  170. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  171. #endif
  172. spin_unlock(&priv->slock);
  173. return IRQ_NONE;
  174. }
  175. /* check whether there is any source of interrupt on the device */
  176. reg = readl(device + ISL38XX_INT_IDENT_REG);
  177. /* also check the contents of the Interrupt Enable Register, because this
  178. * will filter out interrupt sources from other devices on the same irq ! */
  179. reg &= readl(device + ISL38XX_INT_EN_REG);
  180. reg &= ISL38XX_INT_SOURCES;
  181. if (reg != 0) {
  182. if (islpci_get_state(priv) != PRV_STATE_SLEEP)
  183. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  184. /* reset the request bits in the Identification register */
  185. isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG);
  186. #if VERBOSE > SHOW_ERROR_MESSAGES
  187. DEBUG(SHOW_FUNCTION_CALLS,
  188. "IRQ: Identification register 0x%p 0x%x \n", device, reg);
  189. #endif
  190. /* check for each bit in the register separately */
  191. if (reg & ISL38XX_INT_IDENT_UPDATE) {
  192. #if VERBOSE > SHOW_ERROR_MESSAGES
  193. /* Queue has been updated */
  194. DEBUG(SHOW_TRACING, "IRQ: Update flag \n");
  195. DEBUG(SHOW_QUEUE_INDEXES,
  196. "CB drv Qs: [%i][%i][%i][%i][%i][%i]\n",
  197. le32_to_cpu(priv->control_block->
  198. driver_curr_frag[0]),
  199. le32_to_cpu(priv->control_block->
  200. driver_curr_frag[1]),
  201. le32_to_cpu(priv->control_block->
  202. driver_curr_frag[2]),
  203. le32_to_cpu(priv->control_block->
  204. driver_curr_frag[3]),
  205. le32_to_cpu(priv->control_block->
  206. driver_curr_frag[4]),
  207. le32_to_cpu(priv->control_block->
  208. driver_curr_frag[5])
  209. );
  210. DEBUG(SHOW_QUEUE_INDEXES,
  211. "CB dev Qs: [%i][%i][%i][%i][%i][%i]\n",
  212. le32_to_cpu(priv->control_block->
  213. device_curr_frag[0]),
  214. le32_to_cpu(priv->control_block->
  215. device_curr_frag[1]),
  216. le32_to_cpu(priv->control_block->
  217. device_curr_frag[2]),
  218. le32_to_cpu(priv->control_block->
  219. device_curr_frag[3]),
  220. le32_to_cpu(priv->control_block->
  221. device_curr_frag[4]),
  222. le32_to_cpu(priv->control_block->
  223. device_curr_frag[5])
  224. );
  225. #endif
  226. /* cleanup the data low transmit queue */
  227. islpci_eth_cleanup_transmit(priv, priv->control_block);
  228. /* device is in active state, update the
  229. * powerstate flag if necessary */
  230. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  231. /* check all three queues in priority order
  232. * call the PIMFOR receive function until the
  233. * queue is empty */
  234. if (isl38xx_in_queue(priv->control_block,
  235. ISL38XX_CB_RX_MGMTQ) != 0) {
  236. #if VERBOSE > SHOW_ERROR_MESSAGES
  237. DEBUG(SHOW_TRACING,
  238. "Received frame in Management Queue\n");
  239. #endif
  240. islpci_mgt_receive(ndev);
  241. islpci_mgt_cleanup_transmit(ndev);
  242. /* Refill slots in receive queue */
  243. islpci_mgmt_rx_fill(ndev);
  244. /* no need to trigger the device, next
  245. islpci_mgt_transaction does it */
  246. }
  247. while (isl38xx_in_queue(priv->control_block,
  248. ISL38XX_CB_RX_DATA_LQ) != 0) {
  249. #if VERBOSE > SHOW_ERROR_MESSAGES
  250. DEBUG(SHOW_TRACING,
  251. "Received frame in Data Low Queue \n");
  252. #endif
  253. islpci_eth_receive(priv);
  254. }
  255. /* check whether the data transmit queues were full */
  256. if (priv->data_low_tx_full) {
  257. /* check whether the transmit is not full anymore */
  258. if (ISL38XX_CB_TX_QSIZE -
  259. isl38xx_in_queue(priv->control_block,
  260. ISL38XX_CB_TX_DATA_LQ) >=
  261. ISL38XX_MIN_QTHRESHOLD) {
  262. /* nope, the driver is ready for more network frames */
  263. netif_wake_queue(priv->ndev);
  264. /* reset the full flag */
  265. priv->data_low_tx_full = 0;
  266. }
  267. }
  268. }
  269. if (reg & ISL38XX_INT_IDENT_INIT) {
  270. /* Device has been initialized */
  271. #if VERBOSE > SHOW_ERROR_MESSAGES
  272. DEBUG(SHOW_TRACING,
  273. "IRQ: Init flag, device initialized \n");
  274. #endif
  275. wake_up(&priv->reset_done);
  276. }
  277. if (reg & ISL38XX_INT_IDENT_SLEEP) {
  278. /* Device intends to move to powersave state */
  279. #if VERBOSE > SHOW_ERROR_MESSAGES
  280. DEBUG(SHOW_TRACING, "IRQ: Sleep flag \n");
  281. #endif
  282. isl38xx_handle_sleep_request(priv->control_block,
  283. &powerstate,
  284. priv->device_base);
  285. }
  286. if (reg & ISL38XX_INT_IDENT_WAKEUP) {
  287. /* Device has been woken up to active state */
  288. #if VERBOSE > SHOW_ERROR_MESSAGES
  289. DEBUG(SHOW_TRACING, "IRQ: Wakeup flag \n");
  290. #endif
  291. isl38xx_handle_wakeup(priv->control_block,
  292. &powerstate, priv->device_base);
  293. }
  294. } else {
  295. #if VERBOSE > SHOW_ERROR_MESSAGES
  296. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  297. #endif
  298. spin_unlock(&priv->slock);
  299. return IRQ_NONE;
  300. }
  301. /* sleep -> ready */
  302. if (islpci_get_state(priv) == PRV_STATE_SLEEP
  303. && powerstate == ISL38XX_PSM_ACTIVE_STATE)
  304. islpci_set_state(priv, PRV_STATE_READY);
  305. /* !sleep -> sleep */
  306. if (islpci_get_state(priv) != PRV_STATE_SLEEP
  307. && powerstate == ISL38XX_PSM_POWERSAVE_STATE)
  308. islpci_set_state(priv, PRV_STATE_SLEEP);
  309. /* unlock the interrupt handler */
  310. spin_unlock(&priv->slock);
  311. return IRQ_HANDLED;
  312. }
  313. /******************************************************************************
  314. Network Interface Control & Statistical functions
  315. ******************************************************************************/
  316. static int
  317. islpci_open(struct net_device *ndev)
  318. {
  319. u32 rc;
  320. islpci_private *priv = netdev_priv(ndev);
  321. /* reset data structures, upload firmware and reset device */
  322. rc = islpci_reset(priv,1);
  323. if (rc) {
  324. prism54_bring_down(priv);
  325. return rc; /* Returns informative message */
  326. }
  327. netif_start_queue(ndev);
  328. /* Turn off carrier if in STA or Ad-hoc mode. It will be turned on
  329. * once the firmware receives a trap of being associated
  330. * (GEN_OID_LINKSTATE). In other modes (AP or WDS or monitor) we
  331. * should just leave the carrier on as its expected the firmware
  332. * won't send us a trigger. */
  333. if (priv->iw_mode == IW_MODE_INFRA || priv->iw_mode == IW_MODE_ADHOC)
  334. netif_carrier_off(ndev);
  335. else
  336. netif_carrier_on(ndev);
  337. return 0;
  338. }
  339. static int
  340. islpci_close(struct net_device *ndev)
  341. {
  342. islpci_private *priv = netdev_priv(ndev);
  343. printk(KERN_DEBUG "%s: islpci_close ()\n", ndev->name);
  344. netif_stop_queue(ndev);
  345. return prism54_bring_down(priv);
  346. }
  347. static int
  348. prism54_bring_down(islpci_private *priv)
  349. {
  350. void __iomem *device_base = priv->device_base;
  351. u32 reg;
  352. /* we are going to shutdown the device */
  353. islpci_set_state(priv, PRV_STATE_PREBOOT);
  354. /* disable all device interrupts in case they weren't */
  355. isl38xx_disable_interrupts(priv->device_base);
  356. /* For safety reasons, we may want to ensure that no DMA transfer is
  357. * currently in progress by emptying the TX and RX queues. */
  358. /* wait until interrupts have finished executing on other CPUs */
  359. synchronize_irq(priv->pdev->irq);
  360. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  361. reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT);
  362. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  363. wmb();
  364. udelay(ISL38XX_WRITEIO_DELAY);
  365. reg |= ISL38XX_CTRL_STAT_RESET;
  366. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  367. wmb();
  368. udelay(ISL38XX_WRITEIO_DELAY);
  369. /* clear the Reset bit */
  370. reg &= ~ISL38XX_CTRL_STAT_RESET;
  371. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  372. wmb();
  373. /* wait a while for the device to reset */
  374. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  375. return 0;
  376. }
  377. static int
  378. islpci_upload_fw(islpci_private *priv)
  379. {
  380. islpci_state_t old_state;
  381. u32 rc;
  382. old_state = islpci_set_state(priv, PRV_STATE_BOOT);
  383. printk(KERN_DEBUG "%s: uploading firmware...\n", priv->ndev->name);
  384. rc = isl_upload_firmware(priv);
  385. if (rc) {
  386. /* error uploading the firmware */
  387. printk(KERN_ERR "%s: could not upload firmware ('%s')\n",
  388. priv->ndev->name, priv->firmware);
  389. islpci_set_state(priv, old_state);
  390. return rc;
  391. }
  392. printk(KERN_DEBUG "%s: firmware upload complete\n",
  393. priv->ndev->name);
  394. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  395. return 0;
  396. }
  397. static int
  398. islpci_reset_if(islpci_private *priv)
  399. {
  400. long remaining;
  401. int result = -ETIME;
  402. int count;
  403. DEFINE_WAIT(wait);
  404. prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE);
  405. /* now the last step is to reset the interface */
  406. isl38xx_interface_reset(priv->device_base, priv->device_host_address);
  407. islpci_set_state(priv, PRV_STATE_PREINIT);
  408. for(count = 0; count < 2 && result; count++) {
  409. /* The software reset acknowledge needs about 220 msec here.
  410. * Be conservative and wait for up to one second. */
  411. remaining = schedule_timeout_uninterruptible(HZ);
  412. if(remaining > 0) {
  413. result = 0;
  414. break;
  415. }
  416. /* If we're here it's because our IRQ hasn't yet gone through.
  417. * Retry a bit more...
  418. */
  419. printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n",
  420. priv->ndev->name);
  421. }
  422. finish_wait(&priv->reset_done, &wait);
  423. if (result) {
  424. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  425. return result;
  426. }
  427. islpci_set_state(priv, PRV_STATE_INIT);
  428. /* Now that the device is 100% up, let's allow
  429. * for the other interrupts --
  430. * NOTE: this is not *yet* true since we've only allowed the
  431. * INIT interrupt on the IRQ line. We can perhaps poll
  432. * the IRQ line until we know for sure the reset went through */
  433. isl38xx_enable_common_interrupts(priv->device_base);
  434. down_write(&priv->mib_sem);
  435. result = mgt_commit(priv);
  436. if (result) {
  437. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  438. up_write(&priv->mib_sem);
  439. return result;
  440. }
  441. up_write(&priv->mib_sem);
  442. islpci_set_state(priv, PRV_STATE_READY);
  443. printk(KERN_DEBUG "%s: interface reset complete\n", priv->ndev->name);
  444. return 0;
  445. }
  446. int
  447. islpci_reset(islpci_private *priv, int reload_firmware)
  448. {
  449. isl38xx_control_block *cb = /* volatile not needed */
  450. (isl38xx_control_block *) priv->control_block;
  451. unsigned counter;
  452. int rc;
  453. if (reload_firmware)
  454. islpci_set_state(priv, PRV_STATE_PREBOOT);
  455. else
  456. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  457. printk(KERN_DEBUG "%s: resetting device...\n", priv->ndev->name);
  458. /* disable all device interrupts in case they weren't */
  459. isl38xx_disable_interrupts(priv->device_base);
  460. /* flush all management queues */
  461. priv->index_mgmt_tx = 0;
  462. priv->index_mgmt_rx = 0;
  463. /* clear the indexes in the frame pointer */
  464. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  465. cb->driver_curr_frag[counter] = cpu_to_le32(0);
  466. cb->device_curr_frag[counter] = cpu_to_le32(0);
  467. }
  468. /* reset the mgmt receive queue */
  469. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  470. isl38xx_fragment *frag = &cb->rx_data_mgmt[counter];
  471. frag->size = cpu_to_le16(MGMT_FRAME_SIZE);
  472. frag->flags = 0;
  473. frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr);
  474. }
  475. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  476. cb->rx_data_low[counter].address =
  477. cpu_to_le32((u32) priv->pci_map_rx_address[counter]);
  478. }
  479. /* since the receive queues are filled with empty fragments, now we can
  480. * set the corresponding indexes in the Control Block */
  481. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_DATA_LQ] =
  482. cpu_to_le32(ISL38XX_CB_RX_QSIZE);
  483. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_MGMTQ] =
  484. cpu_to_le32(ISL38XX_CB_MGMT_QSIZE);
  485. /* reset the remaining real index registers and full flags */
  486. priv->free_data_rx = 0;
  487. priv->free_data_tx = 0;
  488. priv->data_low_tx_full = 0;
  489. if (reload_firmware) { /* Should we load the firmware ? */
  490. /* now that the data structures are cleaned up, upload
  491. * firmware and reset interface */
  492. rc = islpci_upload_fw(priv);
  493. if (rc) {
  494. printk(KERN_ERR "%s: islpci_reset: failure\n",
  495. priv->ndev->name);
  496. return rc;
  497. }
  498. }
  499. /* finally reset interface */
  500. rc = islpci_reset_if(priv);
  501. if (rc)
  502. printk(KERN_ERR "prism54: Your card/socket may be faulty, or IRQ line too busy :(\n");
  503. return rc;
  504. }
  505. /******************************************************************************
  506. Network device configuration functions
  507. ******************************************************************************/
  508. static int
  509. islpci_alloc_memory(islpci_private *priv)
  510. {
  511. int counter;
  512. #if VERBOSE > SHOW_ERROR_MESSAGES
  513. printk(KERN_DEBUG "islpci_alloc_memory\n");
  514. #endif
  515. /* remap the PCI device base address to accessable */
  516. if (!(priv->device_base =
  517. ioremap(pci_resource_start(priv->pdev, 0),
  518. ISL38XX_PCI_MEM_SIZE))) {
  519. /* error in remapping the PCI device memory address range */
  520. printk(KERN_ERR "PCI memory remapping failed \n");
  521. return -1;
  522. }
  523. /* memory layout for consistent DMA region:
  524. *
  525. * Area 1: Control Block for the device interface
  526. * Area 2: Power Save Mode Buffer for temporary frame storage. Be aware that
  527. * the number of supported stations in the AP determines the minimal
  528. * size of the buffer !
  529. */
  530. /* perform the allocation */
  531. priv->driver_mem_address = pci_alloc_consistent(priv->pdev,
  532. HOST_MEM_BLOCK,
  533. &priv->
  534. device_host_address);
  535. if (!priv->driver_mem_address) {
  536. /* error allocating the block of PCI memory */
  537. printk(KERN_ERR "%s: could not allocate DMA memory, aborting!",
  538. "prism54");
  539. return -1;
  540. }
  541. /* assign the Control Block to the first address of the allocated area */
  542. priv->control_block =
  543. (isl38xx_control_block *) priv->driver_mem_address;
  544. /* set the Power Save Buffer pointer directly behind the CB */
  545. priv->device_psm_buffer =
  546. priv->device_host_address + CONTROL_BLOCK_SIZE;
  547. /* make sure all buffer pointers are initialized */
  548. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  549. priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0);
  550. priv->control_block->device_curr_frag[counter] = cpu_to_le32(0);
  551. }
  552. priv->index_mgmt_rx = 0;
  553. memset(priv->mgmt_rx, 0, sizeof(priv->mgmt_rx));
  554. memset(priv->mgmt_tx, 0, sizeof(priv->mgmt_tx));
  555. /* allocate rx queue for management frames */
  556. if (islpci_mgmt_rx_fill(priv->ndev) < 0)
  557. goto out_free;
  558. /* now get the data rx skb's */
  559. memset(priv->data_low_rx, 0, sizeof (priv->data_low_rx));
  560. memset(priv->pci_map_rx_address, 0, sizeof (priv->pci_map_rx_address));
  561. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  562. struct sk_buff *skb;
  563. /* allocate an sk_buff for received data frames storage
  564. * each frame on receive size consists of 1 fragment
  565. * include any required allignment operations */
  566. if (!(skb = dev_alloc_skb(MAX_FRAGMENT_SIZE_RX + 2))) {
  567. /* error allocating an sk_buff structure elements */
  568. printk(KERN_ERR "Error allocating skb.\n");
  569. skb = NULL;
  570. goto out_free;
  571. }
  572. skb_reserve(skb, (4 - (long) skb->data) & 0x03);
  573. /* add the new allocated sk_buff to the buffer array */
  574. priv->data_low_rx[counter] = skb;
  575. /* map the allocated skb data area to pci */
  576. priv->pci_map_rx_address[counter] =
  577. pci_map_single(priv->pdev, (void *) skb->data,
  578. MAX_FRAGMENT_SIZE_RX + 2,
  579. PCI_DMA_FROMDEVICE);
  580. if (!priv->pci_map_rx_address[counter]) {
  581. /* error mapping the buffer to device
  582. accessable memory address */
  583. printk(KERN_ERR "failed to map skb DMA'able\n");
  584. goto out_free;
  585. }
  586. }
  587. prism54_acl_init(&priv->acl);
  588. prism54_wpa_bss_ie_init(priv);
  589. if (mgt_init(priv))
  590. goto out_free;
  591. return 0;
  592. out_free:
  593. islpci_free_memory(priv);
  594. return -1;
  595. }
  596. int
  597. islpci_free_memory(islpci_private *priv)
  598. {
  599. int counter;
  600. if (priv->device_base)
  601. iounmap(priv->device_base);
  602. priv->device_base = NULL;
  603. /* free consistent DMA area... */
  604. if (priv->driver_mem_address)
  605. pci_free_consistent(priv->pdev, HOST_MEM_BLOCK,
  606. priv->driver_mem_address,
  607. priv->device_host_address);
  608. /* clear some dangling pointers */
  609. priv->driver_mem_address = NULL;
  610. priv->device_host_address = 0;
  611. priv->device_psm_buffer = 0;
  612. priv->control_block = NULL;
  613. /* clean up mgmt rx buffers */
  614. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  615. struct islpci_membuf *buf = &priv->mgmt_rx[counter];
  616. if (buf->pci_addr)
  617. pci_unmap_single(priv->pdev, buf->pci_addr,
  618. buf->size, PCI_DMA_FROMDEVICE);
  619. buf->pci_addr = 0;
  620. kfree(buf->mem);
  621. buf->size = 0;
  622. buf->mem = NULL;
  623. }
  624. /* clean up data rx buffers */
  625. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  626. if (priv->pci_map_rx_address[counter])
  627. pci_unmap_single(priv->pdev,
  628. priv->pci_map_rx_address[counter],
  629. MAX_FRAGMENT_SIZE_RX + 2,
  630. PCI_DMA_FROMDEVICE);
  631. priv->pci_map_rx_address[counter] = 0;
  632. if (priv->data_low_rx[counter])
  633. dev_kfree_skb(priv->data_low_rx[counter]);
  634. priv->data_low_rx[counter] = NULL;
  635. }
  636. /* Free the acces control list and the WPA list */
  637. prism54_acl_clean(&priv->acl);
  638. prism54_wpa_bss_ie_clean(priv);
  639. mgt_clean(priv);
  640. return 0;
  641. }
  642. #if 0
  643. static void
  644. islpci_set_multicast_list(struct net_device *dev)
  645. {
  646. /* put device into promisc mode and let network layer handle it */
  647. }
  648. #endif
  649. static void islpci_ethtool_get_drvinfo(struct net_device *dev,
  650. struct ethtool_drvinfo *info)
  651. {
  652. strcpy(info->driver, DRV_NAME);
  653. strcpy(info->version, DRV_VERSION);
  654. }
  655. static const struct ethtool_ops islpci_ethtool_ops = {
  656. .get_drvinfo = islpci_ethtool_get_drvinfo,
  657. };
  658. static const struct net_device_ops islpci_netdev_ops = {
  659. .ndo_open = islpci_open,
  660. .ndo_stop = islpci_close,
  661. .ndo_do_ioctl = prism54_ioctl,
  662. .ndo_start_xmit = islpci_eth_transmit,
  663. .ndo_tx_timeout = islpci_eth_tx_timeout,
  664. .ndo_set_mac_address = prism54_set_mac_address,
  665. .ndo_change_mtu = eth_change_mtu,
  666. .ndo_validate_addr = eth_validate_addr,
  667. };
  668. struct net_device *
  669. islpci_setup(struct pci_dev *pdev)
  670. {
  671. islpci_private *priv;
  672. struct net_device *ndev = alloc_etherdev(sizeof (islpci_private));
  673. if (!ndev)
  674. return ndev;
  675. pci_set_drvdata(pdev, ndev);
  676. #if defined(SET_NETDEV_DEV)
  677. SET_NETDEV_DEV(ndev, &pdev->dev);
  678. #endif
  679. /* setup the structure members */
  680. ndev->base_addr = pci_resource_start(pdev, 0);
  681. ndev->irq = pdev->irq;
  682. /* initialize the function pointers */
  683. ndev->netdev_ops = &islpci_netdev_ops;
  684. ndev->wireless_handlers = &prism54_handler_def;
  685. ndev->ethtool_ops = &islpci_ethtool_ops;
  686. /* ndev->set_multicast_list = &islpci_set_multicast_list; */
  687. ndev->addr_len = ETH_ALEN;
  688. /* Get a non-zero dummy MAC address for nameif. Jean II */
  689. memcpy(ndev->dev_addr, dummy_mac, 6);
  690. ndev->watchdog_timeo = ISLPCI_TX_TIMEOUT;
  691. /* allocate a private device structure to the network device */
  692. priv = netdev_priv(ndev);
  693. priv->ndev = ndev;
  694. priv->pdev = pdev;
  695. priv->monitor_type = ARPHRD_IEEE80211;
  696. priv->ndev->type = (priv->iw_mode == IW_MODE_MONITOR) ?
  697. priv->monitor_type : ARPHRD_ETHER;
  698. /* Add pointers to enable iwspy support. */
  699. priv->wireless_data.spy_data = &priv->spy_data;
  700. ndev->wireless_data = &priv->wireless_data;
  701. /* save the start and end address of the PCI memory area */
  702. ndev->mem_start = (unsigned long) priv->device_base;
  703. ndev->mem_end = ndev->mem_start + ISL38XX_PCI_MEM_SIZE;
  704. #if VERBOSE > SHOW_ERROR_MESSAGES
  705. DEBUG(SHOW_TRACING, "PCI Memory remapped to 0x%p\n", priv->device_base);
  706. #endif
  707. init_waitqueue_head(&priv->reset_done);
  708. /* init the queue read locks, process wait counter */
  709. mutex_init(&priv->mgmt_lock);
  710. priv->mgmt_received = NULL;
  711. init_waitqueue_head(&priv->mgmt_wqueue);
  712. mutex_init(&priv->stats_lock);
  713. spin_lock_init(&priv->slock);
  714. /* init state machine with off#1 state */
  715. priv->state = PRV_STATE_OFF;
  716. priv->state_off = 1;
  717. /* initialize workqueue's */
  718. INIT_WORK(&priv->stats_work, prism54_update_stats);
  719. priv->stats_timestamp = 0;
  720. INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake);
  721. priv->reset_task_pending = 0;
  722. /* allocate various memory areas */
  723. if (islpci_alloc_memory(priv))
  724. goto do_free_netdev;
  725. /* select the firmware file depending on the device id */
  726. switch (pdev->device) {
  727. case 0x3877:
  728. strcpy(priv->firmware, ISL3877_IMAGE_FILE);
  729. break;
  730. case 0x3886:
  731. strcpy(priv->firmware, ISL3886_IMAGE_FILE);
  732. break;
  733. default:
  734. strcpy(priv->firmware, ISL3890_IMAGE_FILE);
  735. break;
  736. }
  737. if (register_netdev(ndev)) {
  738. DEBUG(SHOW_ERROR_MESSAGES,
  739. "ERROR: register_netdev() failed \n");
  740. goto do_islpci_free_memory;
  741. }
  742. return ndev;
  743. do_islpci_free_memory:
  744. islpci_free_memory(priv);
  745. do_free_netdev:
  746. pci_set_drvdata(pdev, NULL);
  747. free_netdev(ndev);
  748. priv = NULL;
  749. return NULL;
  750. }
  751. islpci_state_t
  752. islpci_set_state(islpci_private *priv, islpci_state_t new_state)
  753. {
  754. islpci_state_t old_state;
  755. /* lock */
  756. old_state = priv->state;
  757. /* this means either a race condition or some serious error in
  758. * the driver code */
  759. switch (new_state) {
  760. case PRV_STATE_OFF:
  761. priv->state_off++;
  762. default:
  763. priv->state = new_state;
  764. break;
  765. case PRV_STATE_PREBOOT:
  766. /* there are actually many off-states, enumerated by
  767. * state_off */
  768. if (old_state == PRV_STATE_OFF)
  769. priv->state_off--;
  770. /* only if hw_unavailable is zero now it means we either
  771. * were in off#1 state, or came here from
  772. * somewhere else */
  773. if (!priv->state_off)
  774. priv->state = new_state;
  775. break;
  776. };
  777. #if 0
  778. printk(KERN_DEBUG "%s: state transition %d -> %d (off#%d)\n",
  779. priv->ndev->name, old_state, new_state, priv->state_off);
  780. #endif
  781. /* invariants */
  782. BUG_ON(priv->state_off < 0);
  783. BUG_ON(priv->state_off && (priv->state != PRV_STATE_OFF));
  784. BUG_ON(!priv->state_off && (priv->state == PRV_STATE_OFF));
  785. /* unlock */
  786. return old_state;
  787. }