p54spi.c 17 KB

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  1. /*
  2. * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
  3. * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
  4. *
  5. * This driver is a port from stlc45xx:
  6. * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. */
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/firmware.h>
  26. #include <linux/delay.h>
  27. #include <linux/irq.h>
  28. #include <linux/spi/spi.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/gpio.h>
  31. #include "p54spi.h"
  32. #include "p54spi_eeprom.h"
  33. #include "p54.h"
  34. #include "lmac.h"
  35. MODULE_FIRMWARE("3826.arm");
  36. MODULE_ALIAS("stlc45xx");
  37. /*
  38. * gpios should be handled in board files and provided via platform data,
  39. * but because it's currently impossible for p54spi to have a header file
  40. * in include/linux, let's use module paramaters for now
  41. */
  42. static int p54spi_gpio_power = 97;
  43. module_param(p54spi_gpio_power, int, 0444);
  44. MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
  45. static int p54spi_gpio_irq = 87;
  46. module_param(p54spi_gpio_irq, int, 0444);
  47. MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
  48. static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
  49. void *buf, size_t len)
  50. {
  51. struct spi_transfer t[2];
  52. struct spi_message m;
  53. __le16 addr;
  54. /* We first push the address */
  55. addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
  56. spi_message_init(&m);
  57. memset(t, 0, sizeof(t));
  58. t[0].tx_buf = &addr;
  59. t[0].len = sizeof(addr);
  60. spi_message_add_tail(&t[0], &m);
  61. t[1].rx_buf = buf;
  62. t[1].len = len;
  63. spi_message_add_tail(&t[1], &m);
  64. spi_sync(priv->spi, &m);
  65. }
  66. static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
  67. const void *buf, size_t len)
  68. {
  69. struct spi_transfer t[3];
  70. struct spi_message m;
  71. __le16 addr;
  72. /* We first push the address */
  73. addr = cpu_to_le16(address << 8);
  74. spi_message_init(&m);
  75. memset(t, 0, sizeof(t));
  76. t[0].tx_buf = &addr;
  77. t[0].len = sizeof(addr);
  78. spi_message_add_tail(&t[0], &m);
  79. t[1].tx_buf = buf;
  80. t[1].len = len & ~1;
  81. spi_message_add_tail(&t[1], &m);
  82. if (len % 2) {
  83. __le16 last_word;
  84. last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
  85. t[2].tx_buf = &last_word;
  86. t[2].len = sizeof(last_word);
  87. spi_message_add_tail(&t[2], &m);
  88. }
  89. spi_sync(priv->spi, &m);
  90. }
  91. static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
  92. {
  93. __le32 val;
  94. p54spi_spi_read(priv, addr, &val, sizeof(val));
  95. return le32_to_cpu(val);
  96. }
  97. static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
  98. {
  99. p54spi_spi_write(priv, addr, &val, sizeof(val));
  100. }
  101. static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
  102. {
  103. p54spi_spi_write(priv, addr, &val, sizeof(val));
  104. }
  105. static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
  106. {
  107. int i;
  108. for (i = 0; i < 2000; i++) {
  109. u32 buffer = p54spi_read32(priv, reg);
  110. if ((buffer & bits) == bits)
  111. return 1;
  112. }
  113. return 0;
  114. }
  115. static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
  116. const void *buf, size_t len)
  117. {
  118. if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
  119. dev_err(&priv->spi->dev, "spi_write_dma not allowed "
  120. "to DMA write.\n");
  121. return -EAGAIN;
  122. }
  123. p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
  124. cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
  125. p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
  126. p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
  127. p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
  128. return 0;
  129. }
  130. static int p54spi_request_firmware(struct ieee80211_hw *dev)
  131. {
  132. struct p54s_priv *priv = dev->priv;
  133. int ret;
  134. /* FIXME: should driver use it's own struct device? */
  135. ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
  136. if (ret < 0) {
  137. dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
  138. return ret;
  139. }
  140. ret = p54_parse_firmware(dev, priv->firmware);
  141. if (ret) {
  142. release_firmware(priv->firmware);
  143. return ret;
  144. }
  145. return 0;
  146. }
  147. static int p54spi_request_eeprom(struct ieee80211_hw *dev)
  148. {
  149. struct p54s_priv *priv = dev->priv;
  150. const struct firmware *eeprom;
  151. int ret;
  152. /*
  153. * allow users to customize their eeprom.
  154. */
  155. ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
  156. if (ret < 0) {
  157. dev_info(&priv->spi->dev, "loading default eeprom...\n");
  158. ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
  159. sizeof(p54spi_eeprom));
  160. } else {
  161. dev_info(&priv->spi->dev, "loading user eeprom...\n");
  162. ret = p54_parse_eeprom(dev, (void *) eeprom->data,
  163. (int)eeprom->size);
  164. release_firmware(eeprom);
  165. }
  166. return ret;
  167. }
  168. static int p54spi_upload_firmware(struct ieee80211_hw *dev)
  169. {
  170. struct p54s_priv *priv = dev->priv;
  171. unsigned long fw_len, _fw_len;
  172. unsigned int offset = 0;
  173. int err = 0;
  174. u8 *fw;
  175. fw_len = priv->firmware->size;
  176. fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
  177. if (!fw)
  178. return -ENOMEM;
  179. /* stop the device */
  180. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  181. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
  182. SPI_CTRL_STAT_START_HALTED));
  183. msleep(TARGET_BOOT_SLEEP);
  184. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  185. SPI_CTRL_STAT_HOST_OVERRIDE |
  186. SPI_CTRL_STAT_START_HALTED));
  187. msleep(TARGET_BOOT_SLEEP);
  188. while (fw_len > 0) {
  189. _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
  190. err = p54spi_spi_write_dma(priv, cpu_to_le32(
  191. ISL38XX_DEV_FIRMWARE_ADDR + offset),
  192. (fw + offset), _fw_len);
  193. if (err < 0)
  194. goto out;
  195. fw_len -= _fw_len;
  196. offset += _fw_len;
  197. }
  198. BUG_ON(fw_len != 0);
  199. /* enable host interrupts */
  200. p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
  201. cpu_to_le32(SPI_HOST_INTS_DEFAULT));
  202. /* boot the device */
  203. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  204. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
  205. SPI_CTRL_STAT_RAM_BOOT));
  206. msleep(TARGET_BOOT_SLEEP);
  207. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  208. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
  209. msleep(TARGET_BOOT_SLEEP);
  210. out:
  211. kfree(fw);
  212. return err;
  213. }
  214. static void p54spi_power_off(struct p54s_priv *priv)
  215. {
  216. disable_irq(gpio_to_irq(p54spi_gpio_irq));
  217. gpio_set_value(p54spi_gpio_power, 0);
  218. }
  219. static void p54spi_power_on(struct p54s_priv *priv)
  220. {
  221. gpio_set_value(p54spi_gpio_power, 1);
  222. enable_irq(gpio_to_irq(p54spi_gpio_irq));
  223. /*
  224. * need to wait a while before device can be accessed, the lenght
  225. * is just a guess
  226. */
  227. msleep(10);
  228. }
  229. static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
  230. {
  231. p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
  232. }
  233. static int p54spi_wakeup(struct p54s_priv *priv)
  234. {
  235. /* wake the chip */
  236. p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
  237. cpu_to_le32(SPI_TARGET_INT_WAKEUP));
  238. /* And wait for the READY interrupt */
  239. if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
  240. SPI_HOST_INT_READY)) {
  241. dev_err(&priv->spi->dev, "INT_READY timeout\n");
  242. return -EBUSY;
  243. }
  244. p54spi_int_ack(priv, SPI_HOST_INT_READY);
  245. return 0;
  246. }
  247. static inline void p54spi_sleep(struct p54s_priv *priv)
  248. {
  249. p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
  250. cpu_to_le32(SPI_TARGET_INT_SLEEP));
  251. }
  252. static void p54spi_int_ready(struct p54s_priv *priv)
  253. {
  254. p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
  255. SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
  256. switch (priv->fw_state) {
  257. case FW_STATE_BOOTING:
  258. priv->fw_state = FW_STATE_READY;
  259. complete(&priv->fw_comp);
  260. break;
  261. case FW_STATE_RESETTING:
  262. priv->fw_state = FW_STATE_READY;
  263. /* TODO: reinitialize state */
  264. break;
  265. default:
  266. break;
  267. }
  268. }
  269. static int p54spi_rx(struct p54s_priv *priv)
  270. {
  271. struct sk_buff *skb;
  272. u16 len;
  273. u16 rx_head[2];
  274. #define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
  275. if (p54spi_wakeup(priv) < 0)
  276. return -EBUSY;
  277. /* Read data size and first data word in one SPI transaction
  278. * This is workaround for firmware/DMA bug,
  279. * when first data word gets lost under high load.
  280. */
  281. p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
  282. len = rx_head[0];
  283. if (len == 0) {
  284. p54spi_sleep(priv);
  285. dev_err(&priv->spi->dev, "rx request of zero bytes\n");
  286. return 0;
  287. }
  288. /* Firmware may insert up to 4 padding bytes after the lmac header,
  289. * but it does not amend the size of SPI data transfer.
  290. * Such packets has correct data size in header, thus referencing
  291. * past the end of allocated skb. Reserve extra 4 bytes for this case */
  292. skb = dev_alloc_skb(len + 4);
  293. if (!skb) {
  294. p54spi_sleep(priv);
  295. dev_err(&priv->spi->dev, "could not alloc skb");
  296. return -ENOMEM;
  297. }
  298. if (len <= READAHEAD_SZ) {
  299. memcpy(skb_put(skb, len), rx_head + 1, len);
  300. } else {
  301. memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
  302. p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
  303. skb_put(skb, len - READAHEAD_SZ),
  304. len - READAHEAD_SZ);
  305. }
  306. p54spi_sleep(priv);
  307. /* Put additional bytes to compensate for the possible
  308. * alignment-caused truncation */
  309. skb_put(skb, 4);
  310. if (p54_rx(priv->hw, skb) == 0)
  311. dev_kfree_skb(skb);
  312. return 0;
  313. }
  314. static irqreturn_t p54spi_interrupt(int irq, void *config)
  315. {
  316. struct spi_device *spi = config;
  317. struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
  318. ieee80211_queue_work(priv->hw, &priv->work);
  319. return IRQ_HANDLED;
  320. }
  321. static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
  322. {
  323. struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
  324. int ret = 0;
  325. if (p54spi_wakeup(priv) < 0)
  326. return -EBUSY;
  327. ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
  328. if (ret < 0)
  329. goto out;
  330. if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
  331. SPI_HOST_INT_WR_READY)) {
  332. dev_err(&priv->spi->dev, "WR_READY timeout\n");
  333. ret = -EAGAIN;
  334. goto out;
  335. }
  336. p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
  337. if (FREE_AFTER_TX(skb))
  338. p54_free_skb(priv->hw, skb);
  339. out:
  340. p54spi_sleep(priv);
  341. return ret;
  342. }
  343. static int p54spi_wq_tx(struct p54s_priv *priv)
  344. {
  345. struct p54s_tx_info *entry;
  346. struct sk_buff *skb;
  347. struct ieee80211_tx_info *info;
  348. struct p54_tx_info *minfo;
  349. struct p54s_tx_info *dinfo;
  350. unsigned long flags;
  351. int ret = 0;
  352. spin_lock_irqsave(&priv->tx_lock, flags);
  353. while (!list_empty(&priv->tx_pending)) {
  354. entry = list_entry(priv->tx_pending.next,
  355. struct p54s_tx_info, tx_list);
  356. list_del_init(&entry->tx_list);
  357. spin_unlock_irqrestore(&priv->tx_lock, flags);
  358. dinfo = container_of((void *) entry, struct p54s_tx_info,
  359. tx_list);
  360. minfo = container_of((void *) dinfo, struct p54_tx_info,
  361. data);
  362. info = container_of((void *) minfo, struct ieee80211_tx_info,
  363. rate_driver_data);
  364. skb = container_of((void *) info, struct sk_buff, cb);
  365. ret = p54spi_tx_frame(priv, skb);
  366. if (ret < 0) {
  367. p54_free_skb(priv->hw, skb);
  368. return ret;
  369. }
  370. spin_lock_irqsave(&priv->tx_lock, flags);
  371. }
  372. spin_unlock_irqrestore(&priv->tx_lock, flags);
  373. return ret;
  374. }
  375. static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  376. {
  377. struct p54s_priv *priv = dev->priv;
  378. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  379. struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
  380. struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
  381. unsigned long flags;
  382. BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
  383. spin_lock_irqsave(&priv->tx_lock, flags);
  384. list_add_tail(&di->tx_list, &priv->tx_pending);
  385. spin_unlock_irqrestore(&priv->tx_lock, flags);
  386. ieee80211_queue_work(priv->hw, &priv->work);
  387. }
  388. static void p54spi_work(struct work_struct *work)
  389. {
  390. struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
  391. u32 ints;
  392. int ret;
  393. mutex_lock(&priv->mutex);
  394. if (priv->fw_state == FW_STATE_OFF)
  395. goto out;
  396. ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
  397. if (ints & SPI_HOST_INT_READY) {
  398. p54spi_int_ready(priv);
  399. p54spi_int_ack(priv, SPI_HOST_INT_READY);
  400. }
  401. if (priv->fw_state != FW_STATE_READY)
  402. goto out;
  403. if (ints & SPI_HOST_INT_UPDATE) {
  404. p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
  405. ret = p54spi_rx(priv);
  406. if (ret < 0)
  407. goto out;
  408. }
  409. if (ints & SPI_HOST_INT_SW_UPDATE) {
  410. p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
  411. ret = p54spi_rx(priv);
  412. if (ret < 0)
  413. goto out;
  414. }
  415. ret = p54spi_wq_tx(priv);
  416. out:
  417. mutex_unlock(&priv->mutex);
  418. }
  419. static int p54spi_op_start(struct ieee80211_hw *dev)
  420. {
  421. struct p54s_priv *priv = dev->priv;
  422. unsigned long timeout;
  423. int ret = 0;
  424. if (mutex_lock_interruptible(&priv->mutex)) {
  425. ret = -EINTR;
  426. goto out;
  427. }
  428. priv->fw_state = FW_STATE_BOOTING;
  429. p54spi_power_on(priv);
  430. ret = p54spi_upload_firmware(dev);
  431. if (ret < 0) {
  432. p54spi_power_off(priv);
  433. goto out_unlock;
  434. }
  435. mutex_unlock(&priv->mutex);
  436. timeout = msecs_to_jiffies(2000);
  437. timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
  438. timeout);
  439. if (!timeout) {
  440. dev_err(&priv->spi->dev, "firmware boot failed");
  441. p54spi_power_off(priv);
  442. ret = -1;
  443. goto out;
  444. }
  445. if (mutex_lock_interruptible(&priv->mutex)) {
  446. ret = -EINTR;
  447. p54spi_power_off(priv);
  448. goto out;
  449. }
  450. WARN_ON(priv->fw_state != FW_STATE_READY);
  451. out_unlock:
  452. mutex_unlock(&priv->mutex);
  453. out:
  454. return ret;
  455. }
  456. static void p54spi_op_stop(struct ieee80211_hw *dev)
  457. {
  458. struct p54s_priv *priv = dev->priv;
  459. unsigned long flags;
  460. if (mutex_lock_interruptible(&priv->mutex)) {
  461. /* FIXME: how to handle this error? */
  462. return;
  463. }
  464. WARN_ON(priv->fw_state != FW_STATE_READY);
  465. cancel_work_sync(&priv->work);
  466. p54spi_power_off(priv);
  467. spin_lock_irqsave(&priv->tx_lock, flags);
  468. INIT_LIST_HEAD(&priv->tx_pending);
  469. spin_unlock_irqrestore(&priv->tx_lock, flags);
  470. priv->fw_state = FW_STATE_OFF;
  471. mutex_unlock(&priv->mutex);
  472. }
  473. static int __devinit p54spi_probe(struct spi_device *spi)
  474. {
  475. struct p54s_priv *priv = NULL;
  476. struct ieee80211_hw *hw;
  477. int ret = -EINVAL;
  478. hw = p54_init_common(sizeof(*priv));
  479. if (!hw) {
  480. dev_err(&spi->dev, "could not alloc ieee80211_hw");
  481. return -ENOMEM;
  482. }
  483. priv = hw->priv;
  484. priv->hw = hw;
  485. dev_set_drvdata(&spi->dev, priv);
  486. priv->spi = spi;
  487. spi->bits_per_word = 16;
  488. spi->max_speed_hz = 24000000;
  489. ret = spi_setup(spi);
  490. if (ret < 0) {
  491. dev_err(&priv->spi->dev, "spi_setup failed");
  492. goto err_free_common;
  493. }
  494. ret = gpio_request(p54spi_gpio_power, "p54spi power");
  495. if (ret < 0) {
  496. dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
  497. goto err_free_common;
  498. }
  499. ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
  500. if (ret < 0) {
  501. dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
  502. goto err_free_common;
  503. }
  504. gpio_direction_output(p54spi_gpio_power, 0);
  505. gpio_direction_input(p54spi_gpio_irq);
  506. ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
  507. p54spi_interrupt, IRQF_DISABLED, "p54spi",
  508. priv->spi);
  509. if (ret < 0) {
  510. dev_err(&priv->spi->dev, "request_irq() failed");
  511. goto err_free_common;
  512. }
  513. set_irq_type(gpio_to_irq(p54spi_gpio_irq),
  514. IRQ_TYPE_EDGE_RISING);
  515. disable_irq(gpio_to_irq(p54spi_gpio_irq));
  516. INIT_WORK(&priv->work, p54spi_work);
  517. init_completion(&priv->fw_comp);
  518. INIT_LIST_HEAD(&priv->tx_pending);
  519. mutex_init(&priv->mutex);
  520. SET_IEEE80211_DEV(hw, &spi->dev);
  521. priv->common.open = p54spi_op_start;
  522. priv->common.stop = p54spi_op_stop;
  523. priv->common.tx = p54spi_op_tx;
  524. ret = p54spi_request_firmware(hw);
  525. if (ret < 0)
  526. goto err_free_common;
  527. ret = p54spi_request_eeprom(hw);
  528. if (ret)
  529. goto err_free_common;
  530. ret = p54_register_common(hw, &priv->spi->dev);
  531. if (ret)
  532. goto err_free_common;
  533. return 0;
  534. err_free_common:
  535. p54_free_common(priv->hw);
  536. return ret;
  537. }
  538. static int __devexit p54spi_remove(struct spi_device *spi)
  539. {
  540. struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
  541. p54_unregister_common(priv->hw);
  542. free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
  543. gpio_free(p54spi_gpio_power);
  544. gpio_free(p54spi_gpio_irq);
  545. release_firmware(priv->firmware);
  546. mutex_destroy(&priv->mutex);
  547. p54_free_common(priv->hw);
  548. return 0;
  549. }
  550. static struct spi_driver p54spi_driver = {
  551. .driver = {
  552. /* use cx3110x name because board-n800.c uses that for the
  553. * SPI port */
  554. .name = "cx3110x",
  555. .bus = &spi_bus_type,
  556. .owner = THIS_MODULE,
  557. },
  558. .probe = p54spi_probe,
  559. .remove = __devexit_p(p54spi_remove),
  560. };
  561. static int __init p54spi_init(void)
  562. {
  563. int ret;
  564. ret = spi_register_driver(&p54spi_driver);
  565. if (ret < 0) {
  566. printk(KERN_ERR "failed to register SPI driver: %d", ret);
  567. goto out;
  568. }
  569. out:
  570. return ret;
  571. }
  572. static void __exit p54spi_exit(void)
  573. {
  574. spi_unregister_driver(&p54spi_driver);
  575. }
  576. module_init(p54spi_init);
  577. module_exit(p54spi_exit);
  578. MODULE_LICENSE("GPL");
  579. MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
  580. MODULE_ALIAS("spi:cx3110x");