b43legacy.h 26 KB

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  1. #ifndef B43legacy_H_
  2. #define B43legacy_H_
  3. #include <linux/hw_random.h>
  4. #include <linux/kernel.h>
  5. #include <linux/spinlock.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/stringify.h>
  8. #include <linux/netdevice.h>
  9. #include <linux/pci.h>
  10. #include <asm/atomic.h>
  11. #include <linux/io.h>
  12. #include <linux/ssb/ssb.h>
  13. #include <linux/ssb/ssb_driver_chipcommon.h>
  14. #include <linux/wireless.h>
  15. #include <net/mac80211.h>
  16. #include "debugfs.h"
  17. #include "leds.h"
  18. #include "rfkill.h"
  19. #include "phy.h"
  20. /* The unique identifier of the firmware that's officially supported by this
  21. * driver version. */
  22. #define B43legacy_SUPPORTED_FIRMWARE_ID "FW10"
  23. #define B43legacy_IRQWAIT_MAX_RETRIES 20
  24. #define B43legacy_RX_MAX_SSI 60 /* best guess at max ssi */
  25. /* MMIO offsets */
  26. #define B43legacy_MMIO_DMA0_REASON 0x20
  27. #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
  28. #define B43legacy_MMIO_DMA1_REASON 0x28
  29. #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
  30. #define B43legacy_MMIO_DMA2_REASON 0x30
  31. #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
  32. #define B43legacy_MMIO_DMA3_REASON 0x38
  33. #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
  34. #define B43legacy_MMIO_DMA4_REASON 0x40
  35. #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
  36. #define B43legacy_MMIO_DMA5_REASON 0x48
  37. #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
  38. #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
  39. #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
  40. #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
  41. #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
  42. #define B43legacy_MMIO_RAM_CONTROL 0x130
  43. #define B43legacy_MMIO_RAM_DATA 0x134
  44. #define B43legacy_MMIO_PS_STATUS 0x140
  45. #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
  46. #define B43legacy_MMIO_SHM_CONTROL 0x160
  47. #define B43legacy_MMIO_SHM_DATA 0x164
  48. #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
  49. #define B43legacy_MMIO_XMITSTAT_0 0x170
  50. #define B43legacy_MMIO_XMITSTAT_1 0x174
  51. #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
  52. #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
  53. #define B43legacy_MMIO_TSF_CFP_REP 0x188
  54. #define B43legacy_MMIO_TSF_CFP_START 0x18C
  55. /* 32-bit DMA */
  56. #define B43legacy_MMIO_DMA32_BASE0 0x200
  57. #define B43legacy_MMIO_DMA32_BASE1 0x220
  58. #define B43legacy_MMIO_DMA32_BASE2 0x240
  59. #define B43legacy_MMIO_DMA32_BASE3 0x260
  60. #define B43legacy_MMIO_DMA32_BASE4 0x280
  61. #define B43legacy_MMIO_DMA32_BASE5 0x2A0
  62. /* 64-bit DMA */
  63. #define B43legacy_MMIO_DMA64_BASE0 0x200
  64. #define B43legacy_MMIO_DMA64_BASE1 0x240
  65. #define B43legacy_MMIO_DMA64_BASE2 0x280
  66. #define B43legacy_MMIO_DMA64_BASE3 0x2C0
  67. #define B43legacy_MMIO_DMA64_BASE4 0x300
  68. #define B43legacy_MMIO_DMA64_BASE5 0x340
  69. /* PIO */
  70. #define B43legacy_MMIO_PIO1_BASE 0x300
  71. #define B43legacy_MMIO_PIO2_BASE 0x310
  72. #define B43legacy_MMIO_PIO3_BASE 0x320
  73. #define B43legacy_MMIO_PIO4_BASE 0x330
  74. #define B43legacy_MMIO_PHY_VER 0x3E0
  75. #define B43legacy_MMIO_PHY_RADIO 0x3E2
  76. #define B43legacy_MMIO_PHY0 0x3E6
  77. #define B43legacy_MMIO_ANTENNA 0x3E8
  78. #define B43legacy_MMIO_CHANNEL 0x3F0
  79. #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
  80. #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
  81. #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
  82. #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
  83. #define B43legacy_MMIO_PHY_CONTROL 0x3FC
  84. #define B43legacy_MMIO_PHY_DATA 0x3FE
  85. #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
  86. #define B43legacy_MMIO_MACFILTER_DATA 0x422
  87. #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
  88. #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
  89. #define B43legacy_MMIO_GPIO_CONTROL 0x49C
  90. #define B43legacy_MMIO_GPIO_MASK 0x49E
  91. #define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612
  92. #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
  93. #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
  94. #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
  95. #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
  96. #define B43legacy_MMIO_RNG 0x65A
  97. #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
  98. /* SPROM boardflags_lo values */
  99. #define B43legacy_BFL_PACTRL 0x0002
  100. #define B43legacy_BFL_RSSI 0x0008
  101. #define B43legacy_BFL_EXTLNA 0x1000
  102. /* GPIO register offset, in both ChipCommon and PCI core. */
  103. #define B43legacy_GPIO_CONTROL 0x6c
  104. /* SHM Routing */
  105. #define B43legacy_SHM_SHARED 0x0001
  106. #define B43legacy_SHM_WIRELESS 0x0002
  107. #define B43legacy_SHM_HW 0x0004
  108. #define B43legacy_SHM_UCODE 0x0300
  109. /* SHM Routing modifiers */
  110. #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
  111. #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
  112. #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \
  113. B43legacy_SHM_AUTOINC_W)
  114. /* Misc SHM_SHARED offsets */
  115. #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
  116. #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
  117. #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
  118. /* SHM_SHARED crypto engine */
  119. #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
  120. /* SHM_SHARED beacon/AP variables */
  121. #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */
  122. #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
  123. #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
  124. #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
  125. #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */
  126. #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
  127. /* SHM_SHARED ACK/CTS control */
  128. #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
  129. /* SHM_SHARED probe response variables */
  130. #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
  131. #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
  132. #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
  133. /* SHM_SHARED rate tables */
  134. #define B43legacy_SHM_SH_OFDMDIRECT 0x0480 /* Pointer to OFDM direct map */
  135. #define B43legacy_SHM_SH_OFDMBASIC 0x04A0 /* Pointer to OFDM basic rate map */
  136. #define B43legacy_SHM_SH_CCKDIRECT 0x04C0 /* Pointer to CCK direct map */
  137. #define B43legacy_SHM_SH_CCKBASIC 0x04E0 /* Pointer to CCK basic rate map */
  138. /* SHM_SHARED microcode soft registers */
  139. #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
  140. #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
  141. #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
  142. #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
  143. #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
  144. #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
  145. #define B43legacy_UCODEFLAGS_OFFSET 0x005E
  146. /* Hardware Radio Enable masks */
  147. #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
  148. #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
  149. /* HostFlags. See b43legacy_hf_read/write() */
  150. #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
  151. #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
  152. #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
  153. #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
  154. /* MacFilter offsets. */
  155. #define B43legacy_MACFILTER_SELF 0x0000
  156. #define B43legacy_MACFILTER_BSSID 0x0003
  157. #define B43legacy_MACFILTER_MAC 0x0010
  158. /* PHYVersioning */
  159. #define B43legacy_PHYTYPE_B 0x01
  160. #define B43legacy_PHYTYPE_G 0x02
  161. /* PHYRegisters */
  162. #define B43legacy_PHY_G_LO_CONTROL 0x0810
  163. #define B43legacy_PHY_ILT_G_CTRL 0x0472
  164. #define B43legacy_PHY_ILT_G_DATA1 0x0473
  165. #define B43legacy_PHY_ILT_G_DATA2 0x0474
  166. #define B43legacy_PHY_G_PCTL 0x0029
  167. #define B43legacy_PHY_RADIO_BITFIELD 0x0401
  168. #define B43legacy_PHY_G_CRS 0x0429
  169. #define B43legacy_PHY_NRSSILT_CTRL 0x0803
  170. #define B43legacy_PHY_NRSSILT_DATA 0x0804
  171. /* RadioRegisters */
  172. #define B43legacy_RADIOCTL_ID 0x01
  173. /* MAC Control bitfield */
  174. #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
  175. #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
  176. #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
  177. #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
  178. #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
  179. #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
  180. #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
  181. #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
  182. #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
  183. #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
  184. #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
  185. #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
  186. #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
  187. #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
  188. #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
  189. #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
  190. #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
  191. #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
  192. /* MAC Command bitfield */
  193. #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
  194. #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
  195. #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
  196. #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */
  197. #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */
  198. /* 802.11 core specific TM State Low flags */
  199. #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
  200. #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
  201. #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
  202. #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
  203. #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
  204. /* 802.11 core specific TM State High flags */
  205. #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
  206. #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
  207. #define B43legacy_UCODEFLAG_AUTODIV 0x0001
  208. /* Generic-Interrupt reasons. */
  209. #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
  210. #define B43legacy_IRQ_BEACON 0x00000002
  211. #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
  212. #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
  213. #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
  214. #define B43legacy_IRQ_ATIM_END 0x00000020
  215. #define B43legacy_IRQ_PMQ 0x00000040
  216. #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
  217. #define B43legacy_IRQ_MAC_TXERR 0x00000200
  218. #define B43legacy_IRQ_PHY_TXERR 0x00000800
  219. #define B43legacy_IRQ_PMEVENT 0x00001000
  220. #define B43legacy_IRQ_TIMER0 0x00002000
  221. #define B43legacy_IRQ_TIMER1 0x00004000
  222. #define B43legacy_IRQ_DMA 0x00008000
  223. #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
  224. #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
  225. #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
  226. #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
  227. #define B43legacy_IRQ_RFKILL 0x10000000
  228. #define B43legacy_IRQ_TX_OK 0x20000000
  229. #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
  230. #define B43legacy_IRQ_TIMEOUT 0x80000000
  231. #define B43legacy_IRQ_ALL 0xFFFFFFFF
  232. #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \
  233. B43legacy_IRQ_TBTT_INDI | \
  234. B43legacy_IRQ_ATIM_END | \
  235. B43legacy_IRQ_PMQ | \
  236. B43legacy_IRQ_MAC_TXERR | \
  237. B43legacy_IRQ_PHY_TXERR | \
  238. B43legacy_IRQ_DMA | \
  239. B43legacy_IRQ_TXFIFO_FLUSH_OK | \
  240. B43legacy_IRQ_NOISESAMPLE_OK | \
  241. B43legacy_IRQ_UCODE_DEBUG | \
  242. B43legacy_IRQ_RFKILL | \
  243. B43legacy_IRQ_TX_OK)
  244. /* Device specific rate values.
  245. * The actual values defined here are (rate_in_mbps * 2).
  246. * Some code depends on this. Don't change it. */
  247. #define B43legacy_CCK_RATE_1MB 2
  248. #define B43legacy_CCK_RATE_2MB 4
  249. #define B43legacy_CCK_RATE_5MB 11
  250. #define B43legacy_CCK_RATE_11MB 22
  251. #define B43legacy_OFDM_RATE_6MB 12
  252. #define B43legacy_OFDM_RATE_9MB 18
  253. #define B43legacy_OFDM_RATE_12MB 24
  254. #define B43legacy_OFDM_RATE_18MB 36
  255. #define B43legacy_OFDM_RATE_24MB 48
  256. #define B43legacy_OFDM_RATE_36MB 72
  257. #define B43legacy_OFDM_RATE_48MB 96
  258. #define B43legacy_OFDM_RATE_54MB 108
  259. /* Convert a b43legacy rate value to a rate in 100kbps */
  260. #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
  261. #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7
  262. #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4
  263. #define B43legacy_PHY_TX_BADNESS_LIMIT 1000
  264. /* Max size of a security key */
  265. #define B43legacy_SEC_KEYSIZE 16
  266. /* Security algorithms. */
  267. enum {
  268. B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
  269. B43legacy_SEC_ALGO_WEP40,
  270. B43legacy_SEC_ALGO_TKIP,
  271. B43legacy_SEC_ALGO_AES,
  272. B43legacy_SEC_ALGO_WEP104,
  273. B43legacy_SEC_ALGO_AES_LEGACY,
  274. };
  275. /* Core Information Registers */
  276. #define B43legacy_CIR_BASE 0xf00
  277. #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
  278. #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
  279. #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
  280. #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
  281. #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
  282. #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
  283. #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
  284. /* sbtmstatehigh state flags */
  285. #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
  286. #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
  287. #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
  288. #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
  289. #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
  290. #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
  291. #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
  292. #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
  293. #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
  294. /* sbimstate flags */
  295. #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
  296. #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
  297. #define PFX KBUILD_MODNAME ": "
  298. #ifdef assert
  299. # undef assert
  300. #endif
  301. #ifdef CONFIG_B43LEGACY_DEBUG
  302. # define B43legacy_WARN_ON(x) WARN_ON(x)
  303. # define B43legacy_BUG_ON(expr) \
  304. do { \
  305. if (unlikely((expr))) { \
  306. printk(KERN_INFO PFX "Test (%s) failed\n", \
  307. #expr); \
  308. BUG_ON(expr); \
  309. } \
  310. } while (0)
  311. # define B43legacy_DEBUG 1
  312. #else
  313. /* This will evaluate the argument even if debugging is disabled. */
  314. static inline bool __b43legacy_warn_on_dummy(bool x) { return x; }
  315. # define B43legacy_WARN_ON(x) __b43legacy_warn_on_dummy(unlikely(!!(x)))
  316. # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
  317. # define B43legacy_DEBUG 0
  318. #endif
  319. struct net_device;
  320. struct pci_dev;
  321. struct b43legacy_dmaring;
  322. struct b43legacy_pioqueue;
  323. /* The firmware file header */
  324. #define B43legacy_FW_TYPE_UCODE 'u'
  325. #define B43legacy_FW_TYPE_PCM 'p'
  326. #define B43legacy_FW_TYPE_IV 'i'
  327. struct b43legacy_fw_header {
  328. /* File type */
  329. u8 type;
  330. /* File format version */
  331. u8 ver;
  332. u8 __padding[2];
  333. /* Size of the data. For ucode and PCM this is in bytes.
  334. * For IV this is number-of-ivs. */
  335. __be32 size;
  336. } __attribute__((__packed__));
  337. /* Initial Value file format */
  338. #define B43legacy_IV_OFFSET_MASK 0x7FFF
  339. #define B43legacy_IV_32BIT 0x8000
  340. struct b43legacy_iv {
  341. __be16 offset_size;
  342. union {
  343. __be16 d16;
  344. __be32 d32;
  345. } data __attribute__((__packed__));
  346. } __attribute__((__packed__));
  347. #define B43legacy_PHYMODE(phytype) (1 << (phytype))
  348. #define B43legacy_PHYMODE_B B43legacy_PHYMODE \
  349. ((B43legacy_PHYTYPE_B))
  350. #define B43legacy_PHYMODE_G B43legacy_PHYMODE \
  351. ((B43legacy_PHYTYPE_G))
  352. /* Value pair to measure the LocalOscillator. */
  353. struct b43legacy_lopair {
  354. s8 low;
  355. s8 high;
  356. u8 used:1;
  357. };
  358. #define B43legacy_LO_COUNT (14*4)
  359. struct b43legacy_phy {
  360. /* Possible PHYMODEs on this PHY */
  361. u8 possible_phymodes;
  362. /* GMODE bit enabled in MACCTL? */
  363. bool gmode;
  364. /* Analog Type */
  365. u8 analog;
  366. /* B43legacy_PHYTYPE_ */
  367. u8 type;
  368. /* PHY revision number. */
  369. u8 rev;
  370. u16 antenna_diversity;
  371. u16 savedpctlreg;
  372. /* Radio versioning */
  373. u16 radio_manuf; /* Radio manufacturer */
  374. u16 radio_ver; /* Radio version */
  375. u8 calibrated:1;
  376. u8 radio_rev; /* Radio revision */
  377. bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
  378. /* ACI (adjacent channel interference) flags. */
  379. bool aci_enable;
  380. bool aci_wlan_automatic;
  381. bool aci_hw_rssi;
  382. /* Radio switched on/off */
  383. bool radio_on;
  384. struct {
  385. /* Values saved when turning the radio off.
  386. * They are needed when turning it on again. */
  387. bool valid;
  388. u16 rfover;
  389. u16 rfoverval;
  390. } radio_off_context;
  391. u16 minlowsig[2];
  392. u16 minlowsigpos[2];
  393. /* LO Measurement Data.
  394. * Use b43legacy_get_lopair() to get a value.
  395. */
  396. struct b43legacy_lopair *_lo_pairs;
  397. /* TSSI to dBm table in use */
  398. const s8 *tssi2dbm;
  399. /* idle TSSI value */
  400. s8 idle_tssi;
  401. /* Target idle TSSI */
  402. int tgt_idle_tssi;
  403. /* Current idle TSSI */
  404. int cur_idle_tssi;
  405. /* LocalOscillator control values. */
  406. struct b43legacy_txpower_lo_control *lo_control;
  407. /* Values from b43legacy_calc_loopback_gain() */
  408. s16 max_lb_gain; /* Maximum Loopback gain in hdB */
  409. s16 trsw_rx_gain; /* TRSW RX gain in hdB */
  410. s16 lna_lod_gain; /* LNA lod */
  411. s16 lna_gain; /* LNA */
  412. s16 pga_gain; /* PGA */
  413. /* Desired TX power level (in dBm). This is set by the user and
  414. * adjusted in b43legacy_phy_xmitpower(). */
  415. u8 power_level;
  416. /* Values from b43legacy_calc_loopback_gain() */
  417. u16 loopback_gain[2];
  418. /* TX Power control values. */
  419. /* B/G PHY */
  420. struct {
  421. /* Current Radio Attenuation for TXpower recalculation. */
  422. u16 rfatt;
  423. /* Current Baseband Attenuation for TXpower recalculation. */
  424. u16 bbatt;
  425. /* Current TXpower control value for TXpower recalculation. */
  426. u16 txctl1;
  427. u16 txctl2;
  428. };
  429. /* A PHY */
  430. struct {
  431. u16 txpwr_offset;
  432. };
  433. /* Current Interference Mitigation mode */
  434. int interfmode;
  435. /* Stack of saved values from the Interference Mitigation code.
  436. * Each value in the stack is layed out as follows:
  437. * bit 0-11: offset
  438. * bit 12-15: register ID
  439. * bit 16-32: value
  440. * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
  441. */
  442. #define B43legacy_INTERFSTACK_SIZE 26
  443. u32 interfstack[B43legacy_INTERFSTACK_SIZE];
  444. /* Saved values from the NRSSI Slope calculation */
  445. s16 nrssi[2];
  446. s32 nrssislope;
  447. /* In memory nrssi lookup table. */
  448. s8 nrssi_lt[64];
  449. /* current channel */
  450. u8 channel;
  451. u16 lofcal;
  452. u16 initval;
  453. /* PHY TX errors counter. */
  454. atomic_t txerr_cnt;
  455. #if B43legacy_DEBUG
  456. /* Manual TX-power control enabled? */
  457. bool manual_txpower_control;
  458. /* PHY registers locked by b43legacy_phy_lock()? */
  459. bool phy_locked;
  460. #endif /* B43legacy_DEBUG */
  461. };
  462. /* Data structures for DMA transmission, per 80211 core. */
  463. struct b43legacy_dma {
  464. struct b43legacy_dmaring *tx_ring0;
  465. struct b43legacy_dmaring *tx_ring1;
  466. struct b43legacy_dmaring *tx_ring2;
  467. struct b43legacy_dmaring *tx_ring3;
  468. struct b43legacy_dmaring *tx_ring4;
  469. struct b43legacy_dmaring *tx_ring5;
  470. struct b43legacy_dmaring *rx_ring0;
  471. struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
  472. };
  473. /* Data structures for PIO transmission, per 80211 core. */
  474. struct b43legacy_pio {
  475. struct b43legacy_pioqueue *queue0;
  476. struct b43legacy_pioqueue *queue1;
  477. struct b43legacy_pioqueue *queue2;
  478. struct b43legacy_pioqueue *queue3;
  479. };
  480. /* Context information for a noise calculation (Link Quality). */
  481. struct b43legacy_noise_calculation {
  482. u8 channel_at_start;
  483. bool calculation_running;
  484. u8 nr_samples;
  485. s8 samples[8][4];
  486. };
  487. struct b43legacy_stats {
  488. u8 link_noise;
  489. /* Store the last TX/RX times here for updating the leds. */
  490. unsigned long last_tx;
  491. unsigned long last_rx;
  492. };
  493. struct b43legacy_key {
  494. void *keyconf;
  495. bool enabled;
  496. u8 algorithm;
  497. };
  498. struct b43legacy_wldev;
  499. /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
  500. struct b43legacy_wl {
  501. /* Pointer to the active wireless device on this chip */
  502. struct b43legacy_wldev *current_dev;
  503. /* Pointer to the ieee80211 hardware data structure */
  504. struct ieee80211_hw *hw;
  505. spinlock_t irq_lock; /* locks IRQ */
  506. struct mutex mutex; /* locks wireless core state */
  507. spinlock_t leds_lock; /* lock for leds */
  508. /* We can only have one operating interface (802.11 core)
  509. * at a time. General information about this interface follows.
  510. */
  511. struct ieee80211_vif *vif;
  512. /* MAC address (can be NULL). */
  513. u8 mac_addr[ETH_ALEN];
  514. /* Current BSSID (can be NULL). */
  515. u8 bssid[ETH_ALEN];
  516. /* Interface type. (IEEE80211_IF_TYPE_XXX) */
  517. int if_type;
  518. /* Is the card operating in AP, STA or IBSS mode? */
  519. bool operating;
  520. /* filter flags */
  521. unsigned int filter_flags;
  522. /* Stats about the wireless interface */
  523. struct ieee80211_low_level_stats ieee_stats;
  524. #ifdef CONFIG_B43LEGACY_HWRNG
  525. struct hwrng rng;
  526. u8 rng_initialized;
  527. char rng_name[30 + 1];
  528. #endif
  529. /* List of all wireless devices on this chip */
  530. struct list_head devlist;
  531. u8 nr_devs;
  532. bool radiotap_enabled;
  533. bool radio_enabled;
  534. /* The beacon we are currently using (AP or IBSS mode).
  535. * This beacon stuff is protected by the irq_lock. */
  536. struct sk_buff *current_beacon;
  537. bool beacon0_uploaded;
  538. bool beacon1_uploaded;
  539. bool beacon_templates_virgin; /* Never wrote the templates? */
  540. struct work_struct beacon_update_trigger;
  541. };
  542. /* Pointers to the firmware data and meta information about it. */
  543. struct b43legacy_firmware {
  544. /* Microcode */
  545. const struct firmware *ucode;
  546. /* PCM code */
  547. const struct firmware *pcm;
  548. /* Initial MMIO values for the firmware */
  549. const struct firmware *initvals;
  550. /* Initial MMIO values for the firmware, band-specific */
  551. const struct firmware *initvals_band;
  552. /* Firmware revision */
  553. u16 rev;
  554. /* Firmware patchlevel */
  555. u16 patch;
  556. };
  557. /* Device (802.11 core) initialization status. */
  558. enum {
  559. B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
  560. B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */
  561. B43legacy_STAT_STARTED = 2, /* Up and running. */
  562. };
  563. #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
  564. #define b43legacy_set_status(wldev, stat) do { \
  565. atomic_set(&(wldev)->__init_status, (stat)); \
  566. smp_wmb(); \
  567. } while (0)
  568. /* *** --- HOW LOCKING WORKS IN B43legacy --- ***
  569. *
  570. * You should always acquire both, wl->mutex and wl->irq_lock unless:
  571. * - You don't need to acquire wl->irq_lock, if the interface is stopped.
  572. * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
  573. * and packet TX path (and _ONLY_ there.)
  574. */
  575. /* Data structure for one wireless device (802.11 core) */
  576. struct b43legacy_wldev {
  577. struct ssb_device *dev;
  578. struct b43legacy_wl *wl;
  579. /* The device initialization status.
  580. * Use b43legacy_status() to query. */
  581. atomic_t __init_status;
  582. /* Saved init status for handling suspend. */
  583. int suspend_init_status;
  584. bool __using_pio; /* Using pio rather than dma. */
  585. bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
  586. bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */
  587. bool short_preamble; /* TRUE if using short preamble. */
  588. bool radio_hw_enable; /* State of radio hardware enable bit. */
  589. /* PHY/Radio device. */
  590. struct b43legacy_phy phy;
  591. union {
  592. /* DMA engines. */
  593. struct b43legacy_dma dma;
  594. /* PIO engines. */
  595. struct b43legacy_pio pio;
  596. };
  597. /* Various statistics about the physical device. */
  598. struct b43legacy_stats stats;
  599. /* The device LEDs. */
  600. struct b43legacy_led led_tx;
  601. struct b43legacy_led led_rx;
  602. struct b43legacy_led led_assoc;
  603. struct b43legacy_led led_radio;
  604. /* Reason code of the last interrupt. */
  605. u32 irq_reason;
  606. u32 dma_reason[6];
  607. /* The currently active generic-interrupt mask. */
  608. u32 irq_mask;
  609. /* Link Quality calculation context. */
  610. struct b43legacy_noise_calculation noisecalc;
  611. /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
  612. int mac_suspended;
  613. /* Interrupt Service Routine tasklet (bottom-half) */
  614. struct tasklet_struct isr_tasklet;
  615. /* Periodic tasks */
  616. struct delayed_work periodic_work;
  617. unsigned int periodic_state;
  618. struct work_struct restart_work;
  619. /* encryption/decryption */
  620. u16 ktp; /* Key table pointer */
  621. u8 max_nr_keys;
  622. struct b43legacy_key key[58];
  623. /* Firmware data */
  624. struct b43legacy_firmware fw;
  625. /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
  626. struct list_head list;
  627. /* Debugging stuff follows. */
  628. #ifdef CONFIG_B43LEGACY_DEBUG
  629. struct b43legacy_dfsentry *dfsentry;
  630. #endif
  631. };
  632. static inline
  633. struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
  634. {
  635. return hw->priv;
  636. }
  637. /* Helper function, which returns a boolean.
  638. * TRUE, if PIO is used; FALSE, if DMA is used.
  639. */
  640. #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  641. static inline
  642. int b43legacy_using_pio(struct b43legacy_wldev *dev)
  643. {
  644. return dev->__using_pio;
  645. }
  646. #elif defined(CONFIG_B43LEGACY_DMA)
  647. static inline
  648. int b43legacy_using_pio(struct b43legacy_wldev *dev)
  649. {
  650. return 0;
  651. }
  652. #elif defined(CONFIG_B43LEGACY_PIO)
  653. static inline
  654. int b43legacy_using_pio(struct b43legacy_wldev *dev)
  655. {
  656. return 1;
  657. }
  658. #else
  659. # error "Using neither DMA nor PIO? Confused..."
  660. #endif
  661. static inline
  662. struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
  663. {
  664. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  665. return ssb_get_drvdata(ssb_dev);
  666. }
  667. /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
  668. static inline
  669. int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
  670. {
  671. return (wl->operating &&
  672. wl->if_type == type);
  673. }
  674. static inline
  675. bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
  676. {
  677. return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
  678. }
  679. static inline
  680. u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
  681. {
  682. return ssb_read16(dev->dev, offset);
  683. }
  684. static inline
  685. void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
  686. {
  687. ssb_write16(dev->dev, offset, value);
  688. }
  689. static inline
  690. u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
  691. {
  692. return ssb_read32(dev->dev, offset);
  693. }
  694. static inline
  695. void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
  696. {
  697. ssb_write32(dev->dev, offset, value);
  698. }
  699. static inline
  700. struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
  701. u16 radio_attenuation,
  702. u16 baseband_attenuation)
  703. {
  704. return phy->_lo_pairs + (radio_attenuation
  705. + 14 * (baseband_attenuation / 2));
  706. }
  707. /* Message printing */
  708. void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
  709. __attribute__((format(printf, 2, 3)));
  710. void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
  711. __attribute__((format(printf, 2, 3)));
  712. void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
  713. __attribute__((format(printf, 2, 3)));
  714. #if B43legacy_DEBUG
  715. void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
  716. __attribute__((format(printf, 2, 3)));
  717. #else /* DEBUG */
  718. # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
  719. #endif /* DEBUG */
  720. /* Macros for printing a value in Q5.2 format */
  721. #define Q52_FMT "%u.%u"
  722. #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
  723. #endif /* B43legacy_H_ */