pio.c 20 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. PIO data transfer
  4. Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; see the file COPYING. If not, write to
  15. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  16. Boston, MA 02110-1301, USA.
  17. */
  18. #include "b43.h"
  19. #include "pio.h"
  20. #include "dma.h"
  21. #include "main.h"
  22. #include "xmit.h"
  23. #include <linux/delay.h>
  24. #include <linux/sched.h>
  25. static u16 generate_cookie(struct b43_pio_txqueue *q,
  26. struct b43_pio_txpacket *pack)
  27. {
  28. u16 cookie;
  29. /* Use the upper 4 bits of the cookie as
  30. * PIO controller ID and store the packet index number
  31. * in the lower 12 bits.
  32. * Note that the cookie must never be 0, as this
  33. * is a special value used in RX path.
  34. * It can also not be 0xFFFF because that is special
  35. * for multicast frames.
  36. */
  37. cookie = (((u16)q->index + 1) << 12);
  38. cookie |= pack->index;
  39. return cookie;
  40. }
  41. static
  42. struct b43_pio_txqueue *parse_cookie(struct b43_wldev *dev,
  43. u16 cookie,
  44. struct b43_pio_txpacket **pack)
  45. {
  46. struct b43_pio *pio = &dev->pio;
  47. struct b43_pio_txqueue *q = NULL;
  48. unsigned int pack_index;
  49. switch (cookie & 0xF000) {
  50. case 0x1000:
  51. q = pio->tx_queue_AC_BK;
  52. break;
  53. case 0x2000:
  54. q = pio->tx_queue_AC_BE;
  55. break;
  56. case 0x3000:
  57. q = pio->tx_queue_AC_VI;
  58. break;
  59. case 0x4000:
  60. q = pio->tx_queue_AC_VO;
  61. break;
  62. case 0x5000:
  63. q = pio->tx_queue_mcast;
  64. break;
  65. }
  66. if (B43_WARN_ON(!q))
  67. return NULL;
  68. pack_index = (cookie & 0x0FFF);
  69. if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets)))
  70. return NULL;
  71. *pack = &q->packets[pack_index];
  72. return q;
  73. }
  74. static u16 index_to_pioqueue_base(struct b43_wldev *dev,
  75. unsigned int index)
  76. {
  77. static const u16 bases[] = {
  78. B43_MMIO_PIO_BASE0,
  79. B43_MMIO_PIO_BASE1,
  80. B43_MMIO_PIO_BASE2,
  81. B43_MMIO_PIO_BASE3,
  82. B43_MMIO_PIO_BASE4,
  83. B43_MMIO_PIO_BASE5,
  84. B43_MMIO_PIO_BASE6,
  85. B43_MMIO_PIO_BASE7,
  86. };
  87. static const u16 bases_rev11[] = {
  88. B43_MMIO_PIO11_BASE0,
  89. B43_MMIO_PIO11_BASE1,
  90. B43_MMIO_PIO11_BASE2,
  91. B43_MMIO_PIO11_BASE3,
  92. B43_MMIO_PIO11_BASE4,
  93. B43_MMIO_PIO11_BASE5,
  94. };
  95. if (dev->dev->id.revision >= 11) {
  96. B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
  97. return bases_rev11[index];
  98. }
  99. B43_WARN_ON(index >= ARRAY_SIZE(bases));
  100. return bases[index];
  101. }
  102. static u16 pio_txqueue_offset(struct b43_wldev *dev)
  103. {
  104. if (dev->dev->id.revision >= 11)
  105. return 0x18;
  106. return 0;
  107. }
  108. static u16 pio_rxqueue_offset(struct b43_wldev *dev)
  109. {
  110. if (dev->dev->id.revision >= 11)
  111. return 0x38;
  112. return 8;
  113. }
  114. static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
  115. unsigned int index)
  116. {
  117. struct b43_pio_txqueue *q;
  118. struct b43_pio_txpacket *p;
  119. unsigned int i;
  120. q = kzalloc(sizeof(*q), GFP_KERNEL);
  121. if (!q)
  122. return NULL;
  123. q->dev = dev;
  124. q->rev = dev->dev->id.revision;
  125. q->mmio_base = index_to_pioqueue_base(dev, index) +
  126. pio_txqueue_offset(dev);
  127. q->index = index;
  128. q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS;
  129. if (q->rev >= 8) {
  130. q->buffer_size = 1920; //FIXME this constant is wrong.
  131. } else {
  132. q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE);
  133. q->buffer_size -= 80;
  134. }
  135. INIT_LIST_HEAD(&q->packets_list);
  136. for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
  137. p = &(q->packets[i]);
  138. INIT_LIST_HEAD(&p->list);
  139. p->index = i;
  140. p->queue = q;
  141. list_add(&p->list, &q->packets_list);
  142. }
  143. return q;
  144. }
  145. static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
  146. unsigned int index)
  147. {
  148. struct b43_pio_rxqueue *q;
  149. q = kzalloc(sizeof(*q), GFP_KERNEL);
  150. if (!q)
  151. return NULL;
  152. q->dev = dev;
  153. q->rev = dev->dev->id.revision;
  154. q->mmio_base = index_to_pioqueue_base(dev, index) +
  155. pio_rxqueue_offset(dev);
  156. /* Enable Direct FIFO RX (PIO) on the engine. */
  157. b43_dma_direct_fifo_rx(dev, index, 1);
  158. return q;
  159. }
  160. static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q)
  161. {
  162. struct b43_pio_txpacket *pack;
  163. unsigned int i;
  164. for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
  165. pack = &(q->packets[i]);
  166. if (pack->skb) {
  167. dev_kfree_skb_any(pack->skb);
  168. pack->skb = NULL;
  169. }
  170. }
  171. }
  172. static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q,
  173. const char *name)
  174. {
  175. if (!q)
  176. return;
  177. b43_pio_cancel_tx_packets(q);
  178. kfree(q);
  179. }
  180. static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q,
  181. const char *name)
  182. {
  183. if (!q)
  184. return;
  185. kfree(q);
  186. }
  187. #define destroy_queue_tx(pio, queue) do { \
  188. b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \
  189. (pio)->queue = NULL; \
  190. } while (0)
  191. #define destroy_queue_rx(pio, queue) do { \
  192. b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \
  193. (pio)->queue = NULL; \
  194. } while (0)
  195. void b43_pio_free(struct b43_wldev *dev)
  196. {
  197. struct b43_pio *pio;
  198. if (!b43_using_pio_transfers(dev))
  199. return;
  200. pio = &dev->pio;
  201. destroy_queue_rx(pio, rx_queue);
  202. destroy_queue_tx(pio, tx_queue_mcast);
  203. destroy_queue_tx(pio, tx_queue_AC_VO);
  204. destroy_queue_tx(pio, tx_queue_AC_VI);
  205. destroy_queue_tx(pio, tx_queue_AC_BE);
  206. destroy_queue_tx(pio, tx_queue_AC_BK);
  207. }
  208. int b43_pio_init(struct b43_wldev *dev)
  209. {
  210. struct b43_pio *pio = &dev->pio;
  211. int err = -ENOMEM;
  212. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  213. & ~B43_MACCTL_BE);
  214. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0);
  215. pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0);
  216. if (!pio->tx_queue_AC_BK)
  217. goto out;
  218. pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1);
  219. if (!pio->tx_queue_AC_BE)
  220. goto err_destroy_bk;
  221. pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2);
  222. if (!pio->tx_queue_AC_VI)
  223. goto err_destroy_be;
  224. pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3);
  225. if (!pio->tx_queue_AC_VO)
  226. goto err_destroy_vi;
  227. pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4);
  228. if (!pio->tx_queue_mcast)
  229. goto err_destroy_vo;
  230. pio->rx_queue = b43_setup_pioqueue_rx(dev, 0);
  231. if (!pio->rx_queue)
  232. goto err_destroy_mcast;
  233. b43dbg(dev->wl, "PIO initialized\n");
  234. err = 0;
  235. out:
  236. return err;
  237. err_destroy_mcast:
  238. destroy_queue_tx(pio, tx_queue_mcast);
  239. err_destroy_vo:
  240. destroy_queue_tx(pio, tx_queue_AC_VO);
  241. err_destroy_vi:
  242. destroy_queue_tx(pio, tx_queue_AC_VI);
  243. err_destroy_be:
  244. destroy_queue_tx(pio, tx_queue_AC_BE);
  245. err_destroy_bk:
  246. destroy_queue_tx(pio, tx_queue_AC_BK);
  247. return err;
  248. }
  249. /* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */
  250. static struct b43_pio_txqueue *select_queue_by_priority(struct b43_wldev *dev,
  251. u8 queue_prio)
  252. {
  253. struct b43_pio_txqueue *q;
  254. if (dev->qos_enabled) {
  255. /* 0 = highest priority */
  256. switch (queue_prio) {
  257. default:
  258. B43_WARN_ON(1);
  259. /* fallthrough */
  260. case 0:
  261. q = dev->pio.tx_queue_AC_VO;
  262. break;
  263. case 1:
  264. q = dev->pio.tx_queue_AC_VI;
  265. break;
  266. case 2:
  267. q = dev->pio.tx_queue_AC_BE;
  268. break;
  269. case 3:
  270. q = dev->pio.tx_queue_AC_BK;
  271. break;
  272. }
  273. } else
  274. q = dev->pio.tx_queue_AC_BE;
  275. return q;
  276. }
  277. static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q,
  278. u16 ctl,
  279. const void *_data,
  280. unsigned int data_len)
  281. {
  282. struct b43_wldev *dev = q->dev;
  283. struct b43_wl *wl = dev->wl;
  284. const u8 *data = _data;
  285. ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI;
  286. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  287. ssb_block_write(dev->dev, data, (data_len & ~1),
  288. q->mmio_base + B43_PIO_TXDATA,
  289. sizeof(u16));
  290. if (data_len & 1) {
  291. /* Write the last byte. */
  292. ctl &= ~B43_PIO_TXCTL_WRITEHI;
  293. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  294. wl->tx_tail[0] = data[data_len - 1];
  295. wl->tx_tail[1] = 0;
  296. ssb_block_write(dev->dev, wl->tx_tail, 2,
  297. q->mmio_base + B43_PIO_TXDATA,
  298. sizeof(u16));
  299. }
  300. return ctl;
  301. }
  302. static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack,
  303. const u8 *hdr, unsigned int hdrlen)
  304. {
  305. struct b43_pio_txqueue *q = pack->queue;
  306. const char *frame = pack->skb->data;
  307. unsigned int frame_len = pack->skb->len;
  308. u16 ctl;
  309. ctl = b43_piotx_read16(q, B43_PIO_TXCTL);
  310. ctl |= B43_PIO_TXCTL_FREADY;
  311. ctl &= ~B43_PIO_TXCTL_EOF;
  312. /* Transfer the header data. */
  313. ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen);
  314. /* Transfer the frame data. */
  315. ctl = tx_write_2byte_queue(q, ctl, frame, frame_len);
  316. ctl |= B43_PIO_TXCTL_EOF;
  317. b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
  318. }
  319. static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q,
  320. u32 ctl,
  321. const void *_data,
  322. unsigned int data_len)
  323. {
  324. struct b43_wldev *dev = q->dev;
  325. struct b43_wl *wl = dev->wl;
  326. const u8 *data = _data;
  327. ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 |
  328. B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31;
  329. b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
  330. ssb_block_write(dev->dev, data, (data_len & ~3),
  331. q->mmio_base + B43_PIO8_TXDATA,
  332. sizeof(u32));
  333. if (data_len & 3) {
  334. wl->tx_tail[3] = 0;
  335. /* Write the last few bytes. */
  336. ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 |
  337. B43_PIO8_TXCTL_24_31);
  338. switch (data_len & 3) {
  339. case 3:
  340. ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15;
  341. wl->tx_tail[0] = data[data_len - 3];
  342. wl->tx_tail[1] = data[data_len - 2];
  343. wl->tx_tail[2] = data[data_len - 1];
  344. break;
  345. case 2:
  346. ctl |= B43_PIO8_TXCTL_8_15;
  347. wl->tx_tail[0] = data[data_len - 2];
  348. wl->tx_tail[1] = data[data_len - 1];
  349. wl->tx_tail[2] = 0;
  350. break;
  351. case 1:
  352. wl->tx_tail[0] = data[data_len - 1];
  353. wl->tx_tail[1] = 0;
  354. wl->tx_tail[2] = 0;
  355. break;
  356. }
  357. b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
  358. ssb_block_write(dev->dev, wl->tx_tail, 4,
  359. q->mmio_base + B43_PIO8_TXDATA,
  360. sizeof(u32));
  361. }
  362. return ctl;
  363. }
  364. static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
  365. const u8 *hdr, unsigned int hdrlen)
  366. {
  367. struct b43_pio_txqueue *q = pack->queue;
  368. const char *frame = pack->skb->data;
  369. unsigned int frame_len = pack->skb->len;
  370. u32 ctl;
  371. ctl = b43_piotx_read32(q, B43_PIO8_TXCTL);
  372. ctl |= B43_PIO8_TXCTL_FREADY;
  373. ctl &= ~B43_PIO8_TXCTL_EOF;
  374. /* Transfer the header data. */
  375. ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen);
  376. /* Transfer the frame data. */
  377. ctl = tx_write_4byte_queue(q, ctl, frame, frame_len);
  378. ctl |= B43_PIO8_TXCTL_EOF;
  379. b43_piotx_write32(q, B43_PIO_TXCTL, ctl);
  380. }
  381. static int pio_tx_frame(struct b43_pio_txqueue *q,
  382. struct sk_buff *skb)
  383. {
  384. struct b43_wldev *dev = q->dev;
  385. struct b43_wl *wl = dev->wl;
  386. struct b43_pio_txpacket *pack;
  387. u16 cookie;
  388. int err;
  389. unsigned int hdrlen;
  390. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  391. B43_WARN_ON(list_empty(&q->packets_list));
  392. pack = list_entry(q->packets_list.next,
  393. struct b43_pio_txpacket, list);
  394. cookie = generate_cookie(q, pack);
  395. hdrlen = b43_txhdr_size(dev);
  396. err = b43_generate_txhdr(dev, (u8 *)&wl->txhdr, skb,
  397. info, cookie);
  398. if (err)
  399. return err;
  400. if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
  401. /* Tell the firmware about the cookie of the last
  402. * mcast frame, so it can clear the more-data bit in it. */
  403. b43_shm_write16(dev, B43_SHM_SHARED,
  404. B43_SHM_SH_MCASTCOOKIE, cookie);
  405. }
  406. pack->skb = skb;
  407. if (q->rev >= 8)
  408. pio_tx_frame_4byte_queue(pack, (const u8 *)&wl->txhdr, hdrlen);
  409. else
  410. pio_tx_frame_2byte_queue(pack, (const u8 *)&wl->txhdr, hdrlen);
  411. /* Remove it from the list of available packet slots.
  412. * It will be put back when we receive the status report. */
  413. list_del(&pack->list);
  414. /* Update the queue statistics. */
  415. q->buffer_used += roundup(skb->len + hdrlen, 4);
  416. q->free_packet_slots -= 1;
  417. return 0;
  418. }
  419. int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
  420. {
  421. struct b43_pio_txqueue *q;
  422. struct ieee80211_hdr *hdr;
  423. unsigned int hdrlen, total_len;
  424. int err = 0;
  425. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  426. hdr = (struct ieee80211_hdr *)skb->data;
  427. if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
  428. /* The multicast queue will be sent after the DTIM. */
  429. q = dev->pio.tx_queue_mcast;
  430. /* Set the frame More-Data bit. Ucode will clear it
  431. * for us on the last frame. */
  432. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
  433. } else {
  434. /* Decide by priority where to put this frame. */
  435. q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
  436. }
  437. hdrlen = b43_txhdr_size(dev);
  438. total_len = roundup(skb->len + hdrlen, 4);
  439. if (unlikely(total_len > q->buffer_size)) {
  440. err = -ENOBUFS;
  441. b43dbg(dev->wl, "PIO: TX packet longer than queue.\n");
  442. goto out;
  443. }
  444. if (unlikely(q->free_packet_slots == 0)) {
  445. err = -ENOBUFS;
  446. b43warn(dev->wl, "PIO: TX packet overflow.\n");
  447. goto out;
  448. }
  449. B43_WARN_ON(q->buffer_used > q->buffer_size);
  450. if (total_len > (q->buffer_size - q->buffer_used)) {
  451. /* Not enough memory on the queue. */
  452. err = -EBUSY;
  453. ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
  454. q->stopped = 1;
  455. goto out;
  456. }
  457. /* Assign the queue number to the ring (if not already done before)
  458. * so TX status handling can use it. The mac80211-queue to b43-queue
  459. * mapping is static, so we don't need to store it per frame. */
  460. q->queue_prio = skb_get_queue_mapping(skb);
  461. err = pio_tx_frame(q, skb);
  462. if (unlikely(err == -ENOKEY)) {
  463. /* Drop this packet, as we don't have the encryption key
  464. * anymore and must not transmit it unencrypted. */
  465. dev_kfree_skb_any(skb);
  466. err = 0;
  467. goto out;
  468. }
  469. if (unlikely(err)) {
  470. b43err(dev->wl, "PIO transmission failure\n");
  471. goto out;
  472. }
  473. q->nr_tx_packets++;
  474. B43_WARN_ON(q->buffer_used > q->buffer_size);
  475. if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
  476. (q->free_packet_slots == 0)) {
  477. /* The queue is full. */
  478. ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
  479. q->stopped = 1;
  480. }
  481. out:
  482. return err;
  483. }
  484. void b43_pio_handle_txstatus(struct b43_wldev *dev,
  485. const struct b43_txstatus *status)
  486. {
  487. struct b43_pio_txqueue *q;
  488. struct b43_pio_txpacket *pack = NULL;
  489. unsigned int total_len;
  490. struct ieee80211_tx_info *info;
  491. q = parse_cookie(dev, status->cookie, &pack);
  492. if (unlikely(!q))
  493. return;
  494. B43_WARN_ON(!pack);
  495. info = IEEE80211_SKB_CB(pack->skb);
  496. b43_fill_txstatus_report(dev, info, status);
  497. total_len = pack->skb->len + b43_txhdr_size(dev);
  498. total_len = roundup(total_len, 4);
  499. q->buffer_used -= total_len;
  500. q->free_packet_slots += 1;
  501. ieee80211_tx_status(dev->wl->hw, pack->skb);
  502. pack->skb = NULL;
  503. list_add(&pack->list, &q->packets_list);
  504. if (q->stopped) {
  505. ieee80211_wake_queue(dev->wl->hw, q->queue_prio);
  506. q->stopped = 0;
  507. }
  508. }
  509. void b43_pio_get_tx_stats(struct b43_wldev *dev,
  510. struct ieee80211_tx_queue_stats *stats)
  511. {
  512. const int nr_queues = dev->wl->hw->queues;
  513. struct b43_pio_txqueue *q;
  514. int i;
  515. for (i = 0; i < nr_queues; i++) {
  516. q = select_queue_by_priority(dev, i);
  517. stats[i].len = B43_PIO_MAX_NR_TXPACKETS - q->free_packet_slots;
  518. stats[i].limit = B43_PIO_MAX_NR_TXPACKETS;
  519. stats[i].count = q->nr_tx_packets;
  520. }
  521. }
  522. /* Returns whether we should fetch another frame. */
  523. static bool pio_rx_frame(struct b43_pio_rxqueue *q)
  524. {
  525. struct b43_wldev *dev = q->dev;
  526. struct b43_wl *wl = dev->wl;
  527. u16 len;
  528. u32 macstat;
  529. unsigned int i, padding;
  530. struct sk_buff *skb;
  531. const char *err_msg = NULL;
  532. memset(&wl->rxhdr, 0, sizeof(wl->rxhdr));
  533. /* Check if we have data and wait for it to get ready. */
  534. if (q->rev >= 8) {
  535. u32 ctl;
  536. ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
  537. if (!(ctl & B43_PIO8_RXCTL_FRAMERDY))
  538. return 0;
  539. b43_piorx_write32(q, B43_PIO8_RXCTL,
  540. B43_PIO8_RXCTL_FRAMERDY);
  541. for (i = 0; i < 10; i++) {
  542. ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
  543. if (ctl & B43_PIO8_RXCTL_DATARDY)
  544. goto data_ready;
  545. udelay(10);
  546. }
  547. } else {
  548. u16 ctl;
  549. ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
  550. if (!(ctl & B43_PIO_RXCTL_FRAMERDY))
  551. return 0;
  552. b43_piorx_write16(q, B43_PIO_RXCTL,
  553. B43_PIO_RXCTL_FRAMERDY);
  554. for (i = 0; i < 10; i++) {
  555. ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
  556. if (ctl & B43_PIO_RXCTL_DATARDY)
  557. goto data_ready;
  558. udelay(10);
  559. }
  560. }
  561. b43dbg(q->dev->wl, "PIO RX timed out\n");
  562. return 1;
  563. data_ready:
  564. /* Get the preamble (RX header) */
  565. if (q->rev >= 8) {
  566. ssb_block_read(dev->dev, &wl->rxhdr, sizeof(wl->rxhdr),
  567. q->mmio_base + B43_PIO8_RXDATA,
  568. sizeof(u32));
  569. } else {
  570. ssb_block_read(dev->dev, &wl->rxhdr, sizeof(wl->rxhdr),
  571. q->mmio_base + B43_PIO_RXDATA,
  572. sizeof(u16));
  573. }
  574. /* Sanity checks. */
  575. len = le16_to_cpu(wl->rxhdr.frame_len);
  576. if (unlikely(len > 0x700)) {
  577. err_msg = "len > 0x700";
  578. goto rx_error;
  579. }
  580. if (unlikely(len == 0)) {
  581. err_msg = "len == 0";
  582. goto rx_error;
  583. }
  584. macstat = le32_to_cpu(wl->rxhdr.mac_status);
  585. if (macstat & B43_RX_MAC_FCSERR) {
  586. if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) {
  587. /* Drop frames with failed FCS. */
  588. err_msg = "Frame FCS error";
  589. goto rx_error;
  590. }
  591. }
  592. /* We always pad 2 bytes, as that's what upstream code expects
  593. * due to the RX-header being 30 bytes. In case the frame is
  594. * unaligned, we pad another 2 bytes. */
  595. padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
  596. skb = dev_alloc_skb(len + padding + 2);
  597. if (unlikely(!skb)) {
  598. err_msg = "Out of memory";
  599. goto rx_error;
  600. }
  601. skb_reserve(skb, 2);
  602. skb_put(skb, len + padding);
  603. if (q->rev >= 8) {
  604. ssb_block_read(dev->dev, skb->data + padding, (len & ~3),
  605. q->mmio_base + B43_PIO8_RXDATA,
  606. sizeof(u32));
  607. if (len & 3) {
  608. /* Read the last few bytes. */
  609. ssb_block_read(dev->dev, wl->rx_tail, 4,
  610. q->mmio_base + B43_PIO8_RXDATA,
  611. sizeof(u32));
  612. switch (len & 3) {
  613. case 3:
  614. skb->data[len + padding - 3] = wl->rx_tail[0];
  615. skb->data[len + padding - 2] = wl->rx_tail[1];
  616. skb->data[len + padding - 1] = wl->rx_tail[2];
  617. break;
  618. case 2:
  619. skb->data[len + padding - 2] = wl->rx_tail[0];
  620. skb->data[len + padding - 1] = wl->rx_tail[1];
  621. break;
  622. case 1:
  623. skb->data[len + padding - 1] = wl->rx_tail[0];
  624. break;
  625. }
  626. }
  627. } else {
  628. ssb_block_read(dev->dev, skb->data + padding, (len & ~1),
  629. q->mmio_base + B43_PIO_RXDATA,
  630. sizeof(u16));
  631. if (len & 1) {
  632. /* Read the last byte. */
  633. ssb_block_read(dev->dev, wl->rx_tail, 2,
  634. q->mmio_base + B43_PIO_RXDATA,
  635. sizeof(u16));
  636. skb->data[len + padding - 1] = wl->rx_tail[0];
  637. }
  638. }
  639. b43_rx(q->dev, skb, &wl->rxhdr);
  640. return 1;
  641. rx_error:
  642. if (err_msg)
  643. b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg);
  644. b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY);
  645. return 1;
  646. }
  647. void b43_pio_rx(struct b43_pio_rxqueue *q)
  648. {
  649. unsigned int count = 0;
  650. bool stop;
  651. while (1) {
  652. stop = (pio_rx_frame(q) == 0);
  653. if (stop)
  654. break;
  655. cond_resched();
  656. if (WARN_ON_ONCE(++count > 10000))
  657. break;
  658. }
  659. }
  660. static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q)
  661. {
  662. if (q->rev >= 8) {
  663. b43_piotx_write32(q, B43_PIO8_TXCTL,
  664. b43_piotx_read32(q, B43_PIO8_TXCTL)
  665. | B43_PIO8_TXCTL_SUSPREQ);
  666. } else {
  667. b43_piotx_write16(q, B43_PIO_TXCTL,
  668. b43_piotx_read16(q, B43_PIO_TXCTL)
  669. | B43_PIO_TXCTL_SUSPREQ);
  670. }
  671. }
  672. static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q)
  673. {
  674. if (q->rev >= 8) {
  675. b43_piotx_write32(q, B43_PIO8_TXCTL,
  676. b43_piotx_read32(q, B43_PIO8_TXCTL)
  677. & ~B43_PIO8_TXCTL_SUSPREQ);
  678. } else {
  679. b43_piotx_write16(q, B43_PIO_TXCTL,
  680. b43_piotx_read16(q, B43_PIO_TXCTL)
  681. & ~B43_PIO_TXCTL_SUSPREQ);
  682. }
  683. }
  684. void b43_pio_tx_suspend(struct b43_wldev *dev)
  685. {
  686. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  687. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK);
  688. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE);
  689. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI);
  690. b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO);
  691. b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast);
  692. }
  693. void b43_pio_tx_resume(struct b43_wldev *dev)
  694. {
  695. b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast);
  696. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO);
  697. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI);
  698. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE);
  699. b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK);
  700. b43_power_saving_ctl_bits(dev, 0);
  701. }