btcoex.c 9.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340
  1. /*
  2. * Copyright (c) 2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "ath9k.h"
  17. static const struct ath_btcoex_config ath_bt_config = { 0, true, true,
  18. ATH_BT_COEX_MODE_SLOTTED, true, true, 2, 5, true };
  19. static const u16 ath_subsysid_tbl[] = {
  20. AR9280_COEX2WIRE_SUBSYSID,
  21. AT9285_COEX3WIRE_SA_SUBSYSID,
  22. AT9285_COEX3WIRE_DA_SUBSYSID
  23. };
  24. /*
  25. * Checks the subsystem id of the device to see if it
  26. * supports btcoex
  27. */
  28. bool ath_btcoex_supported(u16 subsysid)
  29. {
  30. int i;
  31. if (!subsysid)
  32. return false;
  33. for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
  34. if (subsysid == ath_subsysid_tbl[i])
  35. return true;
  36. return false;
  37. }
  38. /*
  39. * Detects if there is any priority bt traffic
  40. */
  41. static void ath_detect_bt_priority(struct ath_softc *sc)
  42. {
  43. struct ath_btcoex_info *btinfo = &sc->btcoex_info;
  44. if (ath9k_hw_gpio_get(sc->sc_ah, btinfo->btpriority_gpio))
  45. btinfo->bt_priority_cnt++;
  46. if (time_after(jiffies, btinfo->bt_priority_time +
  47. msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
  48. if (btinfo->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
  49. DPRINTF(sc, ATH_DBG_BTCOEX,
  50. "BT priority traffic detected");
  51. sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
  52. } else {
  53. sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
  54. }
  55. btinfo->bt_priority_cnt = 0;
  56. btinfo->bt_priority_time = jiffies;
  57. }
  58. }
  59. /*
  60. * Configures appropriate weight based on stomp type.
  61. */
  62. static void ath_btcoex_bt_stomp(struct ath_softc *sc,
  63. struct ath_btcoex_info *btinfo,
  64. int stomp_type)
  65. {
  66. switch (stomp_type) {
  67. case ATH_BTCOEX_STOMP_ALL:
  68. ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
  69. AR_STOMP_ALL_WLAN_WGHT);
  70. break;
  71. case ATH_BTCOEX_STOMP_LOW:
  72. ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
  73. AR_STOMP_LOW_WLAN_WGHT);
  74. break;
  75. case ATH_BTCOEX_STOMP_NONE:
  76. ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
  77. AR_STOMP_NONE_WLAN_WGHT);
  78. break;
  79. default:
  80. DPRINTF(sc, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
  81. break;
  82. }
  83. ath9k_hw_btcoex_enable(sc->sc_ah);
  84. }
  85. /*
  86. * This is the master bt coex timer which runs for every
  87. * 45ms, bt traffic will be given priority during 55% of this
  88. * period while wlan gets remaining 45%
  89. */
  90. static void ath_btcoex_period_timer(unsigned long data)
  91. {
  92. struct ath_softc *sc = (struct ath_softc *) data;
  93. struct ath_btcoex_info *btinfo = &sc->btcoex_info;
  94. ath_detect_bt_priority(sc);
  95. spin_lock_bh(&btinfo->btcoex_lock);
  96. ath_btcoex_bt_stomp(sc, btinfo, btinfo->bt_stomp_type);
  97. spin_unlock_bh(&btinfo->btcoex_lock);
  98. if (btinfo->btcoex_period != btinfo->btcoex_no_stomp) {
  99. if (btinfo->hw_timer_enabled)
  100. ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
  101. ath_gen_timer_start(sc->sc_ah,
  102. btinfo->no_stomp_timer,
  103. (ath9k_hw_gettsf32(sc->sc_ah) +
  104. btinfo->btcoex_no_stomp),
  105. btinfo->btcoex_no_stomp * 10);
  106. btinfo->hw_timer_enabled = true;
  107. }
  108. mod_timer(&btinfo->period_timer, jiffies +
  109. msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
  110. }
  111. /*
  112. * Generic tsf based hw timer which configures weight
  113. * registers to time slice between wlan and bt traffic
  114. */
  115. static void ath_btcoex_no_stomp_timer(void *arg)
  116. {
  117. struct ath_softc *sc = (struct ath_softc *)arg;
  118. struct ath_btcoex_info *btinfo = &sc->btcoex_info;
  119. DPRINTF(sc, ATH_DBG_BTCOEX, "no stomp timer running \n");
  120. spin_lock_bh(&btinfo->btcoex_lock);
  121. if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
  122. ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_NONE);
  123. else if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
  124. ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_LOW);
  125. spin_unlock_bh(&btinfo->btcoex_lock);
  126. }
  127. static int ath_init_btcoex_info(struct ath_hw *hw,
  128. struct ath_btcoex_info *btcoex_info)
  129. {
  130. u32 i;
  131. int qnum;
  132. qnum = ath_tx_get_qnum(hw->ah_sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
  133. btcoex_info->bt_coex_mode =
  134. (btcoex_info->bt_coex_mode & AR_BT_QCU_THRESH) |
  135. SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
  136. SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
  137. SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
  138. SM(ath_bt_config.bt_mode, AR_BT_MODE) |
  139. SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
  140. SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
  141. SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
  142. SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
  143. SM(qnum, AR_BT_QCU_THRESH);
  144. btcoex_info->bt_coex_mode2 =
  145. SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
  146. SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
  147. AR_BT_DISABLE_BT_ANT;
  148. btcoex_info->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  149. btcoex_info->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
  150. btcoex_info->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
  151. btcoex_info->btcoex_period / 100;
  152. for (i = 0; i < 32; i++)
  153. hw->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
  154. setup_timer(&btcoex_info->period_timer, ath_btcoex_period_timer,
  155. (unsigned long) hw->ah_sc);
  156. btcoex_info->no_stomp_timer = ath_gen_timer_alloc(hw,
  157. ath_btcoex_no_stomp_timer,
  158. ath_btcoex_no_stomp_timer,
  159. (void *)hw->ah_sc, AR_FIRST_NDP_TIMER);
  160. if (btcoex_info->no_stomp_timer == NULL)
  161. return -ENOMEM;
  162. spin_lock_init(&btcoex_info->btcoex_lock);
  163. return 0;
  164. }
  165. int ath9k_hw_btcoex_init(struct ath_hw *ah)
  166. {
  167. struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
  168. int ret = 0;
  169. if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
  170. /* connect bt_active to baseband */
  171. REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
  172. (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
  173. AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
  174. REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
  175. AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
  176. /* Set input mux for bt_active to gpio pin */
  177. REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
  178. AR_GPIO_INPUT_MUX1_BT_ACTIVE,
  179. btcoex_info->btactive_gpio);
  180. /* Configure the desired gpio port for input */
  181. ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
  182. } else {
  183. /* btcoex 3-wire */
  184. REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
  185. (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
  186. AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
  187. /* Set input mux for bt_prority_async and
  188. * bt_active_async to GPIO pins */
  189. REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
  190. AR_GPIO_INPUT_MUX1_BT_ACTIVE,
  191. btcoex_info->btactive_gpio);
  192. REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
  193. AR_GPIO_INPUT_MUX1_BT_PRIORITY,
  194. btcoex_info->btpriority_gpio);
  195. /* Configure the desired GPIO ports for input */
  196. ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
  197. ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio);
  198. ret = ath_init_btcoex_info(ah, btcoex_info);
  199. }
  200. return ret;
  201. }
  202. void ath9k_hw_btcoex_enable(struct ath_hw *ah)
  203. {
  204. struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
  205. if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
  206. /* Configure the desired GPIO port for TX_FRAME output */
  207. ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
  208. AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
  209. } else {
  210. /*
  211. * Program coex mode and weight registers to
  212. * enable coex 3-wire
  213. */
  214. REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_info->bt_coex_mode);
  215. REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_info->bt_coex_weights);
  216. REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_info->bt_coex_mode2);
  217. REG_RMW_FIELD(ah, AR_QUIET1,
  218. AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
  219. REG_RMW_FIELD(ah, AR_PCU_MISC,
  220. AR_PCU_BT_ANT_PREVENT_RX, 0);
  221. ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
  222. AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
  223. }
  224. REG_RMW(ah, AR_GPIO_PDPU,
  225. (0x2 << (btcoex_info->btactive_gpio * 2)),
  226. (0x3 << (btcoex_info->btactive_gpio * 2)));
  227. ah->ah_sc->sc_flags |= SC_OP_BTCOEX_ENABLED;
  228. }
  229. void ath9k_hw_btcoex_disable(struct ath_hw *ah)
  230. {
  231. struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
  232. ath9k_hw_set_gpio(ah, btcoex_info->wlanactive_gpio, 0);
  233. ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
  234. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  235. if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) {
  236. REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
  237. REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
  238. REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
  239. }
  240. ah->ah_sc->sc_flags &= ~SC_OP_BTCOEX_ENABLED;
  241. }
  242. /*
  243. * Pause btcoex timer and bt duty cycle timer
  244. */
  245. void ath_btcoex_timer_pause(struct ath_softc *sc,
  246. struct ath_btcoex_info *btinfo)
  247. {
  248. del_timer_sync(&btinfo->period_timer);
  249. if (btinfo->hw_timer_enabled)
  250. ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
  251. btinfo->hw_timer_enabled = false;
  252. }
  253. /*
  254. * (Re)start btcoex timers
  255. */
  256. void ath_btcoex_timer_resume(struct ath_softc *sc,
  257. struct ath_btcoex_info *btinfo)
  258. {
  259. DPRINTF(sc, ATH_DBG_BTCOEX, "Starting btcoex timers");
  260. /* make sure duty cycle timer is also stopped when resuming */
  261. if (btinfo->hw_timer_enabled)
  262. ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
  263. btinfo->bt_priority_cnt = 0;
  264. btinfo->bt_priority_time = jiffies;
  265. sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
  266. mod_timer(&btinfo->period_timer, jiffies);
  267. }