lmc_main.c 62 KB

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  1. /*
  2. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  3. * All rights reserved. www.lanmedia.com
  4. * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
  5. *
  6. * This code is written by:
  7. * Andrew Stanley-Jones (asj@cban.com)
  8. * Rob Braun (bbraun@vix.com),
  9. * Michael Graff (explorer@vix.com) and
  10. * Matt Thomas (matt@3am-software.com).
  11. *
  12. * With Help By:
  13. * David Boggs
  14. * Ron Crane
  15. * Alan Cox
  16. *
  17. * This software may be used and distributed according to the terms
  18. * of the GNU General Public License version 2, incorporated herein by reference.
  19. *
  20. * Driver for the LanMedia LMC5200, LMC5245, LMC1000, LMC1200 cards.
  21. *
  22. * To control link specific options lmcctl is required.
  23. * It can be obtained from ftp.lanmedia.com.
  24. *
  25. * Linux driver notes:
  26. * Linux uses the device struct lmc_private to pass private information
  27. * arround.
  28. *
  29. * The initialization portion of this driver (the lmc_reset() and the
  30. * lmc_dec_reset() functions, as well as the led controls and the
  31. * lmc_initcsrs() functions.
  32. *
  33. * The watchdog function runs every second and checks to see if
  34. * we still have link, and that the timing source is what we expected
  35. * it to be. If link is lost, the interface is marked down, and
  36. * we no longer can transmit.
  37. *
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/ptrace.h>
  44. #include <linux/errno.h>
  45. #include <linux/ioport.h>
  46. #include <linux/slab.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/delay.h>
  50. #include <linux/hdlc.h>
  51. #include <linux/init.h>
  52. #include <linux/in.h>
  53. #include <linux/if_arp.h>
  54. #include <linux/netdevice.h>
  55. #include <linux/etherdevice.h>
  56. #include <linux/skbuff.h>
  57. #include <linux/inet.h>
  58. #include <linux/bitops.h>
  59. #include <asm/processor.h> /* Processor type for cache alignment. */
  60. #include <asm/io.h>
  61. #include <asm/dma.h>
  62. #include <asm/uaccess.h>
  63. //#include <asm/spinlock.h>
  64. #define DRIVER_MAJOR_VERSION 1
  65. #define DRIVER_MINOR_VERSION 34
  66. #define DRIVER_SUB_VERSION 0
  67. #define DRIVER_VERSION ((DRIVER_MAJOR_VERSION << 8) + DRIVER_MINOR_VERSION)
  68. #include "lmc.h"
  69. #include "lmc_var.h"
  70. #include "lmc_ioctl.h"
  71. #include "lmc_debug.h"
  72. #include "lmc_proto.h"
  73. static int LMC_PKT_BUF_SZ = 1542;
  74. static struct pci_device_id lmc_pci_tbl[] = {
  75. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  76. PCI_VENDOR_ID_LMC, PCI_ANY_ID },
  77. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  78. PCI_ANY_ID, PCI_VENDOR_ID_LMC },
  79. { 0 }
  80. };
  81. MODULE_DEVICE_TABLE(pci, lmc_pci_tbl);
  82. MODULE_LICENSE("GPL v2");
  83. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  84. struct net_device *dev);
  85. static int lmc_rx (struct net_device *dev);
  86. static int lmc_open(struct net_device *dev);
  87. static int lmc_close(struct net_device *dev);
  88. static struct net_device_stats *lmc_get_stats(struct net_device *dev);
  89. static irqreturn_t lmc_interrupt(int irq, void *dev_instance);
  90. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
  91. static void lmc_softreset(lmc_softc_t * const);
  92. static void lmc_running_reset(struct net_device *dev);
  93. static int lmc_ifdown(struct net_device * const);
  94. static void lmc_watchdog(unsigned long data);
  95. static void lmc_reset(lmc_softc_t * const sc);
  96. static void lmc_dec_reset(lmc_softc_t * const sc);
  97. static void lmc_driver_timeout(struct net_device *dev);
  98. /*
  99. * linux reserves 16 device specific IOCTLs. We call them
  100. * LMCIOC* to control various bits of our world.
  101. */
  102. int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/
  103. {
  104. lmc_softc_t *sc = dev_to_sc(dev);
  105. lmc_ctl_t ctl;
  106. int ret = -EOPNOTSUPP;
  107. u16 regVal;
  108. unsigned long flags;
  109. lmc_trace(dev, "lmc_ioctl in");
  110. /*
  111. * Most functions mess with the structure
  112. * Disable interrupts while we do the polling
  113. */
  114. switch (cmd) {
  115. /*
  116. * Return current driver state. Since we keep this up
  117. * To date internally, just copy this out to the user.
  118. */
  119. case LMCIOCGINFO: /*fold01*/
  120. if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
  121. ret = -EFAULT;
  122. else
  123. ret = 0;
  124. break;
  125. case LMCIOCSINFO: /*fold01*/
  126. if (!capable(CAP_NET_ADMIN)) {
  127. ret = -EPERM;
  128. break;
  129. }
  130. if(dev->flags & IFF_UP){
  131. ret = -EBUSY;
  132. break;
  133. }
  134. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  135. ret = -EFAULT;
  136. break;
  137. }
  138. spin_lock_irqsave(&sc->lmc_lock, flags);
  139. sc->lmc_media->set_status (sc, &ctl);
  140. if(ctl.crc_length != sc->ictl.crc_length) {
  141. sc->lmc_media->set_crc_length(sc, ctl.crc_length);
  142. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
  143. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  144. else
  145. sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
  146. }
  147. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  148. ret = 0;
  149. break;
  150. case LMCIOCIFTYPE: /*fold01*/
  151. {
  152. u16 old_type = sc->if_type;
  153. u16 new_type;
  154. if (!capable(CAP_NET_ADMIN)) {
  155. ret = -EPERM;
  156. break;
  157. }
  158. if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
  159. ret = -EFAULT;
  160. break;
  161. }
  162. if (new_type == old_type)
  163. {
  164. ret = 0 ;
  165. break; /* no change */
  166. }
  167. spin_lock_irqsave(&sc->lmc_lock, flags);
  168. lmc_proto_close(sc);
  169. sc->if_type = new_type;
  170. lmc_proto_attach(sc);
  171. ret = lmc_proto_open(sc);
  172. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  173. break;
  174. }
  175. case LMCIOCGETXINFO: /*fold01*/
  176. spin_lock_irqsave(&sc->lmc_lock, flags);
  177. sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
  178. sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
  179. sc->lmc_xinfo.PciSlotNumber = 0;
  180. sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
  181. sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
  182. sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
  183. sc->lmc_xinfo.XilinxRevisionNumber =
  184. lmc_mii_readreg (sc, 0, 3) & 0xf;
  185. sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
  186. sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
  187. sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
  188. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  189. sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
  190. if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
  191. sizeof(struct lmc_xinfo)))
  192. ret = -EFAULT;
  193. else
  194. ret = 0;
  195. break;
  196. case LMCIOCGETLMCSTATS:
  197. spin_lock_irqsave(&sc->lmc_lock, flags);
  198. if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
  199. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
  200. sc->extra_stats.framingBitErrorCount +=
  201. lmc_mii_readreg(sc, 0, 18) & 0xff;
  202. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
  203. sc->extra_stats.framingBitErrorCount +=
  204. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  205. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
  206. sc->extra_stats.lineCodeViolationCount +=
  207. lmc_mii_readreg(sc, 0, 18) & 0xff;
  208. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
  209. sc->extra_stats.lineCodeViolationCount +=
  210. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  211. lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
  212. regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
  213. sc->extra_stats.lossOfFrameCount +=
  214. (regVal & T1FRAMER_LOF_MASK) >> 4;
  215. sc->extra_stats.changeOfFrameAlignmentCount +=
  216. (regVal & T1FRAMER_COFA_MASK) >> 2;
  217. sc->extra_stats.severelyErroredFrameCount +=
  218. regVal & T1FRAMER_SEF_MASK;
  219. }
  220. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  221. if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
  222. sizeof(sc->lmc_device->stats)) ||
  223. copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
  224. &sc->extra_stats, sizeof(sc->extra_stats)))
  225. ret = -EFAULT;
  226. else
  227. ret = 0;
  228. break;
  229. case LMCIOCCLEARLMCSTATS:
  230. if (!capable(CAP_NET_ADMIN)) {
  231. ret = -EPERM;
  232. break;
  233. }
  234. spin_lock_irqsave(&sc->lmc_lock, flags);
  235. memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
  236. memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
  237. sc->extra_stats.check = STATCHECK;
  238. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  239. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  240. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  241. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  242. ret = 0;
  243. break;
  244. case LMCIOCSETCIRCUIT: /*fold01*/
  245. if (!capable(CAP_NET_ADMIN)){
  246. ret = -EPERM;
  247. break;
  248. }
  249. if(dev->flags & IFF_UP){
  250. ret = -EBUSY;
  251. break;
  252. }
  253. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  254. ret = -EFAULT;
  255. break;
  256. }
  257. spin_lock_irqsave(&sc->lmc_lock, flags);
  258. sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
  259. sc->ictl.circuit_type = ctl.circuit_type;
  260. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  261. ret = 0;
  262. break;
  263. case LMCIOCRESET: /*fold01*/
  264. if (!capable(CAP_NET_ADMIN)){
  265. ret = -EPERM;
  266. break;
  267. }
  268. spin_lock_irqsave(&sc->lmc_lock, flags);
  269. /* Reset driver and bring back to current state */
  270. printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  271. lmc_running_reset (dev);
  272. printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  273. LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  274. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  275. ret = 0;
  276. break;
  277. #ifdef DEBUG
  278. case LMCIOCDUMPEVENTLOG:
  279. if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
  280. ret = -EFAULT;
  281. break;
  282. }
  283. if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
  284. sizeof(lmcEventLogBuf)))
  285. ret = -EFAULT;
  286. else
  287. ret = 0;
  288. break;
  289. #endif /* end ifdef _DBG_EVENTLOG */
  290. case LMCIOCT1CONTROL: /*fold01*/
  291. if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
  292. ret = -EOPNOTSUPP;
  293. break;
  294. }
  295. break;
  296. case LMCIOCXILINX: /*fold01*/
  297. {
  298. struct lmc_xilinx_control xc; /*fold02*/
  299. if (!capable(CAP_NET_ADMIN)){
  300. ret = -EPERM;
  301. break;
  302. }
  303. /*
  304. * Stop the xwitter whlie we restart the hardware
  305. */
  306. netif_stop_queue(dev);
  307. if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
  308. ret = -EFAULT;
  309. break;
  310. }
  311. switch(xc.command){
  312. case lmc_xilinx_reset: /*fold02*/
  313. {
  314. u16 mii;
  315. spin_lock_irqsave(&sc->lmc_lock, flags);
  316. mii = lmc_mii_readreg (sc, 0, 16);
  317. /*
  318. * Make all of them 0 and make input
  319. */
  320. lmc_gpio_mkinput(sc, 0xff);
  321. /*
  322. * make the reset output
  323. */
  324. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  325. /*
  326. * RESET low to force configuration. This also forces
  327. * the transmitter clock to be internal, but we expect to reset
  328. * that later anyway.
  329. */
  330. sc->lmc_gpio &= ~LMC_GEP_RESET;
  331. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  332. /*
  333. * hold for more than 10 microseconds
  334. */
  335. udelay(50);
  336. sc->lmc_gpio |= LMC_GEP_RESET;
  337. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  338. /*
  339. * stop driving Xilinx-related signals
  340. */
  341. lmc_gpio_mkinput(sc, 0xff);
  342. /* Reset the frammer hardware */
  343. sc->lmc_media->set_link_status (sc, 1);
  344. sc->lmc_media->set_status (sc, NULL);
  345. // lmc_softreset(sc);
  346. {
  347. int i;
  348. for(i = 0; i < 5; i++){
  349. lmc_led_on(sc, LMC_DS3_LED0);
  350. mdelay(100);
  351. lmc_led_off(sc, LMC_DS3_LED0);
  352. lmc_led_on(sc, LMC_DS3_LED1);
  353. mdelay(100);
  354. lmc_led_off(sc, LMC_DS3_LED1);
  355. lmc_led_on(sc, LMC_DS3_LED3);
  356. mdelay(100);
  357. lmc_led_off(sc, LMC_DS3_LED3);
  358. lmc_led_on(sc, LMC_DS3_LED2);
  359. mdelay(100);
  360. lmc_led_off(sc, LMC_DS3_LED2);
  361. }
  362. }
  363. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  364. ret = 0x0;
  365. }
  366. break;
  367. case lmc_xilinx_load_prom: /*fold02*/
  368. {
  369. u16 mii;
  370. int timeout = 500000;
  371. spin_lock_irqsave(&sc->lmc_lock, flags);
  372. mii = lmc_mii_readreg (sc, 0, 16);
  373. /*
  374. * Make all of them 0 and make input
  375. */
  376. lmc_gpio_mkinput(sc, 0xff);
  377. /*
  378. * make the reset output
  379. */
  380. lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  381. /*
  382. * RESET low to force configuration. This also forces
  383. * the transmitter clock to be internal, but we expect to reset
  384. * that later anyway.
  385. */
  386. sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
  387. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  388. /*
  389. * hold for more than 10 microseconds
  390. */
  391. udelay(50);
  392. sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
  393. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  394. /*
  395. * busy wait for the chip to reset
  396. */
  397. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  398. (timeout-- > 0))
  399. cpu_relax();
  400. /*
  401. * stop driving Xilinx-related signals
  402. */
  403. lmc_gpio_mkinput(sc, 0xff);
  404. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  405. ret = 0x0;
  406. break;
  407. }
  408. case lmc_xilinx_load: /*fold02*/
  409. {
  410. char *data;
  411. int pos;
  412. int timeout = 500000;
  413. if (!xc.data) {
  414. ret = -EINVAL;
  415. break;
  416. }
  417. data = kmalloc(xc.len, GFP_KERNEL);
  418. if (!data) {
  419. printk(KERN_WARNING "%s: Failed to allocate memory for copy\n", dev->name);
  420. ret = -ENOMEM;
  421. break;
  422. }
  423. if(copy_from_user(data, xc.data, xc.len))
  424. {
  425. kfree(data);
  426. ret = -ENOMEM;
  427. break;
  428. }
  429. printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
  430. spin_lock_irqsave(&sc->lmc_lock, flags);
  431. lmc_gpio_mkinput(sc, 0xff);
  432. /*
  433. * Clear the Xilinx and start prgramming from the DEC
  434. */
  435. /*
  436. * Set ouput as:
  437. * Reset: 0 (active)
  438. * DP: 0 (active)
  439. * Mode: 1
  440. *
  441. */
  442. sc->lmc_gpio = 0x00;
  443. sc->lmc_gpio &= ~LMC_GEP_DP;
  444. sc->lmc_gpio &= ~LMC_GEP_RESET;
  445. sc->lmc_gpio |= LMC_GEP_MODE;
  446. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  447. lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
  448. /*
  449. * Wait at least 10 us 20 to be safe
  450. */
  451. udelay(50);
  452. /*
  453. * Clear reset and activate programming lines
  454. * Reset: Input
  455. * DP: Input
  456. * Clock: Output
  457. * Data: Output
  458. * Mode: Output
  459. */
  460. lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  461. /*
  462. * Set LOAD, DATA, Clock to 1
  463. */
  464. sc->lmc_gpio = 0x00;
  465. sc->lmc_gpio |= LMC_GEP_MODE;
  466. sc->lmc_gpio |= LMC_GEP_DATA;
  467. sc->lmc_gpio |= LMC_GEP_CLK;
  468. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  469. lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
  470. /*
  471. * busy wait for the chip to reset
  472. */
  473. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  474. (timeout-- > 0))
  475. cpu_relax();
  476. printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
  477. for(pos = 0; pos < xc.len; pos++){
  478. switch(data[pos]){
  479. case 0:
  480. sc->lmc_gpio &= ~LMC_GEP_DATA; /* Data is 0 */
  481. break;
  482. case 1:
  483. sc->lmc_gpio |= LMC_GEP_DATA; /* Data is 1 */
  484. break;
  485. default:
  486. printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
  487. sc->lmc_gpio |= LMC_GEP_DATA; /* Assume it's 1 */
  488. }
  489. sc->lmc_gpio &= ~LMC_GEP_CLK; /* Clock to zero */
  490. sc->lmc_gpio |= LMC_GEP_MODE;
  491. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  492. udelay(1);
  493. sc->lmc_gpio |= LMC_GEP_CLK; /* Put the clack back to one */
  494. sc->lmc_gpio |= LMC_GEP_MODE;
  495. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  496. udelay(1);
  497. }
  498. if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
  499. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
  500. }
  501. else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
  502. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
  503. }
  504. else {
  505. printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
  506. }
  507. lmc_gpio_mkinput(sc, 0xff);
  508. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  509. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  510. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  511. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  512. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  513. kfree(data);
  514. ret = 0;
  515. break;
  516. }
  517. default: /*fold02*/
  518. ret = -EBADE;
  519. break;
  520. }
  521. netif_wake_queue(dev);
  522. sc->lmc_txfull = 0;
  523. }
  524. break;
  525. default: /*fold01*/
  526. /* If we don't know what to do, give the protocol a shot. */
  527. ret = lmc_proto_ioctl (sc, ifr, cmd);
  528. break;
  529. }
  530. lmc_trace(dev, "lmc_ioctl out");
  531. return ret;
  532. }
  533. /* the watchdog process that cruises around */
  534. static void lmc_watchdog (unsigned long data) /*fold00*/
  535. {
  536. struct net_device *dev = (struct net_device *)data;
  537. lmc_softc_t *sc = dev_to_sc(dev);
  538. int link_status;
  539. u32 ticks;
  540. unsigned long flags;
  541. lmc_trace(dev, "lmc_watchdog in");
  542. spin_lock_irqsave(&sc->lmc_lock, flags);
  543. if(sc->check != 0xBEAFCAFE){
  544. printk("LMC: Corrupt net_device struct, breaking out\n");
  545. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  546. return;
  547. }
  548. /* Make sure the tx jabber and rx watchdog are off,
  549. * and the transmit and receive processes are running.
  550. */
  551. LMC_CSR_WRITE (sc, csr_15, 0x00000011);
  552. sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN;
  553. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  554. if (sc->lmc_ok == 0)
  555. goto kick_timer;
  556. LMC_EVENT_LOG(LMC_EVENT_WATCHDOG, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  557. /* --- begin time out check -----------------------------------
  558. * check for a transmit interrupt timeout
  559. * Has the packet xmt vs xmt serviced threshold been exceeded */
  560. if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  561. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  562. sc->tx_TimeoutInd == 0)
  563. {
  564. /* wait for the watchdog to come around again */
  565. sc->tx_TimeoutInd = 1;
  566. }
  567. else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  568. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  569. sc->tx_TimeoutInd)
  570. {
  571. LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0);
  572. sc->tx_TimeoutDisplay = 1;
  573. sc->extra_stats.tx_TimeoutCnt++;
  574. /* DEC chip is stuck, hit it with a RESET!!!! */
  575. lmc_running_reset (dev);
  576. /* look at receive & transmit process state to make sure they are running */
  577. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  578. /* look at: DSR - 02 for Reg 16
  579. * CTS - 08
  580. * DCD - 10
  581. * RI - 20
  582. * for Reg 17
  583. */
  584. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg (sc, 0, 16), lmc_mii_readreg (sc, 0, 17));
  585. /* reset the transmit timeout detection flag */
  586. sc->tx_TimeoutInd = 0;
  587. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  588. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  589. } else {
  590. sc->tx_TimeoutInd = 0;
  591. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  592. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  593. }
  594. /* --- end time out check ----------------------------------- */
  595. link_status = sc->lmc_media->get_link_status (sc);
  596. /*
  597. * hardware level link lost, but the interface is marked as up.
  598. * Mark it as down.
  599. */
  600. if ((link_status == 0) && (sc->last_link_status != 0)) {
  601. printk(KERN_WARNING "%s: hardware/physical link down\n", dev->name);
  602. sc->last_link_status = 0;
  603. /* lmc_reset (sc); Why reset??? The link can go down ok */
  604. /* Inform the world that link has been lost */
  605. netif_carrier_off(dev);
  606. }
  607. /*
  608. * hardware link is up, but the interface is marked as down.
  609. * Bring it back up again.
  610. */
  611. if (link_status != 0 && sc->last_link_status == 0) {
  612. printk(KERN_WARNING "%s: hardware/physical link up\n", dev->name);
  613. sc->last_link_status = 1;
  614. /* lmc_reset (sc); Again why reset??? */
  615. netif_carrier_on(dev);
  616. }
  617. /* Call media specific watchdog functions */
  618. sc->lmc_media->watchdog(sc);
  619. /*
  620. * Poke the transmitter to make sure it
  621. * never stops, even if we run out of mem
  622. */
  623. LMC_CSR_WRITE(sc, csr_rxpoll, 0);
  624. /*
  625. * Check for code that failed
  626. * and try and fix it as appropriate
  627. */
  628. if(sc->failed_ring == 1){
  629. /*
  630. * Failed to setup the recv/xmit rin
  631. * Try again
  632. */
  633. sc->failed_ring = 0;
  634. lmc_softreset(sc);
  635. }
  636. if(sc->failed_recv_alloc == 1){
  637. /*
  638. * We failed to alloc mem in the
  639. * interrupt handler, go through the rings
  640. * and rebuild them
  641. */
  642. sc->failed_recv_alloc = 0;
  643. lmc_softreset(sc);
  644. }
  645. /*
  646. * remember the timer value
  647. */
  648. kick_timer:
  649. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  650. LMC_CSR_WRITE (sc, csr_gp_timer, 0xffffffffUL);
  651. sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff);
  652. /*
  653. * restart this timer.
  654. */
  655. sc->timer.expires = jiffies + (HZ);
  656. add_timer (&sc->timer);
  657. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  658. lmc_trace(dev, "lmc_watchdog out");
  659. }
  660. static int lmc_attach(struct net_device *dev, unsigned short encoding,
  661. unsigned short parity)
  662. {
  663. if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
  664. return 0;
  665. return -EINVAL;
  666. }
  667. static const struct net_device_ops lmc_ops = {
  668. .ndo_open = lmc_open,
  669. .ndo_stop = lmc_close,
  670. .ndo_change_mtu = hdlc_change_mtu,
  671. .ndo_start_xmit = hdlc_start_xmit,
  672. .ndo_do_ioctl = lmc_ioctl,
  673. .ndo_tx_timeout = lmc_driver_timeout,
  674. .ndo_get_stats = lmc_get_stats,
  675. };
  676. static int __devinit lmc_init_one(struct pci_dev *pdev,
  677. const struct pci_device_id *ent)
  678. {
  679. lmc_softc_t *sc;
  680. struct net_device *dev;
  681. u16 subdevice;
  682. u16 AdapModelNum;
  683. int err;
  684. static int cards_found;
  685. /* lmc_trace(dev, "lmc_init_one in"); */
  686. err = pci_enable_device(pdev);
  687. if (err) {
  688. printk(KERN_ERR "lmc: pci enable failed: %d\n", err);
  689. return err;
  690. }
  691. err = pci_request_regions(pdev, "lmc");
  692. if (err) {
  693. printk(KERN_ERR "lmc: pci_request_region failed\n");
  694. goto err_req_io;
  695. }
  696. /*
  697. * Allocate our own device structure
  698. */
  699. sc = kzalloc(sizeof(lmc_softc_t), GFP_KERNEL);
  700. if (!sc) {
  701. err = -ENOMEM;
  702. goto err_kzalloc;
  703. }
  704. dev = alloc_hdlcdev(sc);
  705. if (!dev) {
  706. printk(KERN_ERR "lmc:alloc_netdev for device failed\n");
  707. goto err_hdlcdev;
  708. }
  709. dev->type = ARPHRD_HDLC;
  710. dev_to_hdlc(dev)->xmit = lmc_start_xmit;
  711. dev_to_hdlc(dev)->attach = lmc_attach;
  712. dev->netdev_ops = &lmc_ops;
  713. dev->watchdog_timeo = HZ; /* 1 second */
  714. dev->tx_queue_len = 100;
  715. sc->lmc_device = dev;
  716. sc->name = dev->name;
  717. sc->if_type = LMC_PPP;
  718. sc->check = 0xBEAFCAFE;
  719. dev->base_addr = pci_resource_start(pdev, 0);
  720. dev->irq = pdev->irq;
  721. pci_set_drvdata(pdev, dev);
  722. SET_NETDEV_DEV(dev, &pdev->dev);
  723. /*
  724. * This will get the protocol layer ready and do any 1 time init's
  725. * Must have a valid sc and dev structure
  726. */
  727. lmc_proto_attach(sc);
  728. /* Init the spin lock so can call it latter */
  729. spin_lock_init(&sc->lmc_lock);
  730. pci_set_master(pdev);
  731. printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name,
  732. dev->base_addr, dev->irq);
  733. err = register_hdlc_device(dev);
  734. if (err) {
  735. printk(KERN_ERR "%s: register_netdev failed.\n", dev->name);
  736. free_netdev(dev);
  737. goto err_hdlcdev;
  738. }
  739. sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN;
  740. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  741. /*
  742. *
  743. * Check either the subvendor or the subdevice, some systems reverse
  744. * the setting in the bois, seems to be version and arch dependent?
  745. * Fix the error, exchange the two values
  746. */
  747. if ((subdevice = pdev->subsystem_device) == PCI_VENDOR_ID_LMC)
  748. subdevice = pdev->subsystem_vendor;
  749. switch (subdevice) {
  750. case PCI_DEVICE_ID_LMC_HSSI:
  751. printk(KERN_INFO "%s: LMC HSSI\n", dev->name);
  752. sc->lmc_cardtype = LMC_CARDTYPE_HSSI;
  753. sc->lmc_media = &lmc_hssi_media;
  754. break;
  755. case PCI_DEVICE_ID_LMC_DS3:
  756. printk(KERN_INFO "%s: LMC DS3\n", dev->name);
  757. sc->lmc_cardtype = LMC_CARDTYPE_DS3;
  758. sc->lmc_media = &lmc_ds3_media;
  759. break;
  760. case PCI_DEVICE_ID_LMC_SSI:
  761. printk(KERN_INFO "%s: LMC SSI\n", dev->name);
  762. sc->lmc_cardtype = LMC_CARDTYPE_SSI;
  763. sc->lmc_media = &lmc_ssi_media;
  764. break;
  765. case PCI_DEVICE_ID_LMC_T1:
  766. printk(KERN_INFO "%s: LMC T1\n", dev->name);
  767. sc->lmc_cardtype = LMC_CARDTYPE_T1;
  768. sc->lmc_media = &lmc_t1_media;
  769. break;
  770. default:
  771. printk(KERN_WARNING "%s: LMC UNKOWN CARD!\n", dev->name);
  772. break;
  773. }
  774. lmc_initcsrs (sc, dev->base_addr, 8);
  775. lmc_gpio_mkinput (sc, 0xff);
  776. sc->lmc_gpio = 0; /* drive no signals yet */
  777. sc->lmc_media->defaults (sc);
  778. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  779. /* verify that the PCI Sub System ID matches the Adapter Model number
  780. * from the MII register
  781. */
  782. AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4;
  783. if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */
  784. subdevice != PCI_DEVICE_ID_LMC_T1) &&
  785. (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */
  786. subdevice != PCI_DEVICE_ID_LMC_SSI) &&
  787. (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */
  788. subdevice != PCI_DEVICE_ID_LMC_DS3) &&
  789. (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */
  790. subdevice != PCI_DEVICE_ID_LMC_HSSI))
  791. printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI"
  792. " Subsystem ID = 0x%04x\n",
  793. dev->name, AdapModelNum, subdevice);
  794. /*
  795. * reset clock
  796. */
  797. LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL);
  798. sc->board_idx = cards_found++;
  799. sc->extra_stats.check = STATCHECK;
  800. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  801. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  802. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  803. sc->lmc_ok = 0;
  804. sc->last_link_status = 0;
  805. lmc_trace(dev, "lmc_init_one out");
  806. return 0;
  807. err_hdlcdev:
  808. pci_set_drvdata(pdev, NULL);
  809. kfree(sc);
  810. err_kzalloc:
  811. pci_release_regions(pdev);
  812. err_req_io:
  813. pci_disable_device(pdev);
  814. return err;
  815. }
  816. /*
  817. * Called from pci when removing module.
  818. */
  819. static void __devexit lmc_remove_one(struct pci_dev *pdev)
  820. {
  821. struct net_device *dev = pci_get_drvdata(pdev);
  822. if (dev) {
  823. printk(KERN_DEBUG "%s: removing...\n", dev->name);
  824. unregister_hdlc_device(dev);
  825. free_netdev(dev);
  826. pci_release_regions(pdev);
  827. pci_disable_device(pdev);
  828. pci_set_drvdata(pdev, NULL);
  829. }
  830. }
  831. /* After this is called, packets can be sent.
  832. * Does not initialize the addresses
  833. */
  834. static int lmc_open(struct net_device *dev)
  835. {
  836. lmc_softc_t *sc = dev_to_sc(dev);
  837. int err;
  838. lmc_trace(dev, "lmc_open in");
  839. lmc_led_on(sc, LMC_DS3_LED0);
  840. lmc_dec_reset(sc);
  841. lmc_reset(sc);
  842. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0);
  843. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16),
  844. lmc_mii_readreg(sc, 0, 17));
  845. if (sc->lmc_ok){
  846. lmc_trace(dev, "lmc_open lmc_ok out");
  847. return (0);
  848. }
  849. lmc_softreset (sc);
  850. /* Since we have to use PCI bus, this should work on x86,alpha,ppc */
  851. if (request_irq (dev->irq, &lmc_interrupt, IRQF_SHARED, dev->name, dev)){
  852. printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
  853. lmc_trace(dev, "lmc_open irq failed out");
  854. return -EAGAIN;
  855. }
  856. sc->got_irq = 1;
  857. /* Assert Terminal Active */
  858. sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
  859. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  860. /*
  861. * reset to last state.
  862. */
  863. sc->lmc_media->set_status (sc, NULL);
  864. /* setup default bits to be used in tulip_desc_t transmit descriptor
  865. * -baz */
  866. sc->TxDescriptControlInit = (
  867. LMC_TDES_INTERRUPT_ON_COMPLETION
  868. | LMC_TDES_FIRST_SEGMENT
  869. | LMC_TDES_LAST_SEGMENT
  870. | LMC_TDES_SECOND_ADDR_CHAINED
  871. | LMC_TDES_DISABLE_PADDING
  872. );
  873. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16) {
  874. /* disable 32 bit CRC generated by ASIC */
  875. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  876. }
  877. sc->lmc_media->set_crc_length(sc, sc->ictl.crc_length);
  878. /* Acknoledge the Terminal Active and light LEDs */
  879. /* dev->flags |= IFF_UP; */
  880. if ((err = lmc_proto_open(sc)) != 0)
  881. return err;
  882. netif_start_queue(dev);
  883. sc->extra_stats.tx_tbusy0++;
  884. /*
  885. * select what interrupts we want to get
  886. */
  887. sc->lmc_intrmask = 0;
  888. /* Should be using the default interrupt mask defined in the .h file. */
  889. sc->lmc_intrmask |= (TULIP_STS_NORMALINTR
  890. | TULIP_STS_RXINTR
  891. | TULIP_STS_TXINTR
  892. | TULIP_STS_ABNRMLINTR
  893. | TULIP_STS_SYSERROR
  894. | TULIP_STS_TXSTOPPED
  895. | TULIP_STS_TXUNDERFLOW
  896. | TULIP_STS_RXSTOPPED
  897. | TULIP_STS_RXNOBUF
  898. );
  899. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  900. sc->lmc_cmdmode |= TULIP_CMD_TXRUN;
  901. sc->lmc_cmdmode |= TULIP_CMD_RXRUN;
  902. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  903. sc->lmc_ok = 1; /* Run watchdog */
  904. /*
  905. * Set the if up now - pfb
  906. */
  907. sc->last_link_status = 1;
  908. /*
  909. * Setup a timer for the watchdog on probe, and start it running.
  910. * Since lmc_ok == 0, it will be a NOP for now.
  911. */
  912. init_timer (&sc->timer);
  913. sc->timer.expires = jiffies + HZ;
  914. sc->timer.data = (unsigned long) dev;
  915. sc->timer.function = &lmc_watchdog;
  916. add_timer (&sc->timer);
  917. lmc_trace(dev, "lmc_open out");
  918. return (0);
  919. }
  920. /* Total reset to compensate for the AdTran DSU doing bad things
  921. * under heavy load
  922. */
  923. static void lmc_running_reset (struct net_device *dev) /*fold00*/
  924. {
  925. lmc_softc_t *sc = dev_to_sc(dev);
  926. lmc_trace(dev, "lmc_runnig_reset in");
  927. /* stop interrupts */
  928. /* Clear the interrupt mask */
  929. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  930. lmc_dec_reset (sc);
  931. lmc_reset (sc);
  932. lmc_softreset (sc);
  933. /* sc->lmc_miireg16 |= LMC_MII16_LED_ALL; */
  934. sc->lmc_media->set_link_status (sc, 1);
  935. sc->lmc_media->set_status (sc, NULL);
  936. netif_wake_queue(dev);
  937. sc->lmc_txfull = 0;
  938. sc->extra_stats.tx_tbusy0++;
  939. sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK;
  940. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  941. sc->lmc_cmdmode |= (TULIP_CMD_TXRUN | TULIP_CMD_RXRUN);
  942. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  943. lmc_trace(dev, "lmc_runnin_reset_out");
  944. }
  945. /* This is what is called when you ifconfig down a device.
  946. * This disables the timer for the watchdog and keepalives,
  947. * and disables the irq for dev.
  948. */
  949. static int lmc_close(struct net_device *dev)
  950. {
  951. /* not calling release_region() as we should */
  952. lmc_softc_t *sc = dev_to_sc(dev);
  953. lmc_trace(dev, "lmc_close in");
  954. sc->lmc_ok = 0;
  955. sc->lmc_media->set_link_status (sc, 0);
  956. del_timer (&sc->timer);
  957. lmc_proto_close(sc);
  958. lmc_ifdown (dev);
  959. lmc_trace(dev, "lmc_close out");
  960. return 0;
  961. }
  962. /* Ends the transfer of packets */
  963. /* When the interface goes down, this is called */
  964. static int lmc_ifdown (struct net_device *dev) /*fold00*/
  965. {
  966. lmc_softc_t *sc = dev_to_sc(dev);
  967. u32 csr6;
  968. int i;
  969. lmc_trace(dev, "lmc_ifdown in");
  970. /* Don't let anything else go on right now */
  971. // dev->start = 0;
  972. netif_stop_queue(dev);
  973. sc->extra_stats.tx_tbusy1++;
  974. /* stop interrupts */
  975. /* Clear the interrupt mask */
  976. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  977. /* Stop Tx and Rx on the chip */
  978. csr6 = LMC_CSR_READ (sc, csr_command);
  979. csr6 &= ~LMC_DEC_ST; /* Turn off the Transmission bit */
  980. csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
  981. LMC_CSR_WRITE (sc, csr_command, csr6);
  982. sc->lmc_device->stats.rx_missed_errors +=
  983. LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  984. /* release the interrupt */
  985. if(sc->got_irq == 1){
  986. free_irq (dev->irq, dev);
  987. sc->got_irq = 0;
  988. }
  989. /* free skbuffs in the Rx queue */
  990. for (i = 0; i < LMC_RXDESCS; i++)
  991. {
  992. struct sk_buff *skb = sc->lmc_rxq[i];
  993. sc->lmc_rxq[i] = NULL;
  994. sc->lmc_rxring[i].status = 0;
  995. sc->lmc_rxring[i].length = 0;
  996. sc->lmc_rxring[i].buffer1 = 0xDEADBEEF;
  997. if (skb != NULL)
  998. dev_kfree_skb(skb);
  999. sc->lmc_rxq[i] = NULL;
  1000. }
  1001. for (i = 0; i < LMC_TXDESCS; i++)
  1002. {
  1003. if (sc->lmc_txq[i] != NULL)
  1004. dev_kfree_skb(sc->lmc_txq[i]);
  1005. sc->lmc_txq[i] = NULL;
  1006. }
  1007. lmc_led_off (sc, LMC_MII16_LED_ALL);
  1008. netif_wake_queue(dev);
  1009. sc->extra_stats.tx_tbusy0++;
  1010. lmc_trace(dev, "lmc_ifdown out");
  1011. return 0;
  1012. }
  1013. /* Interrupt handling routine. This will take an incoming packet, or clean
  1014. * up after a trasmit.
  1015. */
  1016. static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/
  1017. {
  1018. struct net_device *dev = (struct net_device *) dev_instance;
  1019. lmc_softc_t *sc = dev_to_sc(dev);
  1020. u32 csr;
  1021. int i;
  1022. s32 stat;
  1023. unsigned int badtx;
  1024. u32 firstcsr;
  1025. int max_work = LMC_RXDESCS;
  1026. int handled = 0;
  1027. lmc_trace(dev, "lmc_interrupt in");
  1028. spin_lock(&sc->lmc_lock);
  1029. /*
  1030. * Read the csr to find what interrupts we have (if any)
  1031. */
  1032. csr = LMC_CSR_READ (sc, csr_status);
  1033. /*
  1034. * Make sure this is our interrupt
  1035. */
  1036. if ( ! (csr & sc->lmc_intrmask)) {
  1037. goto lmc_int_fail_out;
  1038. }
  1039. firstcsr = csr;
  1040. /* always go through this loop at least once */
  1041. while (csr & sc->lmc_intrmask) {
  1042. handled = 1;
  1043. /*
  1044. * Clear interrupt bits, we handle all case below
  1045. */
  1046. LMC_CSR_WRITE (sc, csr_status, csr);
  1047. /*
  1048. * One of
  1049. * - Transmit process timed out CSR5<1>
  1050. * - Transmit jabber timeout CSR5<3>
  1051. * - Transmit underflow CSR5<5>
  1052. * - Transmit Receiver buffer unavailable CSR5<7>
  1053. * - Receive process stopped CSR5<8>
  1054. * - Receive watchdog timeout CSR5<9>
  1055. * - Early transmit interrupt CSR5<10>
  1056. *
  1057. * Is this really right? Should we do a running reset for jabber?
  1058. * (being a WAN card and all)
  1059. */
  1060. if (csr & TULIP_STS_ABNRMLINTR){
  1061. lmc_running_reset (dev);
  1062. break;
  1063. }
  1064. if (csr & TULIP_STS_RXINTR){
  1065. lmc_trace(dev, "rx interrupt");
  1066. lmc_rx (dev);
  1067. }
  1068. if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) {
  1069. int n_compl = 0 ;
  1070. /* reset the transmit timeout detection flag -baz */
  1071. sc->extra_stats.tx_NoCompleteCnt = 0;
  1072. badtx = sc->lmc_taint_tx;
  1073. i = badtx % LMC_TXDESCS;
  1074. while ((badtx < sc->lmc_next_tx)) {
  1075. stat = sc->lmc_txring[i].status;
  1076. LMC_EVENT_LOG (LMC_EVENT_XMTINT, stat,
  1077. sc->lmc_txring[i].length);
  1078. /*
  1079. * If bit 31 is 1 the tulip owns it break out of the loop
  1080. */
  1081. if (stat & 0x80000000)
  1082. break;
  1083. n_compl++ ; /* i.e., have an empty slot in ring */
  1084. /*
  1085. * If we have no skbuff or have cleared it
  1086. * Already continue to the next buffer
  1087. */
  1088. if (sc->lmc_txq[i] == NULL)
  1089. continue;
  1090. /*
  1091. * Check the total error summary to look for any errors
  1092. */
  1093. if (stat & 0x8000) {
  1094. sc->lmc_device->stats.tx_errors++;
  1095. if (stat & 0x4104)
  1096. sc->lmc_device->stats.tx_aborted_errors++;
  1097. if (stat & 0x0C00)
  1098. sc->lmc_device->stats.tx_carrier_errors++;
  1099. if (stat & 0x0200)
  1100. sc->lmc_device->stats.tx_window_errors++;
  1101. if (stat & 0x0002)
  1102. sc->lmc_device->stats.tx_fifo_errors++;
  1103. } else {
  1104. sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff;
  1105. sc->lmc_device->stats.tx_packets++;
  1106. }
  1107. // dev_kfree_skb(sc->lmc_txq[i]);
  1108. dev_kfree_skb_irq(sc->lmc_txq[i]);
  1109. sc->lmc_txq[i] = NULL;
  1110. badtx++;
  1111. i = badtx % LMC_TXDESCS;
  1112. }
  1113. if (sc->lmc_next_tx - badtx > LMC_TXDESCS)
  1114. {
  1115. printk ("%s: out of sync pointer\n", dev->name);
  1116. badtx += LMC_TXDESCS;
  1117. }
  1118. LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0);
  1119. sc->lmc_txfull = 0;
  1120. netif_wake_queue(dev);
  1121. sc->extra_stats.tx_tbusy0++;
  1122. #ifdef DEBUG
  1123. sc->extra_stats.dirtyTx = badtx;
  1124. sc->extra_stats.lmc_next_tx = sc->lmc_next_tx;
  1125. sc->extra_stats.lmc_txfull = sc->lmc_txfull;
  1126. #endif
  1127. sc->lmc_taint_tx = badtx;
  1128. /*
  1129. * Why was there a break here???
  1130. */
  1131. } /* end handle transmit interrupt */
  1132. if (csr & TULIP_STS_SYSERROR) {
  1133. u32 error;
  1134. printk (KERN_WARNING "%s: system bus error csr: %#8.8x\n", dev->name, csr);
  1135. error = csr>>23 & 0x7;
  1136. switch(error){
  1137. case 0x000:
  1138. printk(KERN_WARNING "%s: Parity Fault (bad)\n", dev->name);
  1139. break;
  1140. case 0x001:
  1141. printk(KERN_WARNING "%s: Master Abort (naughty)\n", dev->name);
  1142. break;
  1143. case 0x010:
  1144. printk(KERN_WARNING "%s: Target Abort (not so naughty)\n", dev->name);
  1145. break;
  1146. default:
  1147. printk(KERN_WARNING "%s: This bus error code was supposed to be reserved!\n", dev->name);
  1148. }
  1149. lmc_dec_reset (sc);
  1150. lmc_reset (sc);
  1151. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1152. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1153. lmc_mii_readreg (sc, 0, 16),
  1154. lmc_mii_readreg (sc, 0, 17));
  1155. }
  1156. if(max_work-- <= 0)
  1157. break;
  1158. /*
  1159. * Get current csr status to make sure
  1160. * we've cleared all interrupts
  1161. */
  1162. csr = LMC_CSR_READ (sc, csr_status);
  1163. } /* end interrupt loop */
  1164. LMC_EVENT_LOG(LMC_EVENT_INT, firstcsr, csr);
  1165. lmc_int_fail_out:
  1166. spin_unlock(&sc->lmc_lock);
  1167. lmc_trace(dev, "lmc_interrupt out");
  1168. return IRQ_RETVAL(handled);
  1169. }
  1170. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  1171. struct net_device *dev)
  1172. {
  1173. lmc_softc_t *sc = dev_to_sc(dev);
  1174. u32 flag;
  1175. int entry;
  1176. unsigned long flags;
  1177. lmc_trace(dev, "lmc_start_xmit in");
  1178. spin_lock_irqsave(&sc->lmc_lock, flags);
  1179. /* normal path, tbusy known to be zero */
  1180. entry = sc->lmc_next_tx % LMC_TXDESCS;
  1181. sc->lmc_txq[entry] = skb;
  1182. sc->lmc_txring[entry].buffer1 = virt_to_bus (skb->data);
  1183. LMC_CONSOLE_LOG("xmit", skb->data, skb->len);
  1184. #ifndef GCOM
  1185. /* If the queue is less than half full, don't interrupt */
  1186. if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS / 2)
  1187. {
  1188. /* Do not interrupt on completion of this packet */
  1189. flag = 0x60000000;
  1190. netif_wake_queue(dev);
  1191. }
  1192. else if (sc->lmc_next_tx - sc->lmc_taint_tx == LMC_TXDESCS / 2)
  1193. {
  1194. /* This generates an interrupt on completion of this packet */
  1195. flag = 0xe0000000;
  1196. netif_wake_queue(dev);
  1197. }
  1198. else if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS - 1)
  1199. {
  1200. /* Do not interrupt on completion of this packet */
  1201. flag = 0x60000000;
  1202. netif_wake_queue(dev);
  1203. }
  1204. else
  1205. {
  1206. /* This generates an interrupt on completion of this packet */
  1207. flag = 0xe0000000;
  1208. sc->lmc_txfull = 1;
  1209. netif_stop_queue(dev);
  1210. }
  1211. #else
  1212. flag = LMC_TDES_INTERRUPT_ON_COMPLETION;
  1213. if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1)
  1214. { /* ring full, go busy */
  1215. sc->lmc_txfull = 1;
  1216. netif_stop_queue(dev);
  1217. sc->extra_stats.tx_tbusy1++;
  1218. LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0);
  1219. }
  1220. #endif
  1221. if (entry == LMC_TXDESCS - 1) /* last descriptor in ring */
  1222. flag |= LMC_TDES_END_OF_RING; /* flag as such for Tulip */
  1223. /* don't pad small packets either */
  1224. flag = sc->lmc_txring[entry].length = (skb->len) | flag |
  1225. sc->TxDescriptControlInit;
  1226. /* set the transmit timeout flag to be checked in
  1227. * the watchdog timer handler. -baz
  1228. */
  1229. sc->extra_stats.tx_NoCompleteCnt++;
  1230. sc->lmc_next_tx++;
  1231. /* give ownership to the chip */
  1232. LMC_EVENT_LOG(LMC_EVENT_XMT, flag, entry);
  1233. sc->lmc_txring[entry].status = 0x80000000;
  1234. /* send now! */
  1235. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1236. dev->trans_start = jiffies;
  1237. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1238. lmc_trace(dev, "lmc_start_xmit_out");
  1239. return NETDEV_TX_OK;
  1240. }
  1241. static int lmc_rx(struct net_device *dev)
  1242. {
  1243. lmc_softc_t *sc = dev_to_sc(dev);
  1244. int i;
  1245. int rx_work_limit = LMC_RXDESCS;
  1246. unsigned int next_rx;
  1247. int rxIntLoopCnt; /* debug -baz */
  1248. int localLengthErrCnt = 0;
  1249. long stat;
  1250. struct sk_buff *skb, *nsb;
  1251. u16 len;
  1252. lmc_trace(dev, "lmc_rx in");
  1253. lmc_led_on(sc, LMC_DS3_LED3);
  1254. rxIntLoopCnt = 0; /* debug -baz */
  1255. i = sc->lmc_next_rx % LMC_RXDESCS;
  1256. next_rx = sc->lmc_next_rx;
  1257. while (((stat = sc->lmc_rxring[i].status) & LMC_RDES_OWN_BIT) != DESC_OWNED_BY_DC21X4)
  1258. {
  1259. rxIntLoopCnt++; /* debug -baz */
  1260. len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER);
  1261. if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */
  1262. if ((stat & 0x0000ffff) != 0x7fff) {
  1263. /* Oversized frame */
  1264. sc->lmc_device->stats.rx_length_errors++;
  1265. goto skip_packet;
  1266. }
  1267. }
  1268. if (stat & 0x00000008) { /* Catch a dribbling bit error */
  1269. sc->lmc_device->stats.rx_errors++;
  1270. sc->lmc_device->stats.rx_frame_errors++;
  1271. goto skip_packet;
  1272. }
  1273. if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */
  1274. sc->lmc_device->stats.rx_errors++;
  1275. sc->lmc_device->stats.rx_crc_errors++;
  1276. goto skip_packet;
  1277. }
  1278. if (len > LMC_PKT_BUF_SZ) {
  1279. sc->lmc_device->stats.rx_length_errors++;
  1280. localLengthErrCnt++;
  1281. goto skip_packet;
  1282. }
  1283. if (len < sc->lmc_crcSize + 2) {
  1284. sc->lmc_device->stats.rx_length_errors++;
  1285. sc->extra_stats.rx_SmallPktCnt++;
  1286. localLengthErrCnt++;
  1287. goto skip_packet;
  1288. }
  1289. if(stat & 0x00004000){
  1290. printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name);
  1291. }
  1292. len -= sc->lmc_crcSize;
  1293. skb = sc->lmc_rxq[i];
  1294. /*
  1295. * We ran out of memory at some point
  1296. * just allocate an skb buff and continue.
  1297. */
  1298. if (!skb) {
  1299. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1300. if (nsb) {
  1301. sc->lmc_rxq[i] = nsb;
  1302. nsb->dev = dev;
  1303. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1304. }
  1305. sc->failed_recv_alloc = 1;
  1306. goto skip_packet;
  1307. }
  1308. sc->lmc_device->stats.rx_packets++;
  1309. sc->lmc_device->stats.rx_bytes += len;
  1310. LMC_CONSOLE_LOG("recv", skb->data, len);
  1311. /*
  1312. * I'm not sure of the sanity of this
  1313. * Packets could be arriving at a constant
  1314. * 44.210mbits/sec and we're going to copy
  1315. * them into a new buffer??
  1316. */
  1317. if(len > (LMC_MTU - (LMC_MTU>>2))){ /* len > LMC_MTU * 0.75 */
  1318. /*
  1319. * If it's a large packet don't copy it just hand it up
  1320. */
  1321. give_it_anyways:
  1322. sc->lmc_rxq[i] = NULL;
  1323. sc->lmc_rxring[i].buffer1 = 0x0;
  1324. skb_put (skb, len);
  1325. skb->protocol = lmc_proto_type(sc, skb);
  1326. skb_reset_mac_header(skb);
  1327. /* skb_reset_network_header(skb); */
  1328. skb->dev = dev;
  1329. lmc_proto_netif(sc, skb);
  1330. /*
  1331. * This skb will be destroyed by the upper layers, make a new one
  1332. */
  1333. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1334. if (nsb) {
  1335. sc->lmc_rxq[i] = nsb;
  1336. nsb->dev = dev;
  1337. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1338. /* Transferred to 21140 below */
  1339. }
  1340. else {
  1341. /*
  1342. * We've run out of memory, stop trying to allocate
  1343. * memory and exit the interrupt handler
  1344. *
  1345. * The chip may run out of receivers and stop
  1346. * in which care we'll try to allocate the buffer
  1347. * again. (once a second)
  1348. */
  1349. sc->extra_stats.rx_BuffAllocErr++;
  1350. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1351. sc->failed_recv_alloc = 1;
  1352. goto skip_out_of_mem;
  1353. }
  1354. }
  1355. else {
  1356. nsb = dev_alloc_skb(len);
  1357. if(!nsb) {
  1358. goto give_it_anyways;
  1359. }
  1360. skb_copy_from_linear_data(skb, skb_put(nsb, len), len);
  1361. nsb->protocol = lmc_proto_type(sc, nsb);
  1362. skb_reset_mac_header(nsb);
  1363. /* skb_reset_network_header(nsb); */
  1364. nsb->dev = dev;
  1365. lmc_proto_netif(sc, nsb);
  1366. }
  1367. skip_packet:
  1368. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1369. sc->lmc_rxring[i].status = DESC_OWNED_BY_DC21X4;
  1370. sc->lmc_next_rx++;
  1371. i = sc->lmc_next_rx % LMC_RXDESCS;
  1372. rx_work_limit--;
  1373. if (rx_work_limit < 0)
  1374. break;
  1375. }
  1376. /* detect condition for LMC1000 where DSU cable attaches and fills
  1377. * descriptors with bogus packets
  1378. *
  1379. if (localLengthErrCnt > LMC_RXDESCS - 3) {
  1380. sc->extra_stats.rx_BadPktSurgeCnt++;
  1381. LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt,
  1382. sc->extra_stats.rx_BadPktSurgeCnt);
  1383. } */
  1384. /* save max count of receive descriptors serviced */
  1385. if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt)
  1386. sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */
  1387. #ifdef DEBUG
  1388. if (rxIntLoopCnt == 0)
  1389. {
  1390. for (i = 0; i < LMC_RXDESCS; i++)
  1391. {
  1392. if ((sc->lmc_rxring[i].status & LMC_RDES_OWN_BIT)
  1393. != DESC_OWNED_BY_DC21X4)
  1394. {
  1395. rxIntLoopCnt++;
  1396. }
  1397. }
  1398. LMC_EVENT_LOG(LMC_EVENT_RCVEND, rxIntLoopCnt, 0);
  1399. }
  1400. #endif
  1401. lmc_led_off(sc, LMC_DS3_LED3);
  1402. skip_out_of_mem:
  1403. lmc_trace(dev, "lmc_rx out");
  1404. return 0;
  1405. }
  1406. static struct net_device_stats *lmc_get_stats(struct net_device *dev)
  1407. {
  1408. lmc_softc_t *sc = dev_to_sc(dev);
  1409. unsigned long flags;
  1410. lmc_trace(dev, "lmc_get_stats in");
  1411. spin_lock_irqsave(&sc->lmc_lock, flags);
  1412. sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  1413. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1414. lmc_trace(dev, "lmc_get_stats out");
  1415. return &sc->lmc_device->stats;
  1416. }
  1417. static struct pci_driver lmc_driver = {
  1418. .name = "lmc",
  1419. .id_table = lmc_pci_tbl,
  1420. .probe = lmc_init_one,
  1421. .remove = __devexit_p(lmc_remove_one),
  1422. };
  1423. static int __init init_lmc(void)
  1424. {
  1425. return pci_register_driver(&lmc_driver);
  1426. }
  1427. static void __exit exit_lmc(void)
  1428. {
  1429. pci_unregister_driver(&lmc_driver);
  1430. }
  1431. module_init(init_lmc);
  1432. module_exit(exit_lmc);
  1433. unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno) /*fold00*/
  1434. {
  1435. int i;
  1436. int command = (0xf6 << 10) | (devaddr << 5) | regno;
  1437. int retval = 0;
  1438. lmc_trace(sc->lmc_device, "lmc_mii_readreg in");
  1439. LMC_MII_SYNC (sc);
  1440. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done sync");
  1441. for (i = 15; i >= 0; i--)
  1442. {
  1443. int dataval = (command & (1 << i)) ? 0x20000 : 0;
  1444. LMC_CSR_WRITE (sc, csr_9, dataval);
  1445. lmc_delay ();
  1446. /* __SLOW_DOWN_IO; */
  1447. LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
  1448. lmc_delay ();
  1449. /* __SLOW_DOWN_IO; */
  1450. }
  1451. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done1");
  1452. for (i = 19; i > 0; i--)
  1453. {
  1454. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1455. lmc_delay ();
  1456. /* __SLOW_DOWN_IO; */
  1457. retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
  1458. LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
  1459. lmc_delay ();
  1460. /* __SLOW_DOWN_IO; */
  1461. }
  1462. lmc_trace(sc->lmc_device, "lmc_mii_readreg out");
  1463. return (retval >> 1) & 0xffff;
  1464. }
  1465. void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno, unsigned data) /*fold00*/
  1466. {
  1467. int i = 32;
  1468. int command = (0x5002 << 16) | (devaddr << 23) | (regno << 18) | data;
  1469. lmc_trace(sc->lmc_device, "lmc_mii_writereg in");
  1470. LMC_MII_SYNC (sc);
  1471. i = 31;
  1472. while (i >= 0)
  1473. {
  1474. int datav;
  1475. if (command & (1 << i))
  1476. datav = 0x20000;
  1477. else
  1478. datav = 0x00000;
  1479. LMC_CSR_WRITE (sc, csr_9, datav);
  1480. lmc_delay ();
  1481. /* __SLOW_DOWN_IO; */
  1482. LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
  1483. lmc_delay ();
  1484. /* __SLOW_DOWN_IO; */
  1485. i--;
  1486. }
  1487. i = 2;
  1488. while (i > 0)
  1489. {
  1490. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1491. lmc_delay ();
  1492. /* __SLOW_DOWN_IO; */
  1493. LMC_CSR_WRITE (sc, csr_9, 0x50000);
  1494. lmc_delay ();
  1495. /* __SLOW_DOWN_IO; */
  1496. i--;
  1497. }
  1498. lmc_trace(sc->lmc_device, "lmc_mii_writereg out");
  1499. }
  1500. static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/
  1501. {
  1502. int i;
  1503. lmc_trace(sc->lmc_device, "lmc_softreset in");
  1504. /* Initialize the receive rings and buffers. */
  1505. sc->lmc_txfull = 0;
  1506. sc->lmc_next_rx = 0;
  1507. sc->lmc_next_tx = 0;
  1508. sc->lmc_taint_rx = 0;
  1509. sc->lmc_taint_tx = 0;
  1510. /*
  1511. * Setup each one of the receiver buffers
  1512. * allocate an skbuff for each one, setup the descriptor table
  1513. * and point each buffer at the next one
  1514. */
  1515. for (i = 0; i < LMC_RXDESCS; i++)
  1516. {
  1517. struct sk_buff *skb;
  1518. if (sc->lmc_rxq[i] == NULL)
  1519. {
  1520. skb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1521. if(skb == NULL){
  1522. printk(KERN_WARNING "%s: Failed to allocate receiver ring, will try again\n", sc->name);
  1523. sc->failed_ring = 1;
  1524. break;
  1525. }
  1526. else{
  1527. sc->lmc_rxq[i] = skb;
  1528. }
  1529. }
  1530. else
  1531. {
  1532. skb = sc->lmc_rxq[i];
  1533. }
  1534. skb->dev = sc->lmc_device;
  1535. /* owned by 21140 */
  1536. sc->lmc_rxring[i].status = 0x80000000;
  1537. /* used to be PKT_BUF_SZ now uses skb since we lose some to head room */
  1538. sc->lmc_rxring[i].length = skb_tailroom(skb);
  1539. /* use to be tail which is dumb since you're thinking why write
  1540. * to the end of the packj,et but since there's nothing there tail == data
  1541. */
  1542. sc->lmc_rxring[i].buffer1 = virt_to_bus (skb->data);
  1543. /* This is fair since the structure is static and we have the next address */
  1544. sc->lmc_rxring[i].buffer2 = virt_to_bus (&sc->lmc_rxring[i + 1]);
  1545. }
  1546. /*
  1547. * Sets end of ring
  1548. */
  1549. if (i != 0) {
  1550. sc->lmc_rxring[i - 1].length |= 0x02000000; /* Set end of buffers flag */
  1551. sc->lmc_rxring[i - 1].buffer2 = virt_to_bus(&sc->lmc_rxring[0]); /* Point back to the start */
  1552. }
  1553. LMC_CSR_WRITE (sc, csr_rxlist, virt_to_bus (sc->lmc_rxring)); /* write base address */
  1554. /* Initialize the transmit rings and buffers */
  1555. for (i = 0; i < LMC_TXDESCS; i++)
  1556. {
  1557. if (sc->lmc_txq[i] != NULL){ /* have buffer */
  1558. dev_kfree_skb(sc->lmc_txq[i]); /* free it */
  1559. sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */
  1560. }
  1561. sc->lmc_txq[i] = NULL;
  1562. sc->lmc_txring[i].status = 0x00000000;
  1563. sc->lmc_txring[i].buffer2 = virt_to_bus (&sc->lmc_txring[i + 1]);
  1564. }
  1565. sc->lmc_txring[i - 1].buffer2 = virt_to_bus (&sc->lmc_txring[0]);
  1566. LMC_CSR_WRITE (sc, csr_txlist, virt_to_bus (sc->lmc_txring));
  1567. lmc_trace(sc->lmc_device, "lmc_softreset out");
  1568. }
  1569. void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1570. {
  1571. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in");
  1572. sc->lmc_gpio_io &= ~bits;
  1573. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1574. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out");
  1575. }
  1576. void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1577. {
  1578. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in");
  1579. sc->lmc_gpio_io |= bits;
  1580. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1581. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out");
  1582. }
  1583. void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/
  1584. {
  1585. lmc_trace(sc->lmc_device, "lmc_led_on in");
  1586. if((~sc->lmc_miireg16) & led){ /* Already on! */
  1587. lmc_trace(sc->lmc_device, "lmc_led_on aon out");
  1588. return;
  1589. }
  1590. sc->lmc_miireg16 &= ~led;
  1591. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1592. lmc_trace(sc->lmc_device, "lmc_led_on out");
  1593. }
  1594. void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/
  1595. {
  1596. lmc_trace(sc->lmc_device, "lmc_led_off in");
  1597. if(sc->lmc_miireg16 & led){ /* Already set don't do anything */
  1598. lmc_trace(sc->lmc_device, "lmc_led_off aoff out");
  1599. return;
  1600. }
  1601. sc->lmc_miireg16 |= led;
  1602. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1603. lmc_trace(sc->lmc_device, "lmc_led_off out");
  1604. }
  1605. static void lmc_reset(lmc_softc_t * const sc) /*fold00*/
  1606. {
  1607. lmc_trace(sc->lmc_device, "lmc_reset in");
  1608. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  1609. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1610. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  1611. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1612. /*
  1613. * make some of the GPIO pins be outputs
  1614. */
  1615. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  1616. /*
  1617. * RESET low to force state reset. This also forces
  1618. * the transmitter clock to be internal, but we expect to reset
  1619. * that later anyway.
  1620. */
  1621. sc->lmc_gpio &= ~(LMC_GEP_RESET);
  1622. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  1623. /*
  1624. * hold for more than 10 microseconds
  1625. */
  1626. udelay(50);
  1627. /*
  1628. * stop driving Xilinx-related signals
  1629. */
  1630. lmc_gpio_mkinput(sc, LMC_GEP_RESET);
  1631. /*
  1632. * Call media specific init routine
  1633. */
  1634. sc->lmc_media->init(sc);
  1635. sc->extra_stats.resetCount++;
  1636. lmc_trace(sc->lmc_device, "lmc_reset out");
  1637. }
  1638. static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/
  1639. {
  1640. u32 val;
  1641. lmc_trace(sc->lmc_device, "lmc_dec_reset in");
  1642. /*
  1643. * disable all interrupts
  1644. */
  1645. sc->lmc_intrmask = 0;
  1646. LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
  1647. /*
  1648. * Reset the chip with a software reset command.
  1649. * Wait 10 microseconds (actually 50 PCI cycles but at
  1650. * 33MHz that comes to two microseconds but wait a
  1651. * bit longer anyways)
  1652. */
  1653. LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
  1654. udelay(25);
  1655. #ifdef __sparc__
  1656. sc->lmc_busmode = LMC_CSR_READ(sc, csr_busmode);
  1657. sc->lmc_busmode = 0x00100000;
  1658. sc->lmc_busmode &= ~TULIP_BUSMODE_SWRESET;
  1659. LMC_CSR_WRITE(sc, csr_busmode, sc->lmc_busmode);
  1660. #endif
  1661. sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
  1662. /*
  1663. * We want:
  1664. * no ethernet address in frames we write
  1665. * disable padding (txdesc, padding disable)
  1666. * ignore runt frames (rdes0 bit 15)
  1667. * no receiver watchdog or transmitter jabber timer
  1668. * (csr15 bit 0,14 == 1)
  1669. * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
  1670. */
  1671. sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
  1672. | TULIP_CMD_FULLDUPLEX
  1673. | TULIP_CMD_PASSBADPKT
  1674. | TULIP_CMD_NOHEARTBEAT
  1675. | TULIP_CMD_PORTSELECT
  1676. | TULIP_CMD_RECEIVEALL
  1677. | TULIP_CMD_MUSTBEONE
  1678. );
  1679. sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
  1680. | TULIP_CMD_THRESHOLDCTL
  1681. | TULIP_CMD_STOREFWD
  1682. | TULIP_CMD_TXTHRSHLDCTL
  1683. );
  1684. LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
  1685. /*
  1686. * disable receiver watchdog and transmit jabber
  1687. */
  1688. val = LMC_CSR_READ(sc, csr_sia_general);
  1689. val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
  1690. LMC_CSR_WRITE(sc, csr_sia_general, val);
  1691. lmc_trace(sc->lmc_device, "lmc_dec_reset out");
  1692. }
  1693. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/
  1694. size_t csr_size)
  1695. {
  1696. lmc_trace(sc->lmc_device, "lmc_initcsrs in");
  1697. sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
  1698. sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
  1699. sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
  1700. sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
  1701. sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
  1702. sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
  1703. sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
  1704. sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
  1705. sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
  1706. sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
  1707. sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
  1708. sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
  1709. sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
  1710. sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
  1711. sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
  1712. sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
  1713. lmc_trace(sc->lmc_device, "lmc_initcsrs out");
  1714. }
  1715. static void lmc_driver_timeout(struct net_device *dev)
  1716. {
  1717. lmc_softc_t *sc = dev_to_sc(dev);
  1718. u32 csr6;
  1719. unsigned long flags;
  1720. lmc_trace(dev, "lmc_driver_timeout in");
  1721. spin_lock_irqsave(&sc->lmc_lock, flags);
  1722. printk("%s: Xmitter busy|\n", dev->name);
  1723. sc->extra_stats.tx_tbusy_calls++;
  1724. if (jiffies - dev->trans_start < TX_TIMEOUT)
  1725. goto bug_out;
  1726. /*
  1727. * Chip seems to have locked up
  1728. * Reset it
  1729. * This whips out all our decriptor
  1730. * table and starts from scartch
  1731. */
  1732. LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO,
  1733. LMC_CSR_READ (sc, csr_status),
  1734. sc->extra_stats.tx_ProcTimeout);
  1735. lmc_running_reset (dev);
  1736. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1737. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1738. lmc_mii_readreg (sc, 0, 16),
  1739. lmc_mii_readreg (sc, 0, 17));
  1740. /* restart the tx processes */
  1741. csr6 = LMC_CSR_READ (sc, csr_command);
  1742. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x0002);
  1743. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x2002);
  1744. /* immediate transmit */
  1745. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1746. sc->lmc_device->stats.tx_errors++;
  1747. sc->extra_stats.tx_ProcTimeout++; /* -baz */
  1748. dev->trans_start = jiffies;
  1749. bug_out:
  1750. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1751. lmc_trace(dev, "lmc_driver_timout out");
  1752. }