smsc95xx.c 33 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include "smsc95xx.h"
  31. #define SMSC_CHIPNAME "smsc95xx"
  32. #define SMSC_DRIVER_VERSION "1.0.4"
  33. #define HS_USB_PKT_SIZE (512)
  34. #define FS_USB_PKT_SIZE (64)
  35. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  36. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  37. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  38. #define MAX_SINGLE_PACKET_SIZE (2048)
  39. #define LAN95XX_EEPROM_MAGIC (0x9500)
  40. #define EEPROM_MAC_OFFSET (0x01)
  41. #define DEFAULT_TX_CSUM_ENABLE (true)
  42. #define DEFAULT_RX_CSUM_ENABLE (true)
  43. #define SMSC95XX_INTERNAL_PHY_ID (1)
  44. #define SMSC95XX_TX_OVERHEAD (8)
  45. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  46. struct smsc95xx_priv {
  47. u32 mac_cr;
  48. spinlock_t mac_cr_lock;
  49. bool use_tx_csum;
  50. bool use_rx_csum;
  51. };
  52. struct usb_context {
  53. struct usb_ctrlrequest req;
  54. struct usbnet *dev;
  55. };
  56. static int turbo_mode = true;
  57. module_param(turbo_mode, bool, 0644);
  58. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  59. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  60. {
  61. u32 *buf = kmalloc(4, GFP_KERNEL);
  62. int ret;
  63. BUG_ON(!dev);
  64. if (!buf)
  65. return -ENOMEM;
  66. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  67. USB_VENDOR_REQUEST_READ_REGISTER,
  68. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  69. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  70. if (unlikely(ret < 0))
  71. devwarn(dev, "Failed to read register index 0x%08x", index);
  72. le32_to_cpus(buf);
  73. *data = *buf;
  74. kfree(buf);
  75. return ret;
  76. }
  77. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  78. {
  79. u32 *buf = kmalloc(4, GFP_KERNEL);
  80. int ret;
  81. BUG_ON(!dev);
  82. if (!buf)
  83. return -ENOMEM;
  84. *buf = data;
  85. cpu_to_le32s(buf);
  86. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  87. USB_VENDOR_REQUEST_WRITE_REGISTER,
  88. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  89. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  90. if (unlikely(ret < 0))
  91. devwarn(dev, "Failed to write register index 0x%08x", index);
  92. kfree(buf);
  93. return ret;
  94. }
  95. /* Loop until the read is completed with timeout
  96. * called with phy_mutex held */
  97. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  98. {
  99. unsigned long start_time = jiffies;
  100. u32 val;
  101. do {
  102. smsc95xx_read_reg(dev, MII_ADDR, &val);
  103. if (!(val & MII_BUSY_))
  104. return 0;
  105. } while (!time_after(jiffies, start_time + HZ));
  106. return -EIO;
  107. }
  108. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  109. {
  110. struct usbnet *dev = netdev_priv(netdev);
  111. u32 val, addr;
  112. mutex_lock(&dev->phy_mutex);
  113. /* confirm MII not busy */
  114. if (smsc95xx_phy_wait_not_busy(dev)) {
  115. devwarn(dev, "MII is busy in smsc95xx_mdio_read");
  116. mutex_unlock(&dev->phy_mutex);
  117. return -EIO;
  118. }
  119. /* set the address, index & direction (read from PHY) */
  120. phy_id &= dev->mii.phy_id_mask;
  121. idx &= dev->mii.reg_num_mask;
  122. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  123. smsc95xx_write_reg(dev, MII_ADDR, addr);
  124. if (smsc95xx_phy_wait_not_busy(dev)) {
  125. devwarn(dev, "Timed out reading MII reg %02X", idx);
  126. mutex_unlock(&dev->phy_mutex);
  127. return -EIO;
  128. }
  129. smsc95xx_read_reg(dev, MII_DATA, &val);
  130. mutex_unlock(&dev->phy_mutex);
  131. return (u16)(val & 0xFFFF);
  132. }
  133. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  134. int regval)
  135. {
  136. struct usbnet *dev = netdev_priv(netdev);
  137. u32 val, addr;
  138. mutex_lock(&dev->phy_mutex);
  139. /* confirm MII not busy */
  140. if (smsc95xx_phy_wait_not_busy(dev)) {
  141. devwarn(dev, "MII is busy in smsc95xx_mdio_write");
  142. mutex_unlock(&dev->phy_mutex);
  143. return;
  144. }
  145. val = regval;
  146. smsc95xx_write_reg(dev, MII_DATA, val);
  147. /* set the address, index & direction (write to PHY) */
  148. phy_id &= dev->mii.phy_id_mask;
  149. idx &= dev->mii.reg_num_mask;
  150. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  151. smsc95xx_write_reg(dev, MII_ADDR, addr);
  152. if (smsc95xx_phy_wait_not_busy(dev))
  153. devwarn(dev, "Timed out writing MII reg %02X", idx);
  154. mutex_unlock(&dev->phy_mutex);
  155. }
  156. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  157. {
  158. unsigned long start_time = jiffies;
  159. u32 val;
  160. do {
  161. smsc95xx_read_reg(dev, E2P_CMD, &val);
  162. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  163. break;
  164. udelay(40);
  165. } while (!time_after(jiffies, start_time + HZ));
  166. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  167. devwarn(dev, "EEPROM read operation timeout");
  168. return -EIO;
  169. }
  170. return 0;
  171. }
  172. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  173. {
  174. unsigned long start_time = jiffies;
  175. u32 val;
  176. do {
  177. smsc95xx_read_reg(dev, E2P_CMD, &val);
  178. if (!(val & E2P_CMD_BUSY_))
  179. return 0;
  180. udelay(40);
  181. } while (!time_after(jiffies, start_time + HZ));
  182. devwarn(dev, "EEPROM is busy");
  183. return -EIO;
  184. }
  185. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  186. u8 *data)
  187. {
  188. u32 val;
  189. int i, ret;
  190. BUG_ON(!dev);
  191. BUG_ON(!data);
  192. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  193. if (ret)
  194. return ret;
  195. for (i = 0; i < length; i++) {
  196. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  197. smsc95xx_write_reg(dev, E2P_CMD, val);
  198. ret = smsc95xx_wait_eeprom(dev);
  199. if (ret < 0)
  200. return ret;
  201. smsc95xx_read_reg(dev, E2P_DATA, &val);
  202. data[i] = val & 0xFF;
  203. offset++;
  204. }
  205. return 0;
  206. }
  207. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  208. u8 *data)
  209. {
  210. u32 val;
  211. int i, ret;
  212. BUG_ON(!dev);
  213. BUG_ON(!data);
  214. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  215. if (ret)
  216. return ret;
  217. /* Issue write/erase enable command */
  218. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  219. smsc95xx_write_reg(dev, E2P_CMD, val);
  220. ret = smsc95xx_wait_eeprom(dev);
  221. if (ret < 0)
  222. return ret;
  223. for (i = 0; i < length; i++) {
  224. /* Fill data register */
  225. val = data[i];
  226. smsc95xx_write_reg(dev, E2P_DATA, val);
  227. /* Send "write" command */
  228. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  229. smsc95xx_write_reg(dev, E2P_CMD, val);
  230. ret = smsc95xx_wait_eeprom(dev);
  231. if (ret < 0)
  232. return ret;
  233. offset++;
  234. }
  235. return 0;
  236. }
  237. static void smsc95xx_async_cmd_callback(struct urb *urb)
  238. {
  239. struct usb_context *usb_context = urb->context;
  240. struct usbnet *dev = usb_context->dev;
  241. int status = urb->status;
  242. if (status < 0)
  243. devwarn(dev, "async callback failed with %d", status);
  244. kfree(usb_context);
  245. usb_free_urb(urb);
  246. }
  247. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  248. {
  249. struct usb_context *usb_context;
  250. int status;
  251. struct urb *urb;
  252. const u16 size = 4;
  253. urb = usb_alloc_urb(0, GFP_ATOMIC);
  254. if (!urb) {
  255. devwarn(dev, "Error allocating URB");
  256. return -ENOMEM;
  257. }
  258. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  259. if (usb_context == NULL) {
  260. devwarn(dev, "Error allocating control msg");
  261. usb_free_urb(urb);
  262. return -ENOMEM;
  263. }
  264. usb_context->req.bRequestType =
  265. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  266. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  267. usb_context->req.wValue = 00;
  268. usb_context->req.wIndex = cpu_to_le16(index);
  269. usb_context->req.wLength = cpu_to_le16(size);
  270. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  271. (void *)&usb_context->req, data, size,
  272. smsc95xx_async_cmd_callback,
  273. (void *)usb_context);
  274. status = usb_submit_urb(urb, GFP_ATOMIC);
  275. if (status < 0) {
  276. devwarn(dev, "Error submitting control msg, sts=%d", status);
  277. kfree(usb_context);
  278. usb_free_urb(urb);
  279. }
  280. return status;
  281. }
  282. /* returns hash bit number for given MAC address
  283. * example:
  284. * 01 00 5E 00 00 01 -> returns bit number 31 */
  285. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  286. {
  287. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  288. }
  289. static void smsc95xx_set_multicast(struct net_device *netdev)
  290. {
  291. struct usbnet *dev = netdev_priv(netdev);
  292. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  293. u32 hash_hi = 0;
  294. u32 hash_lo = 0;
  295. unsigned long flags;
  296. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  297. if (dev->net->flags & IFF_PROMISC) {
  298. if (netif_msg_drv(dev))
  299. devdbg(dev, "promiscuous mode enabled");
  300. pdata->mac_cr |= MAC_CR_PRMS_;
  301. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  302. } else if (dev->net->flags & IFF_ALLMULTI) {
  303. if (netif_msg_drv(dev))
  304. devdbg(dev, "receive all multicast enabled");
  305. pdata->mac_cr |= MAC_CR_MCPAS_;
  306. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  307. } else if (dev->net->mc_count > 0) {
  308. struct dev_mc_list *mc_list = dev->net->mc_list;
  309. int count = 0;
  310. pdata->mac_cr |= MAC_CR_HPFILT_;
  311. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  312. while (mc_list) {
  313. count++;
  314. if (mc_list->dmi_addrlen == ETH_ALEN) {
  315. u32 bitnum = smsc95xx_hash(mc_list->dmi_addr);
  316. u32 mask = 0x01 << (bitnum & 0x1F);
  317. if (bitnum & 0x20)
  318. hash_hi |= mask;
  319. else
  320. hash_lo |= mask;
  321. } else {
  322. devwarn(dev, "dmi_addrlen != 6");
  323. }
  324. mc_list = mc_list->next;
  325. }
  326. if (count != ((u32)dev->net->mc_count))
  327. devwarn(dev, "mc_count != dev->mc_count");
  328. if (netif_msg_drv(dev))
  329. devdbg(dev, "HASHH=0x%08X, HASHL=0x%08X", hash_hi,
  330. hash_lo);
  331. } else {
  332. if (netif_msg_drv(dev))
  333. devdbg(dev, "receive own packets only");
  334. pdata->mac_cr &=
  335. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  336. }
  337. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  338. /* Initiate async writes, as we can't wait for completion here */
  339. smsc95xx_write_reg_async(dev, HASHH, &hash_hi);
  340. smsc95xx_write_reg_async(dev, HASHL, &hash_lo);
  341. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  342. }
  343. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  344. u16 lcladv, u16 rmtadv)
  345. {
  346. u32 flow, afc_cfg = 0;
  347. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  348. if (ret < 0) {
  349. devwarn(dev, "error reading AFC_CFG");
  350. return;
  351. }
  352. if (duplex == DUPLEX_FULL) {
  353. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  354. if (cap & FLOW_CTRL_RX)
  355. flow = 0xFFFF0002;
  356. else
  357. flow = 0;
  358. if (cap & FLOW_CTRL_TX)
  359. afc_cfg |= 0xF;
  360. else
  361. afc_cfg &= ~0xF;
  362. if (netif_msg_link(dev))
  363. devdbg(dev, "rx pause %s, tx pause %s",
  364. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  365. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  366. } else {
  367. if (netif_msg_link(dev))
  368. devdbg(dev, "half duplex");
  369. flow = 0;
  370. afc_cfg |= 0xF;
  371. }
  372. smsc95xx_write_reg(dev, FLOW, flow);
  373. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  374. }
  375. static int smsc95xx_link_reset(struct usbnet *dev)
  376. {
  377. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  378. struct mii_if_info *mii = &dev->mii;
  379. struct ethtool_cmd ecmd;
  380. unsigned long flags;
  381. u16 lcladv, rmtadv;
  382. u32 intdata;
  383. /* clear interrupt status */
  384. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  385. intdata = 0xFFFFFFFF;
  386. smsc95xx_write_reg(dev, INT_STS, intdata);
  387. mii_check_media(mii, 1, 1);
  388. mii_ethtool_gset(&dev->mii, &ecmd);
  389. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  390. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  391. if (netif_msg_link(dev))
  392. devdbg(dev, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x",
  393. ecmd.speed, ecmd.duplex, lcladv, rmtadv);
  394. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  395. if (ecmd.duplex != DUPLEX_FULL) {
  396. pdata->mac_cr &= ~MAC_CR_FDPX_;
  397. pdata->mac_cr |= MAC_CR_RCVOWN_;
  398. } else {
  399. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  400. pdata->mac_cr |= MAC_CR_FDPX_;
  401. }
  402. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  403. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  404. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  405. return 0;
  406. }
  407. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  408. {
  409. u32 intdata;
  410. if (urb->actual_length != 4) {
  411. devwarn(dev, "unexpected urb length %d", urb->actual_length);
  412. return;
  413. }
  414. memcpy(&intdata, urb->transfer_buffer, 4);
  415. le32_to_cpus(&intdata);
  416. if (netif_msg_link(dev))
  417. devdbg(dev, "intdata: 0x%08X", intdata);
  418. if (intdata & INT_ENP_PHY_INT_)
  419. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  420. else
  421. devwarn(dev, "unexpected interrupt, intdata=0x%08X", intdata);
  422. }
  423. /* Enable or disable Tx & Rx checksum offload engines */
  424. static int smsc95xx_set_csums(struct usbnet *dev)
  425. {
  426. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  427. u32 read_buf;
  428. int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  429. if (ret < 0) {
  430. devwarn(dev, "Failed to read COE_CR: %d", ret);
  431. return ret;
  432. }
  433. if (pdata->use_tx_csum)
  434. read_buf |= Tx_COE_EN_;
  435. else
  436. read_buf &= ~Tx_COE_EN_;
  437. if (pdata->use_rx_csum)
  438. read_buf |= Rx_COE_EN_;
  439. else
  440. read_buf &= ~Rx_COE_EN_;
  441. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  442. if (ret < 0) {
  443. devwarn(dev, "Failed to write COE_CR: %d", ret);
  444. return ret;
  445. }
  446. if (netif_msg_hw(dev))
  447. devdbg(dev, "COE_CR = 0x%08x", read_buf);
  448. return 0;
  449. }
  450. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  451. {
  452. return MAX_EEPROM_SIZE;
  453. }
  454. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  455. struct ethtool_eeprom *ee, u8 *data)
  456. {
  457. struct usbnet *dev = netdev_priv(netdev);
  458. ee->magic = LAN95XX_EEPROM_MAGIC;
  459. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  460. }
  461. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  462. struct ethtool_eeprom *ee, u8 *data)
  463. {
  464. struct usbnet *dev = netdev_priv(netdev);
  465. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  466. devwarn(dev, "EEPROM: magic value mismatch, magic = 0x%x",
  467. ee->magic);
  468. return -EINVAL;
  469. }
  470. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  471. }
  472. static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
  473. {
  474. struct usbnet *dev = netdev_priv(netdev);
  475. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  476. return pdata->use_rx_csum;
  477. }
  478. static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
  479. {
  480. struct usbnet *dev = netdev_priv(netdev);
  481. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  482. pdata->use_rx_csum = !!val;
  483. return smsc95xx_set_csums(dev);
  484. }
  485. static u32 smsc95xx_ethtool_get_tx_csum(struct net_device *netdev)
  486. {
  487. struct usbnet *dev = netdev_priv(netdev);
  488. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  489. return pdata->use_tx_csum;
  490. }
  491. static int smsc95xx_ethtool_set_tx_csum(struct net_device *netdev, u32 val)
  492. {
  493. struct usbnet *dev = netdev_priv(netdev);
  494. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  495. pdata->use_tx_csum = !!val;
  496. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  497. return smsc95xx_set_csums(dev);
  498. }
  499. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  500. .get_link = usbnet_get_link,
  501. .nway_reset = usbnet_nway_reset,
  502. .get_drvinfo = usbnet_get_drvinfo,
  503. .get_msglevel = usbnet_get_msglevel,
  504. .set_msglevel = usbnet_set_msglevel,
  505. .get_settings = usbnet_get_settings,
  506. .set_settings = usbnet_set_settings,
  507. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  508. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  509. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  510. .get_tx_csum = smsc95xx_ethtool_get_tx_csum,
  511. .set_tx_csum = smsc95xx_ethtool_set_tx_csum,
  512. .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
  513. .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
  514. };
  515. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  516. {
  517. struct usbnet *dev = netdev_priv(netdev);
  518. if (!netif_running(netdev))
  519. return -EINVAL;
  520. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  521. }
  522. static void smsc95xx_init_mac_address(struct usbnet *dev)
  523. {
  524. /* try reading mac address from EEPROM */
  525. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  526. dev->net->dev_addr) == 0) {
  527. if (is_valid_ether_addr(dev->net->dev_addr)) {
  528. /* eeprom values are valid so use them */
  529. if (netif_msg_ifup(dev))
  530. devdbg(dev, "MAC address read from EEPROM");
  531. return;
  532. }
  533. }
  534. /* no eeprom, or eeprom values are invalid. generate random MAC */
  535. random_ether_addr(dev->net->dev_addr);
  536. if (netif_msg_ifup(dev))
  537. devdbg(dev, "MAC address set to random_ether_addr");
  538. }
  539. static int smsc95xx_set_mac_address(struct usbnet *dev)
  540. {
  541. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  542. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  543. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  544. int ret;
  545. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  546. if (ret < 0) {
  547. devwarn(dev, "Failed to write ADDRL: %d", ret);
  548. return ret;
  549. }
  550. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  551. if (ret < 0) {
  552. devwarn(dev, "Failed to write ADDRH: %d", ret);
  553. return ret;
  554. }
  555. return 0;
  556. }
  557. /* starts the TX path */
  558. static void smsc95xx_start_tx_path(struct usbnet *dev)
  559. {
  560. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  561. unsigned long flags;
  562. u32 reg_val;
  563. /* Enable Tx at MAC */
  564. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  565. pdata->mac_cr |= MAC_CR_TXEN_;
  566. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  567. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  568. /* Enable Tx at SCSRs */
  569. reg_val = TX_CFG_ON_;
  570. smsc95xx_write_reg(dev, TX_CFG, reg_val);
  571. }
  572. /* Starts the Receive path */
  573. static void smsc95xx_start_rx_path(struct usbnet *dev)
  574. {
  575. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  576. unsigned long flags;
  577. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  578. pdata->mac_cr |= MAC_CR_RXEN_;
  579. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  580. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  581. }
  582. static int smsc95xx_phy_initialize(struct usbnet *dev)
  583. {
  584. /* Initialize MII structure */
  585. dev->mii.dev = dev->net;
  586. dev->mii.mdio_read = smsc95xx_mdio_read;
  587. dev->mii.mdio_write = smsc95xx_mdio_write;
  588. dev->mii.phy_id_mask = 0x1f;
  589. dev->mii.reg_num_mask = 0x1f;
  590. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  591. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  592. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  593. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  594. ADVERTISE_PAUSE_ASYM);
  595. /* read to clear */
  596. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  597. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  598. PHY_INT_MASK_DEFAULT_);
  599. mii_nway_restart(&dev->mii);
  600. if (netif_msg_ifup(dev))
  601. devdbg(dev, "phy initialised succesfully");
  602. return 0;
  603. }
  604. static int smsc95xx_reset(struct usbnet *dev)
  605. {
  606. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  607. struct net_device *netdev = dev->net;
  608. u32 read_buf, write_buf, burst_cap;
  609. int ret = 0, timeout;
  610. if (netif_msg_ifup(dev))
  611. devdbg(dev, "entering smsc95xx_reset");
  612. write_buf = HW_CFG_LRST_;
  613. ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
  614. if (ret < 0) {
  615. devwarn(dev, "Failed to write HW_CFG_LRST_ bit in HW_CFG "
  616. "register, ret = %d", ret);
  617. return ret;
  618. }
  619. timeout = 0;
  620. do {
  621. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  622. if (ret < 0) {
  623. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  624. return ret;
  625. }
  626. msleep(10);
  627. timeout++;
  628. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  629. if (timeout >= 100) {
  630. devwarn(dev, "timeout waiting for completion of Lite Reset");
  631. return ret;
  632. }
  633. write_buf = PM_CTL_PHY_RST_;
  634. ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
  635. if (ret < 0) {
  636. devwarn(dev, "Failed to write PM_CTRL: %d", ret);
  637. return ret;
  638. }
  639. timeout = 0;
  640. do {
  641. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  642. if (ret < 0) {
  643. devwarn(dev, "Failed to read PM_CTRL: %d", ret);
  644. return ret;
  645. }
  646. msleep(10);
  647. timeout++;
  648. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  649. if (timeout >= 100) {
  650. devwarn(dev, "timeout waiting for PHY Reset");
  651. return ret;
  652. }
  653. smsc95xx_init_mac_address(dev);
  654. ret = smsc95xx_set_mac_address(dev);
  655. if (ret < 0)
  656. return ret;
  657. if (netif_msg_ifup(dev))
  658. devdbg(dev, "MAC Address: %pM", dev->net->dev_addr);
  659. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  660. if (ret < 0) {
  661. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  662. return ret;
  663. }
  664. if (netif_msg_ifup(dev))
  665. devdbg(dev, "Read Value from HW_CFG : 0x%08x", read_buf);
  666. read_buf |= HW_CFG_BIR_;
  667. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  668. if (ret < 0) {
  669. devwarn(dev, "Failed to write HW_CFG_BIR_ bit in HW_CFG "
  670. "register, ret = %d", ret);
  671. return ret;
  672. }
  673. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  674. if (ret < 0) {
  675. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  676. return ret;
  677. }
  678. if (netif_msg_ifup(dev))
  679. devdbg(dev, "Read Value from HW_CFG after writing "
  680. "HW_CFG_BIR_: 0x%08x", read_buf);
  681. if (!turbo_mode) {
  682. burst_cap = 0;
  683. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  684. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  685. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  686. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  687. } else {
  688. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  689. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  690. }
  691. if (netif_msg_ifup(dev))
  692. devdbg(dev, "rx_urb_size=%ld", (ulong)dev->rx_urb_size);
  693. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  694. if (ret < 0) {
  695. devwarn(dev, "Failed to write BURST_CAP: %d", ret);
  696. return ret;
  697. }
  698. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  699. if (ret < 0) {
  700. devwarn(dev, "Failed to read BURST_CAP: %d", ret);
  701. return ret;
  702. }
  703. if (netif_msg_ifup(dev))
  704. devdbg(dev, "Read Value from BURST_CAP after writing: 0x%08x",
  705. read_buf);
  706. read_buf = DEFAULT_BULK_IN_DELAY;
  707. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
  708. if (ret < 0) {
  709. devwarn(dev, "ret = %d", ret);
  710. return ret;
  711. }
  712. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  713. if (ret < 0) {
  714. devwarn(dev, "Failed to read BULK_IN_DLY: %d", ret);
  715. return ret;
  716. }
  717. if (netif_msg_ifup(dev))
  718. devdbg(dev, "Read Value from BULK_IN_DLY after writing: "
  719. "0x%08x", read_buf);
  720. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  721. if (ret < 0) {
  722. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  723. return ret;
  724. }
  725. if (netif_msg_ifup(dev))
  726. devdbg(dev, "Read Value from HW_CFG: 0x%08x", read_buf);
  727. if (turbo_mode)
  728. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  729. read_buf &= ~HW_CFG_RXDOFF_;
  730. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  731. read_buf |= NET_IP_ALIGN << 9;
  732. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  733. if (ret < 0) {
  734. devwarn(dev, "Failed to write HW_CFG register, ret=%d", ret);
  735. return ret;
  736. }
  737. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  738. if (ret < 0) {
  739. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  740. return ret;
  741. }
  742. if (netif_msg_ifup(dev))
  743. devdbg(dev, "Read Value from HW_CFG after writing: 0x%08x",
  744. read_buf);
  745. write_buf = 0xFFFFFFFF;
  746. ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
  747. if (ret < 0) {
  748. devwarn(dev, "Failed to write INT_STS register, ret=%d", ret);
  749. return ret;
  750. }
  751. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  752. if (ret < 0) {
  753. devwarn(dev, "Failed to read ID_REV: %d", ret);
  754. return ret;
  755. }
  756. if (netif_msg_ifup(dev))
  757. devdbg(dev, "ID_REV = 0x%08x", read_buf);
  758. /* Configure GPIO pins as LED outputs */
  759. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  760. LED_GPIO_CFG_FDX_LED;
  761. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  762. if (ret < 0) {
  763. devwarn(dev, "Failed to write LED_GPIO_CFG register, ret=%d",
  764. ret);
  765. return ret;
  766. }
  767. /* Init Tx */
  768. write_buf = 0;
  769. ret = smsc95xx_write_reg(dev, FLOW, write_buf);
  770. if (ret < 0) {
  771. devwarn(dev, "Failed to write FLOW: %d", ret);
  772. return ret;
  773. }
  774. read_buf = AFC_CFG_DEFAULT;
  775. ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
  776. if (ret < 0) {
  777. devwarn(dev, "Failed to write AFC_CFG: %d", ret);
  778. return ret;
  779. }
  780. /* Don't need mac_cr_lock during initialisation */
  781. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  782. if (ret < 0) {
  783. devwarn(dev, "Failed to read MAC_CR: %d", ret);
  784. return ret;
  785. }
  786. /* Init Rx */
  787. /* Set Vlan */
  788. write_buf = (u32)ETH_P_8021Q;
  789. ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
  790. if (ret < 0) {
  791. devwarn(dev, "Failed to write VAN1: %d", ret);
  792. return ret;
  793. }
  794. /* Enable or disable checksum offload engines */
  795. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  796. ret = smsc95xx_set_csums(dev);
  797. if (ret < 0) {
  798. devwarn(dev, "Failed to set csum offload: %d", ret);
  799. return ret;
  800. }
  801. smsc95xx_set_multicast(dev->net);
  802. if (smsc95xx_phy_initialize(dev) < 0)
  803. return -EIO;
  804. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  805. if (ret < 0) {
  806. devwarn(dev, "Failed to read INT_EP_CTL: %d", ret);
  807. return ret;
  808. }
  809. /* enable PHY interrupts */
  810. read_buf |= INT_EP_CTL_PHY_INT_;
  811. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  812. if (ret < 0) {
  813. devwarn(dev, "Failed to write INT_EP_CTL: %d", ret);
  814. return ret;
  815. }
  816. smsc95xx_start_tx_path(dev);
  817. smsc95xx_start_rx_path(dev);
  818. if (netif_msg_ifup(dev))
  819. devdbg(dev, "smsc95xx_reset, return 0");
  820. return 0;
  821. }
  822. static const struct net_device_ops smsc95xx_netdev_ops = {
  823. .ndo_open = usbnet_open,
  824. .ndo_stop = usbnet_stop,
  825. .ndo_start_xmit = usbnet_start_xmit,
  826. .ndo_tx_timeout = usbnet_tx_timeout,
  827. .ndo_change_mtu = usbnet_change_mtu,
  828. .ndo_set_mac_address = eth_mac_addr,
  829. .ndo_validate_addr = eth_validate_addr,
  830. .ndo_do_ioctl = smsc95xx_ioctl,
  831. .ndo_set_multicast_list = smsc95xx_set_multicast,
  832. };
  833. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  834. {
  835. struct smsc95xx_priv *pdata = NULL;
  836. int ret;
  837. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  838. ret = usbnet_get_endpoints(dev, intf);
  839. if (ret < 0) {
  840. devwarn(dev, "usbnet_get_endpoints failed: %d", ret);
  841. return ret;
  842. }
  843. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  844. GFP_KERNEL);
  845. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  846. if (!pdata) {
  847. devwarn(dev, "Unable to allocate struct smsc95xx_priv");
  848. return -ENOMEM;
  849. }
  850. spin_lock_init(&pdata->mac_cr_lock);
  851. pdata->use_tx_csum = DEFAULT_TX_CSUM_ENABLE;
  852. pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
  853. /* Init all registers */
  854. ret = smsc95xx_reset(dev);
  855. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  856. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  857. dev->net->flags |= IFF_MULTICAST;
  858. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
  859. return 0;
  860. }
  861. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  862. {
  863. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  864. if (pdata) {
  865. if (netif_msg_ifdown(dev))
  866. devdbg(dev, "free pdata");
  867. kfree(pdata);
  868. pdata = NULL;
  869. dev->data[0] = 0;
  870. }
  871. }
  872. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  873. {
  874. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  875. skb->ip_summed = CHECKSUM_COMPLETE;
  876. skb_trim(skb, skb->len - 2);
  877. }
  878. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  879. {
  880. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  881. while (skb->len > 0) {
  882. u32 header, align_count;
  883. struct sk_buff *ax_skb;
  884. unsigned char *packet;
  885. u16 size;
  886. memcpy(&header, skb->data, sizeof(header));
  887. le32_to_cpus(&header);
  888. skb_pull(skb, 4 + NET_IP_ALIGN);
  889. packet = skb->data;
  890. /* get the packet length */
  891. size = (u16)((header & RX_STS_FL_) >> 16);
  892. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  893. if (unlikely(header & RX_STS_ES_)) {
  894. if (netif_msg_rx_err(dev))
  895. devdbg(dev, "Error header=0x%08x", header);
  896. dev->net->stats.rx_errors++;
  897. dev->net->stats.rx_dropped++;
  898. if (header & RX_STS_CRC_) {
  899. dev->net->stats.rx_crc_errors++;
  900. } else {
  901. if (header & (RX_STS_TL_ | RX_STS_RF_))
  902. dev->net->stats.rx_frame_errors++;
  903. if ((header & RX_STS_LE_) &&
  904. (!(header & RX_STS_FT_)))
  905. dev->net->stats.rx_length_errors++;
  906. }
  907. } else {
  908. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  909. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  910. if (netif_msg_rx_err(dev))
  911. devdbg(dev, "size err header=0x%08x",
  912. header);
  913. return 0;
  914. }
  915. /* last frame in this batch */
  916. if (skb->len == size) {
  917. if (pdata->use_rx_csum)
  918. smsc95xx_rx_csum_offload(skb);
  919. skb_trim(skb, skb->len - 4); /* remove fcs */
  920. skb->truesize = size + sizeof(struct sk_buff);
  921. return 1;
  922. }
  923. ax_skb = skb_clone(skb, GFP_ATOMIC);
  924. if (unlikely(!ax_skb)) {
  925. devwarn(dev, "Error allocating skb");
  926. return 0;
  927. }
  928. ax_skb->len = size;
  929. ax_skb->data = packet;
  930. skb_set_tail_pointer(ax_skb, size);
  931. if (pdata->use_rx_csum)
  932. smsc95xx_rx_csum_offload(ax_skb);
  933. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  934. ax_skb->truesize = size + sizeof(struct sk_buff);
  935. usbnet_skb_return(dev, ax_skb);
  936. }
  937. skb_pull(skb, size);
  938. /* padding bytes before the next frame starts */
  939. if (skb->len)
  940. skb_pull(skb, align_count);
  941. }
  942. if (unlikely(skb->len < 0)) {
  943. devwarn(dev, "invalid rx length<0 %d", skb->len);
  944. return 0;
  945. }
  946. return 1;
  947. }
  948. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  949. {
  950. int len = skb->data - skb->head;
  951. u16 high_16 = (u16)(skb->csum_offset + skb->csum_start - len);
  952. u16 low_16 = (u16)(skb->csum_start - len);
  953. return (high_16 << 16) | low_16;
  954. }
  955. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  956. struct sk_buff *skb, gfp_t flags)
  957. {
  958. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  959. bool csum = pdata->use_tx_csum && (skb->ip_summed == CHECKSUM_PARTIAL);
  960. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  961. u32 tx_cmd_a, tx_cmd_b;
  962. /* We do not advertise SG, so skbs should be already linearized */
  963. BUG_ON(skb_shinfo(skb)->nr_frags);
  964. if (skb_headroom(skb) < overhead) {
  965. struct sk_buff *skb2 = skb_copy_expand(skb,
  966. overhead, 0, flags);
  967. dev_kfree_skb_any(skb);
  968. skb = skb2;
  969. if (!skb)
  970. return NULL;
  971. }
  972. if (csum) {
  973. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  974. skb_push(skb, 4);
  975. memcpy(skb->data, &csum_preamble, 4);
  976. }
  977. skb_push(skb, 4);
  978. tx_cmd_b = (u32)(skb->len - 4);
  979. if (csum)
  980. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  981. cpu_to_le32s(&tx_cmd_b);
  982. memcpy(skb->data, &tx_cmd_b, 4);
  983. skb_push(skb, 4);
  984. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  985. TX_CMD_A_LAST_SEG_;
  986. cpu_to_le32s(&tx_cmd_a);
  987. memcpy(skb->data, &tx_cmd_a, 4);
  988. return skb;
  989. }
  990. static const struct driver_info smsc95xx_info = {
  991. .description = "smsc95xx USB 2.0 Ethernet",
  992. .bind = smsc95xx_bind,
  993. .unbind = smsc95xx_unbind,
  994. .link_reset = smsc95xx_link_reset,
  995. .reset = smsc95xx_reset,
  996. .rx_fixup = smsc95xx_rx_fixup,
  997. .tx_fixup = smsc95xx_tx_fixup,
  998. .status = smsc95xx_status,
  999. .flags = FLAG_ETHER | FLAG_SEND_ZLP,
  1000. };
  1001. static const struct usb_device_id products[] = {
  1002. {
  1003. /* SMSC9500 USB Ethernet Device */
  1004. USB_DEVICE(0x0424, 0x9500),
  1005. .driver_info = (unsigned long) &smsc95xx_info,
  1006. },
  1007. {
  1008. /* SMSC9505 USB Ethernet Device */
  1009. USB_DEVICE(0x0424, 0x9505),
  1010. .driver_info = (unsigned long) &smsc95xx_info,
  1011. },
  1012. {
  1013. /* SMSC9500A USB Ethernet Device */
  1014. USB_DEVICE(0x0424, 0x9E00),
  1015. .driver_info = (unsigned long) &smsc95xx_info,
  1016. },
  1017. {
  1018. /* SMSC9505A USB Ethernet Device */
  1019. USB_DEVICE(0x0424, 0x9E01),
  1020. .driver_info = (unsigned long) &smsc95xx_info,
  1021. },
  1022. {
  1023. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1024. USB_DEVICE(0x0424, 0xec00),
  1025. .driver_info = (unsigned long) &smsc95xx_info,
  1026. },
  1027. {
  1028. /* SMSC9500 USB Ethernet Device (SAL10) */
  1029. USB_DEVICE(0x0424, 0x9900),
  1030. .driver_info = (unsigned long) &smsc95xx_info,
  1031. },
  1032. {
  1033. /* SMSC9505 USB Ethernet Device (SAL10) */
  1034. USB_DEVICE(0x0424, 0x9901),
  1035. .driver_info = (unsigned long) &smsc95xx_info,
  1036. },
  1037. {
  1038. /* SMSC9500A USB Ethernet Device (SAL10) */
  1039. USB_DEVICE(0x0424, 0x9902),
  1040. .driver_info = (unsigned long) &smsc95xx_info,
  1041. },
  1042. {
  1043. /* SMSC9505A USB Ethernet Device (SAL10) */
  1044. USB_DEVICE(0x0424, 0x9903),
  1045. .driver_info = (unsigned long) &smsc95xx_info,
  1046. },
  1047. {
  1048. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1049. USB_DEVICE(0x0424, 0x9904),
  1050. .driver_info = (unsigned long) &smsc95xx_info,
  1051. },
  1052. {
  1053. /* SMSC9500A USB Ethernet Device (HAL) */
  1054. USB_DEVICE(0x0424, 0x9905),
  1055. .driver_info = (unsigned long) &smsc95xx_info,
  1056. },
  1057. {
  1058. /* SMSC9505A USB Ethernet Device (HAL) */
  1059. USB_DEVICE(0x0424, 0x9906),
  1060. .driver_info = (unsigned long) &smsc95xx_info,
  1061. },
  1062. {
  1063. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1064. USB_DEVICE(0x0424, 0x9907),
  1065. .driver_info = (unsigned long) &smsc95xx_info,
  1066. },
  1067. {
  1068. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1069. USB_DEVICE(0x0424, 0x9908),
  1070. .driver_info = (unsigned long) &smsc95xx_info,
  1071. },
  1072. {
  1073. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1074. USB_DEVICE(0x0424, 0x9909),
  1075. .driver_info = (unsigned long) &smsc95xx_info,
  1076. },
  1077. { }, /* END */
  1078. };
  1079. MODULE_DEVICE_TABLE(usb, products);
  1080. static struct usb_driver smsc95xx_driver = {
  1081. .name = "smsc95xx",
  1082. .id_table = products,
  1083. .probe = usbnet_probe,
  1084. .suspend = usbnet_suspend,
  1085. .resume = usbnet_resume,
  1086. .disconnect = usbnet_disconnect,
  1087. };
  1088. static int __init smsc95xx_init(void)
  1089. {
  1090. return usb_register(&smsc95xx_driver);
  1091. }
  1092. module_init(smsc95xx_init);
  1093. static void __exit smsc95xx_exit(void)
  1094. {
  1095. usb_deregister(&smsc95xx_driver);
  1096. }
  1097. module_exit(smsc95xx_exit);
  1098. MODULE_AUTHOR("Nancy Lin");
  1099. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
  1100. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1101. MODULE_LICENSE("GPL");