tehuti.c 68 KB

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  1. /*
  2. * Tehuti Networks(R) Network Driver
  3. * ethtool interface implementation
  4. * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. /*
  12. * RX HW/SW interaction overview
  13. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  14. * There are 2 types of RX communication channels betwean driver and NIC.
  15. * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
  16. * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
  17. * info about buffer's location, size and ID. An ID field is used to identify a
  18. * buffer when it's returned with data via RXD Fifo (see below)
  19. * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
  20. * filled by HW and is readen by SW. Each descriptor holds status and ID.
  21. * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
  22. * via dma moves it into host memory, builds new RXD descriptor with same ID,
  23. * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
  24. *
  25. * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
  26. * One holds 1.5K packets and another - 26K packets. Depending on incoming
  27. * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
  28. * filled with data, HW builds new RXD descriptor for it and push it into single
  29. * RXD Fifo.
  30. *
  31. * RX SW Data Structures
  32. * ~~~~~~~~~~~~~~~~~~~~~
  33. * skb db - used to keep track of all skbs owned by SW and their dma addresses.
  34. * For RX case, ownership lasts from allocating new empty skb for RXF until
  35. * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
  36. * skb db. Implemented as array with bitmask.
  37. * fifo - keeps info about fifo's size and location, relevant HW registers,
  38. * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
  39. * Implemented as simple struct.
  40. *
  41. * RX SW Execution Flow
  42. * ~~~~~~~~~~~~~~~~~~~~
  43. * Upon initialization (ifconfig up) driver creates RX fifos and initializes
  44. * relevant registers. At the end of init phase, driver enables interrupts.
  45. * NIC sees that there is no RXF buffers and raises
  46. * RD_INTR interrupt, isr fills skbs and Rx begins.
  47. * Driver has two receive operation modes:
  48. * NAPI - interrupt-driven mixed with polling
  49. * interrupt-driven only
  50. *
  51. * Interrupt-driven only flow is following. When buffer is ready, HW raises
  52. * interrupt and isr is called. isr collects all available packets
  53. * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
  54. * Rx buffer allocation note
  55. * ~~~~~~~~~~~~~~~~~~~~~~~~~
  56. * Driver cares to feed such amount of RxF descriptors that respective amount of
  57. * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
  58. * overflow check in Bordeaux for RxD fifo free/used size.
  59. * FIXME: this is NOT fully implemented, more work should be done
  60. *
  61. */
  62. #include "tehuti.h"
  63. static struct pci_device_id __devinitdata bdx_pci_tbl[] = {
  64. {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  65. {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  66. {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  67. {0}
  68. };
  69. MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
  70. /* Definitions needed by ISR or NAPI functions */
  71. static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
  72. static void bdx_tx_cleanup(struct bdx_priv *priv);
  73. static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
  74. /* Definitions needed by FW loading */
  75. static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
  76. /* Definitions needed by hw_start */
  77. static int bdx_tx_init(struct bdx_priv *priv);
  78. static int bdx_rx_init(struct bdx_priv *priv);
  79. /* Definitions needed by bdx_close */
  80. static void bdx_rx_free(struct bdx_priv *priv);
  81. static void bdx_tx_free(struct bdx_priv *priv);
  82. /* Definitions needed by bdx_probe */
  83. static void bdx_ethtool_ops(struct net_device *netdev);
  84. /*************************************************************************
  85. * Print Info *
  86. *************************************************************************/
  87. static void print_hw_id(struct pci_dev *pdev)
  88. {
  89. struct pci_nic *nic = pci_get_drvdata(pdev);
  90. u16 pci_link_status = 0;
  91. u16 pci_ctrl = 0;
  92. pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
  93. pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
  94. printk(KERN_INFO "tehuti: %s%s\n", BDX_NIC_NAME,
  95. nic->port_num == 1 ? "" : ", 2-Port");
  96. printk(KERN_INFO
  97. "tehuti: srom 0x%x fpga %d build %u lane# %d"
  98. " max_pl 0x%x mrrs 0x%x\n",
  99. readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
  100. readl(nic->regs + FPGA_SEED),
  101. GET_LINK_STATUS_LANES(pci_link_status),
  102. GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
  103. }
  104. static void print_fw_id(struct pci_nic *nic)
  105. {
  106. printk(KERN_INFO "tehuti: fw 0x%x\n", readl(nic->regs + FW_VER));
  107. }
  108. static void print_eth_id(struct net_device *ndev)
  109. {
  110. printk(KERN_INFO "%s: %s, Port %c\n", ndev->name, BDX_NIC_NAME,
  111. (ndev->if_port == 0) ? 'A' : 'B');
  112. }
  113. /*************************************************************************
  114. * Code *
  115. *************************************************************************/
  116. #define bdx_enable_interrupts(priv) \
  117. do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
  118. #define bdx_disable_interrupts(priv) \
  119. do { WRITE_REG(priv, regIMR, 0); } while (0)
  120. /* bdx_fifo_init
  121. * create TX/RX descriptor fifo for host-NIC communication.
  122. * 1K extra space is allocated at the end of the fifo to simplify
  123. * processing of descriptors that wraps around fifo's end
  124. * @priv - NIC private structure
  125. * @f - fifo to initialize
  126. * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
  127. * @reg_XXX - offsets of registers relative to base address
  128. *
  129. * Returns 0 on success, negative value on failure
  130. *
  131. */
  132. static int
  133. bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
  134. u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
  135. {
  136. u16 memsz = FIFO_SIZE * (1 << fsz_type);
  137. memset(f, 0, sizeof(struct fifo));
  138. /* pci_alloc_consistent gives us 4k-aligned memory */
  139. f->va = pci_alloc_consistent(priv->pdev,
  140. memsz + FIFO_EXTRA_SPACE, &f->da);
  141. if (!f->va) {
  142. ERR("pci_alloc_consistent failed\n");
  143. RET(-ENOMEM);
  144. }
  145. f->reg_CFG0 = reg_CFG0;
  146. f->reg_CFG1 = reg_CFG1;
  147. f->reg_RPTR = reg_RPTR;
  148. f->reg_WPTR = reg_WPTR;
  149. f->rptr = 0;
  150. f->wptr = 0;
  151. f->memsz = memsz;
  152. f->size_mask = memsz - 1;
  153. WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
  154. WRITE_REG(priv, reg_CFG1, H32_64(f->da));
  155. RET(0);
  156. }
  157. /* bdx_fifo_free - free all resources used by fifo
  158. * @priv - NIC private structure
  159. * @f - fifo to release
  160. */
  161. static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
  162. {
  163. ENTER;
  164. if (f->va) {
  165. pci_free_consistent(priv->pdev,
  166. f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
  167. f->va = NULL;
  168. }
  169. RET();
  170. }
  171. /*
  172. * bdx_link_changed - notifies OS about hw link state.
  173. * @bdx_priv - hw adapter structure
  174. */
  175. static void bdx_link_changed(struct bdx_priv *priv)
  176. {
  177. u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
  178. if (!link) {
  179. if (netif_carrier_ok(priv->ndev)) {
  180. netif_stop_queue(priv->ndev);
  181. netif_carrier_off(priv->ndev);
  182. ERR("%s: Link Down\n", priv->ndev->name);
  183. }
  184. } else {
  185. if (!netif_carrier_ok(priv->ndev)) {
  186. netif_wake_queue(priv->ndev);
  187. netif_carrier_on(priv->ndev);
  188. ERR("%s: Link Up\n", priv->ndev->name);
  189. }
  190. }
  191. }
  192. static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
  193. {
  194. if (isr & IR_RX_FREE_0) {
  195. bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
  196. DBG("RX_FREE_0\n");
  197. }
  198. if (isr & IR_LNKCHG0)
  199. bdx_link_changed(priv);
  200. if (isr & IR_PCIE_LINK)
  201. ERR("%s: PCI-E Link Fault\n", priv->ndev->name);
  202. if (isr & IR_PCIE_TOUT)
  203. ERR("%s: PCI-E Time Out\n", priv->ndev->name);
  204. }
  205. /* bdx_isr - Interrupt Service Routine for Bordeaux NIC
  206. * @irq - interrupt number
  207. * @ndev - network device
  208. * @regs - CPU registers
  209. *
  210. * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
  211. *
  212. * It reads ISR register to know interrupt reasons, and proceed them one by one.
  213. * Reasons of interest are:
  214. * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
  215. * RX_FREE - number of free Rx buffers in RXF fifo gets low
  216. * TX_FREE - packet was transmited and RXF fifo holds its descriptor
  217. */
  218. static irqreturn_t bdx_isr_napi(int irq, void *dev)
  219. {
  220. struct net_device *ndev = dev;
  221. struct bdx_priv *priv = netdev_priv(ndev);
  222. u32 isr;
  223. ENTER;
  224. isr = (READ_REG(priv, regISR) & IR_RUN);
  225. if (unlikely(!isr)) {
  226. bdx_enable_interrupts(priv);
  227. return IRQ_NONE; /* Not our interrupt */
  228. }
  229. if (isr & IR_EXTRA)
  230. bdx_isr_extra(priv, isr);
  231. if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
  232. if (likely(napi_schedule_prep(&priv->napi))) {
  233. __napi_schedule(&priv->napi);
  234. RET(IRQ_HANDLED);
  235. } else {
  236. /* NOTE: we get here if intr has slipped into window
  237. * between these lines in bdx_poll:
  238. * bdx_enable_interrupts(priv);
  239. * return 0;
  240. * currently intrs are disabled (since we read ISR),
  241. * and we have failed to register next poll.
  242. * so we read the regs to trigger chip
  243. * and allow further interupts. */
  244. READ_REG(priv, regTXF_WPTR_0);
  245. READ_REG(priv, regRXD_WPTR_0);
  246. }
  247. }
  248. bdx_enable_interrupts(priv);
  249. RET(IRQ_HANDLED);
  250. }
  251. static int bdx_poll(struct napi_struct *napi, int budget)
  252. {
  253. struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
  254. int work_done;
  255. ENTER;
  256. bdx_tx_cleanup(priv);
  257. work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
  258. if ((work_done < budget) ||
  259. (priv->napi_stop++ >= 30)) {
  260. DBG("rx poll is done. backing to isr-driven\n");
  261. /* from time to time we exit to let NAPI layer release
  262. * device lock and allow waiting tasks (eg rmmod) to advance) */
  263. priv->napi_stop = 0;
  264. napi_complete(napi);
  265. bdx_enable_interrupts(priv);
  266. }
  267. return work_done;
  268. }
  269. /* bdx_fw_load - loads firmware to NIC
  270. * @priv - NIC private structure
  271. * Firmware is loaded via TXD fifo, so it must be initialized first.
  272. * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
  273. * can have few of them). So all drivers use semaphore register to choose one
  274. * that will actually load FW to NIC.
  275. */
  276. static int bdx_fw_load(struct bdx_priv *priv)
  277. {
  278. const struct firmware *fw = NULL;
  279. int master, i;
  280. int rc;
  281. ENTER;
  282. master = READ_REG(priv, regINIT_SEMAPHORE);
  283. if (!READ_REG(priv, regINIT_STATUS) && master) {
  284. rc = request_firmware(&fw, "tehuti/firmware.bin", &priv->pdev->dev);
  285. if (rc)
  286. goto out;
  287. bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
  288. mdelay(100);
  289. }
  290. for (i = 0; i < 200; i++) {
  291. if (READ_REG(priv, regINIT_STATUS)) {
  292. rc = 0;
  293. goto out;
  294. }
  295. mdelay(2);
  296. }
  297. rc = -EIO;
  298. out:
  299. if (master)
  300. WRITE_REG(priv, regINIT_SEMAPHORE, 1);
  301. if (fw)
  302. release_firmware(fw);
  303. if (rc) {
  304. ERR("%s: firmware loading failed\n", priv->ndev->name);
  305. if (rc == -EIO)
  306. DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
  307. READ_REG(priv, regVPC),
  308. READ_REG(priv, regVIC),
  309. READ_REG(priv, regINIT_STATUS), i);
  310. RET(rc);
  311. } else {
  312. DBG("%s: firmware loading success\n", priv->ndev->name);
  313. RET(0);
  314. }
  315. }
  316. static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
  317. {
  318. u32 val;
  319. ENTER;
  320. DBG("mac0=%x mac1=%x mac2=%x\n",
  321. READ_REG(priv, regUNC_MAC0_A),
  322. READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
  323. val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
  324. WRITE_REG(priv, regUNC_MAC2_A, val);
  325. val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
  326. WRITE_REG(priv, regUNC_MAC1_A, val);
  327. val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
  328. WRITE_REG(priv, regUNC_MAC0_A, val);
  329. DBG("mac0=%x mac1=%x mac2=%x\n",
  330. READ_REG(priv, regUNC_MAC0_A),
  331. READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
  332. RET();
  333. }
  334. /* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
  335. * @priv - NIC private structure
  336. */
  337. static int bdx_hw_start(struct bdx_priv *priv)
  338. {
  339. int rc = -EIO;
  340. struct net_device *ndev = priv->ndev;
  341. ENTER;
  342. bdx_link_changed(priv);
  343. /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
  344. WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
  345. WRITE_REG(priv, regPAUSE_QUANT, 0x96);
  346. WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
  347. WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
  348. WRITE_REG(priv, regRX_FULLNESS, 0);
  349. WRITE_REG(priv, regTX_FULLNESS, 0);
  350. WRITE_REG(priv, regCTRLST,
  351. regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
  352. WRITE_REG(priv, regVGLB, 0);
  353. WRITE_REG(priv, regMAX_FRAME_A,
  354. priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
  355. DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
  356. WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
  357. WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
  358. DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
  359. WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
  360. /* Enable timer interrupt once in 2 secs. */
  361. /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
  362. bdx_restore_mac(priv->ndev, priv);
  363. WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
  364. GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
  365. #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED)
  366. if ((rc = request_irq(priv->pdev->irq, &bdx_isr_napi, BDX_IRQ_TYPE,
  367. ndev->name, ndev)))
  368. goto err_irq;
  369. bdx_enable_interrupts(priv);
  370. RET(0);
  371. err_irq:
  372. RET(rc);
  373. }
  374. static void bdx_hw_stop(struct bdx_priv *priv)
  375. {
  376. ENTER;
  377. bdx_disable_interrupts(priv);
  378. free_irq(priv->pdev->irq, priv->ndev);
  379. netif_carrier_off(priv->ndev);
  380. netif_stop_queue(priv->ndev);
  381. RET();
  382. }
  383. static int bdx_hw_reset_direct(void __iomem *regs)
  384. {
  385. u32 val, i;
  386. ENTER;
  387. /* reset sequences: read, write 1, read, write 0 */
  388. val = readl(regs + regCLKPLL);
  389. writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
  390. udelay(50);
  391. val = readl(regs + regCLKPLL);
  392. writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
  393. /* check that the PLLs are locked and reset ended */
  394. for (i = 0; i < 70; i++, mdelay(10))
  395. if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
  396. /* do any PCI-E read transaction */
  397. readl(regs + regRXD_CFG0_0);
  398. return 0;
  399. }
  400. ERR("tehuti: HW reset failed\n");
  401. return 1; /* failure */
  402. }
  403. static int bdx_hw_reset(struct bdx_priv *priv)
  404. {
  405. u32 val, i;
  406. ENTER;
  407. if (priv->port == 0) {
  408. /* reset sequences: read, write 1, read, write 0 */
  409. val = READ_REG(priv, regCLKPLL);
  410. WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
  411. udelay(50);
  412. val = READ_REG(priv, regCLKPLL);
  413. WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
  414. }
  415. /* check that the PLLs are locked and reset ended */
  416. for (i = 0; i < 70; i++, mdelay(10))
  417. if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
  418. /* do any PCI-E read transaction */
  419. READ_REG(priv, regRXD_CFG0_0);
  420. return 0;
  421. }
  422. ERR("tehuti: HW reset failed\n");
  423. return 1; /* failure */
  424. }
  425. static int bdx_sw_reset(struct bdx_priv *priv)
  426. {
  427. int i;
  428. ENTER;
  429. /* 1. load MAC (obsolete) */
  430. /* 2. disable Rx (and Tx) */
  431. WRITE_REG(priv, regGMAC_RXF_A, 0);
  432. mdelay(100);
  433. /* 3. disable port */
  434. WRITE_REG(priv, regDIS_PORT, 1);
  435. /* 4. disable queue */
  436. WRITE_REG(priv, regDIS_QU, 1);
  437. /* 5. wait until hw is disabled */
  438. for (i = 0; i < 50; i++) {
  439. if (READ_REG(priv, regRST_PORT) & 1)
  440. break;
  441. mdelay(10);
  442. }
  443. if (i == 50)
  444. ERR("%s: SW reset timeout. continuing anyway\n",
  445. priv->ndev->name);
  446. /* 6. disable intrs */
  447. WRITE_REG(priv, regRDINTCM0, 0);
  448. WRITE_REG(priv, regTDINTCM0, 0);
  449. WRITE_REG(priv, regIMR, 0);
  450. READ_REG(priv, regISR);
  451. /* 7. reset queue */
  452. WRITE_REG(priv, regRST_QU, 1);
  453. /* 8. reset port */
  454. WRITE_REG(priv, regRST_PORT, 1);
  455. /* 9. zero all read and write pointers */
  456. for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
  457. DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
  458. for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
  459. WRITE_REG(priv, i, 0);
  460. /* 10. unseet port disable */
  461. WRITE_REG(priv, regDIS_PORT, 0);
  462. /* 11. unset queue disable */
  463. WRITE_REG(priv, regDIS_QU, 0);
  464. /* 12. unset queue reset */
  465. WRITE_REG(priv, regRST_QU, 0);
  466. /* 13. unset port reset */
  467. WRITE_REG(priv, regRST_PORT, 0);
  468. /* 14. enable Rx */
  469. /* skiped. will be done later */
  470. /* 15. save MAC (obsolete) */
  471. for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
  472. DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
  473. RET(0);
  474. }
  475. /* bdx_reset - performs right type of reset depending on hw type */
  476. static int bdx_reset(struct bdx_priv *priv)
  477. {
  478. ENTER;
  479. RET((priv->pdev->device == 0x3009)
  480. ? bdx_hw_reset(priv)
  481. : bdx_sw_reset(priv));
  482. }
  483. /**
  484. * bdx_close - Disables a network interface
  485. * @netdev: network interface device structure
  486. *
  487. * Returns 0, this is not allowed to fail
  488. *
  489. * The close entry point is called when an interface is de-activated
  490. * by the OS. The hardware is still under the drivers control, but
  491. * needs to be disabled. A global MAC reset is issued to stop the
  492. * hardware, and all transmit and receive resources are freed.
  493. **/
  494. static int bdx_close(struct net_device *ndev)
  495. {
  496. struct bdx_priv *priv = NULL;
  497. ENTER;
  498. priv = netdev_priv(ndev);
  499. napi_disable(&priv->napi);
  500. bdx_reset(priv);
  501. bdx_hw_stop(priv);
  502. bdx_rx_free(priv);
  503. bdx_tx_free(priv);
  504. RET(0);
  505. }
  506. /**
  507. * bdx_open - Called when a network interface is made active
  508. * @netdev: network interface device structure
  509. *
  510. * Returns 0 on success, negative value on failure
  511. *
  512. * The open entry point is called when a network interface is made
  513. * active by the system (IFF_UP). At this point all resources needed
  514. * for transmit and receive operations are allocated, the interrupt
  515. * handler is registered with the OS, the watchdog timer is started,
  516. * and the stack is notified that the interface is ready.
  517. **/
  518. static int bdx_open(struct net_device *ndev)
  519. {
  520. struct bdx_priv *priv;
  521. int rc;
  522. ENTER;
  523. priv = netdev_priv(ndev);
  524. bdx_reset(priv);
  525. if (netif_running(ndev))
  526. netif_stop_queue(priv->ndev);
  527. if ((rc = bdx_tx_init(priv)))
  528. goto err;
  529. if ((rc = bdx_rx_init(priv)))
  530. goto err;
  531. if ((rc = bdx_fw_load(priv)))
  532. goto err;
  533. bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
  534. if ((rc = bdx_hw_start(priv)))
  535. goto err;
  536. napi_enable(&priv->napi);
  537. print_fw_id(priv->nic);
  538. RET(0);
  539. err:
  540. bdx_close(ndev);
  541. RET(rc);
  542. }
  543. static int bdx_range_check(struct bdx_priv *priv, u32 offset)
  544. {
  545. return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
  546. -EINVAL : 0;
  547. }
  548. static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
  549. {
  550. struct bdx_priv *priv = netdev_priv(ndev);
  551. u32 data[3];
  552. int error;
  553. ENTER;
  554. DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
  555. if (cmd != SIOCDEVPRIVATE) {
  556. error = copy_from_user(data, ifr->ifr_data, sizeof(data));
  557. if (error) {
  558. ERR("cant copy from user\n");
  559. RET(error);
  560. }
  561. DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
  562. }
  563. if (!capable(CAP_SYS_RAWIO))
  564. return -EPERM;
  565. switch (data[0]) {
  566. case BDX_OP_READ:
  567. error = bdx_range_check(priv, data[1]);
  568. if (error < 0)
  569. return error;
  570. data[2] = READ_REG(priv, data[1]);
  571. DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
  572. data[2]);
  573. error = copy_to_user(ifr->ifr_data, data, sizeof(data));
  574. if (error)
  575. RET(error);
  576. break;
  577. case BDX_OP_WRITE:
  578. error = bdx_range_check(priv, data[1]);
  579. if (error < 0)
  580. return error;
  581. WRITE_REG(priv, data[1], data[2]);
  582. DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
  583. break;
  584. default:
  585. RET(-EOPNOTSUPP);
  586. }
  587. return 0;
  588. }
  589. static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
  590. {
  591. ENTER;
  592. if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
  593. RET(bdx_ioctl_priv(ndev, ifr, cmd));
  594. else
  595. RET(-EOPNOTSUPP);
  596. }
  597. /*
  598. * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
  599. * by passing VLAN filter table to hardware
  600. * @ndev network device
  601. * @vid VLAN vid
  602. * @op add or kill operation
  603. */
  604. static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
  605. {
  606. struct bdx_priv *priv = netdev_priv(ndev);
  607. u32 reg, bit, val;
  608. ENTER;
  609. DBG2("vid=%d value=%d\n", (int)vid, enable);
  610. if (unlikely(vid >= 4096)) {
  611. ERR("tehuti: invalid VID: %u (> 4096)\n", vid);
  612. RET();
  613. }
  614. reg = regVLAN_0 + (vid / 32) * 4;
  615. bit = 1 << vid % 32;
  616. val = READ_REG(priv, reg);
  617. DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
  618. if (enable)
  619. val |= bit;
  620. else
  621. val &= ~bit;
  622. DBG2("new val %x\n", val);
  623. WRITE_REG(priv, reg, val);
  624. RET();
  625. }
  626. /*
  627. * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
  628. * @ndev network device
  629. * @vid VLAN vid to add
  630. */
  631. static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid)
  632. {
  633. __bdx_vlan_rx_vid(ndev, vid, 1);
  634. }
  635. /*
  636. * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
  637. * @ndev network device
  638. * @vid VLAN vid to kill
  639. */
  640. static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
  641. {
  642. __bdx_vlan_rx_vid(ndev, vid, 0);
  643. }
  644. /*
  645. * bdx_vlan_rx_register - kernel hook for adding VLAN group
  646. * @ndev network device
  647. * @grp VLAN group
  648. */
  649. static void
  650. bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
  651. {
  652. struct bdx_priv *priv = netdev_priv(ndev);
  653. ENTER;
  654. DBG("device='%s', group='%p'\n", ndev->name, grp);
  655. priv->vlgrp = grp;
  656. RET();
  657. }
  658. /**
  659. * bdx_change_mtu - Change the Maximum Transfer Unit
  660. * @netdev: network interface device structure
  661. * @new_mtu: new value for maximum frame size
  662. *
  663. * Returns 0 on success, negative on failure
  664. */
  665. static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
  666. {
  667. ENTER;
  668. if (new_mtu == ndev->mtu)
  669. RET(0);
  670. /* enforce minimum frame size */
  671. if (new_mtu < ETH_ZLEN) {
  672. ERR("%s: %s mtu %d is less then minimal %d\n",
  673. BDX_DRV_NAME, ndev->name, new_mtu, ETH_ZLEN);
  674. RET(-EINVAL);
  675. }
  676. ndev->mtu = new_mtu;
  677. if (netif_running(ndev)) {
  678. bdx_close(ndev);
  679. bdx_open(ndev);
  680. }
  681. RET(0);
  682. }
  683. static void bdx_setmulti(struct net_device *ndev)
  684. {
  685. struct bdx_priv *priv = netdev_priv(ndev);
  686. u32 rxf_val =
  687. GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
  688. int i;
  689. ENTER;
  690. /* IMF - imperfect (hash) rx multicat filter */
  691. /* PMF - perfect rx multicat filter */
  692. /* FIXME: RXE(OFF) */
  693. if (ndev->flags & IFF_PROMISC) {
  694. rxf_val |= GMAC_RX_FILTER_PRM;
  695. } else if (ndev->flags & IFF_ALLMULTI) {
  696. /* set IMF to accept all multicast frmaes */
  697. for (i = 0; i < MAC_MCST_HASH_NUM; i++)
  698. WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
  699. } else if (ndev->mc_count) {
  700. u8 hash;
  701. struct dev_mc_list *mclist;
  702. u32 reg, val;
  703. /* set IMF to deny all multicast frames */
  704. for (i = 0; i < MAC_MCST_HASH_NUM; i++)
  705. WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
  706. /* set PMF to deny all multicast frames */
  707. for (i = 0; i < MAC_MCST_NUM; i++) {
  708. WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
  709. WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
  710. }
  711. /* use PMF to accept first MAC_MCST_NUM (15) addresses */
  712. /* TBD: sort addreses and write them in ascending order
  713. * into RX_MAC_MCST regs. we skip this phase now and accept ALL
  714. * multicast frames throu IMF */
  715. mclist = ndev->mc_list;
  716. /* accept the rest of addresses throu IMF */
  717. for (; mclist; mclist = mclist->next) {
  718. hash = 0;
  719. for (i = 0; i < ETH_ALEN; i++)
  720. hash ^= mclist->dmi_addr[i];
  721. reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
  722. val = READ_REG(priv, reg);
  723. val |= (1 << (hash % 32));
  724. WRITE_REG(priv, reg, val);
  725. }
  726. } else {
  727. DBG("only own mac %d\n", ndev->mc_count);
  728. rxf_val |= GMAC_RX_FILTER_AB;
  729. }
  730. WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
  731. /* enable RX */
  732. /* FIXME: RXE(ON) */
  733. RET();
  734. }
  735. static int bdx_set_mac(struct net_device *ndev, void *p)
  736. {
  737. struct bdx_priv *priv = netdev_priv(ndev);
  738. struct sockaddr *addr = p;
  739. ENTER;
  740. /*
  741. if (netif_running(dev))
  742. return -EBUSY
  743. */
  744. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  745. bdx_restore_mac(ndev, priv);
  746. RET(0);
  747. }
  748. static int bdx_read_mac(struct bdx_priv *priv)
  749. {
  750. u16 macAddress[3], i;
  751. ENTER;
  752. macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
  753. macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
  754. macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
  755. macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
  756. macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
  757. macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
  758. for (i = 0; i < 3; i++) {
  759. priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
  760. priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
  761. }
  762. RET(0);
  763. }
  764. static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
  765. {
  766. u64 val;
  767. val = READ_REG(priv, reg);
  768. val |= ((u64) READ_REG(priv, reg + 8)) << 32;
  769. return val;
  770. }
  771. /*Do the statistics-update work*/
  772. static void bdx_update_stats(struct bdx_priv *priv)
  773. {
  774. struct bdx_stats *stats = &priv->hw_stats;
  775. u64 *stats_vector = (u64 *) stats;
  776. int i;
  777. int addr;
  778. /*Fill HW structure */
  779. addr = 0x7200;
  780. /*First 12 statistics - 0x7200 - 0x72B0 */
  781. for (i = 0; i < 12; i++) {
  782. stats_vector[i] = bdx_read_l2stat(priv, addr);
  783. addr += 0x10;
  784. }
  785. BDX_ASSERT(addr != 0x72C0);
  786. /* 0x72C0-0x72E0 RSRV */
  787. addr = 0x72F0;
  788. for (; i < 16; i++) {
  789. stats_vector[i] = bdx_read_l2stat(priv, addr);
  790. addr += 0x10;
  791. }
  792. BDX_ASSERT(addr != 0x7330);
  793. /* 0x7330-0x7360 RSRV */
  794. addr = 0x7370;
  795. for (; i < 19; i++) {
  796. stats_vector[i] = bdx_read_l2stat(priv, addr);
  797. addr += 0x10;
  798. }
  799. BDX_ASSERT(addr != 0x73A0);
  800. /* 0x73A0-0x73B0 RSRV */
  801. addr = 0x73C0;
  802. for (; i < 23; i++) {
  803. stats_vector[i] = bdx_read_l2stat(priv, addr);
  804. addr += 0x10;
  805. }
  806. BDX_ASSERT(addr != 0x7400);
  807. BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
  808. }
  809. static struct net_device_stats *bdx_get_stats(struct net_device *ndev)
  810. {
  811. struct bdx_priv *priv = netdev_priv(ndev);
  812. struct net_device_stats *net_stat = &priv->net_stats;
  813. return net_stat;
  814. }
  815. static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
  816. u16 rxd_vlan);
  817. static void print_rxfd(struct rxf_desc *rxfd);
  818. /*************************************************************************
  819. * Rx DB *
  820. *************************************************************************/
  821. static void bdx_rxdb_destroy(struct rxdb *db)
  822. {
  823. vfree(db);
  824. }
  825. static struct rxdb *bdx_rxdb_create(int nelem)
  826. {
  827. struct rxdb *db;
  828. int i;
  829. db = vmalloc(sizeof(struct rxdb)
  830. + (nelem * sizeof(int))
  831. + (nelem * sizeof(struct rx_map)));
  832. if (likely(db != NULL)) {
  833. db->stack = (int *)(db + 1);
  834. db->elems = (void *)(db->stack + nelem);
  835. db->nelem = nelem;
  836. db->top = nelem;
  837. for (i = 0; i < nelem; i++)
  838. db->stack[i] = nelem - i - 1; /* to make first allocs
  839. close to db struct*/
  840. }
  841. return db;
  842. }
  843. static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
  844. {
  845. BDX_ASSERT(db->top <= 0);
  846. return db->stack[--(db->top)];
  847. }
  848. static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
  849. {
  850. BDX_ASSERT((n < 0) || (n >= db->nelem));
  851. return db->elems + n;
  852. }
  853. static inline int bdx_rxdb_available(struct rxdb *db)
  854. {
  855. return db->top;
  856. }
  857. static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
  858. {
  859. BDX_ASSERT((n >= db->nelem) || (n < 0));
  860. db->stack[(db->top)++] = n;
  861. }
  862. /*************************************************************************
  863. * Rx Init *
  864. *************************************************************************/
  865. /* bdx_rx_init - initialize RX all related HW and SW resources
  866. * @priv - NIC private structure
  867. *
  868. * Returns 0 on success, negative value on failure
  869. *
  870. * It creates rxf and rxd fifos, update relevant HW registers, preallocate
  871. * skb for rx. It assumes that Rx is desabled in HW
  872. * funcs are grouped for better cache usage
  873. *
  874. * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
  875. * filled and packets will be dropped by nic without getting into host or
  876. * cousing interrupt. Anyway, in that condition, host has no chance to proccess
  877. * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
  878. */
  879. /* TBD: ensure proper packet size */
  880. static int bdx_rx_init(struct bdx_priv *priv)
  881. {
  882. ENTER;
  883. if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
  884. regRXD_CFG0_0, regRXD_CFG1_0,
  885. regRXD_RPTR_0, regRXD_WPTR_0))
  886. goto err_mem;
  887. if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
  888. regRXF_CFG0_0, regRXF_CFG1_0,
  889. regRXF_RPTR_0, regRXF_WPTR_0))
  890. goto err_mem;
  891. if (!
  892. (priv->rxdb =
  893. bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
  894. sizeof(struct rxf_desc))))
  895. goto err_mem;
  896. priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
  897. return 0;
  898. err_mem:
  899. ERR("%s: %s: Rx init failed\n", BDX_DRV_NAME, priv->ndev->name);
  900. return -ENOMEM;
  901. }
  902. /* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
  903. * @priv - NIC private structure
  904. * @f - RXF fifo
  905. */
  906. static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
  907. {
  908. struct rx_map *dm;
  909. struct rxdb *db = priv->rxdb;
  910. u16 i;
  911. ENTER;
  912. DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
  913. db->nelem - bdx_rxdb_available(db));
  914. while (bdx_rxdb_available(db) > 0) {
  915. i = bdx_rxdb_alloc_elem(db);
  916. dm = bdx_rxdb_addr_elem(db, i);
  917. dm->dma = 0;
  918. }
  919. for (i = 0; i < db->nelem; i++) {
  920. dm = bdx_rxdb_addr_elem(db, i);
  921. if (dm->dma) {
  922. pci_unmap_single(priv->pdev,
  923. dm->dma, f->m.pktsz,
  924. PCI_DMA_FROMDEVICE);
  925. dev_kfree_skb(dm->skb);
  926. }
  927. }
  928. }
  929. /* bdx_rx_free - release all Rx resources
  930. * @priv - NIC private structure
  931. * It assumes that Rx is desabled in HW
  932. */
  933. static void bdx_rx_free(struct bdx_priv *priv)
  934. {
  935. ENTER;
  936. if (priv->rxdb) {
  937. bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
  938. bdx_rxdb_destroy(priv->rxdb);
  939. priv->rxdb = NULL;
  940. }
  941. bdx_fifo_free(priv, &priv->rxf_fifo0.m);
  942. bdx_fifo_free(priv, &priv->rxd_fifo0.m);
  943. RET();
  944. }
  945. /*************************************************************************
  946. * Rx Engine *
  947. *************************************************************************/
  948. /* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
  949. * @priv - nic's private structure
  950. * @f - RXF fifo that needs skbs
  951. * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
  952. * skb's virtual and physical addresses are stored in skb db.
  953. * To calculate free space, func uses cached values of RPTR and WPTR
  954. * When needed, it also updates RPTR and WPTR.
  955. */
  956. /* TBD: do not update WPTR if no desc were written */
  957. static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
  958. {
  959. struct sk_buff *skb;
  960. struct rxf_desc *rxfd;
  961. struct rx_map *dm;
  962. int dno, delta, idx;
  963. struct rxdb *db = priv->rxdb;
  964. ENTER;
  965. dno = bdx_rxdb_available(db) - 1;
  966. while (dno > 0) {
  967. if (!(skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN))) {
  968. ERR("NO MEM: dev_alloc_skb failed\n");
  969. break;
  970. }
  971. skb->dev = priv->ndev;
  972. skb_reserve(skb, NET_IP_ALIGN);
  973. idx = bdx_rxdb_alloc_elem(db);
  974. dm = bdx_rxdb_addr_elem(db, idx);
  975. dm->dma = pci_map_single(priv->pdev,
  976. skb->data, f->m.pktsz,
  977. PCI_DMA_FROMDEVICE);
  978. dm->skb = skb;
  979. rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
  980. rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
  981. rxfd->va_lo = idx;
  982. rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
  983. rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
  984. rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
  985. print_rxfd(rxfd);
  986. f->m.wptr += sizeof(struct rxf_desc);
  987. delta = f->m.wptr - f->m.memsz;
  988. if (unlikely(delta >= 0)) {
  989. f->m.wptr = delta;
  990. if (delta > 0) {
  991. memcpy(f->m.va, f->m.va + f->m.memsz, delta);
  992. DBG("wrapped descriptor\n");
  993. }
  994. }
  995. dno--;
  996. }
  997. /*TBD: to do - delayed rxf wptr like in txd */
  998. WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
  999. RET();
  1000. }
  1001. static inline void
  1002. NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
  1003. struct sk_buff *skb)
  1004. {
  1005. ENTER;
  1006. DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1),
  1007. priv->vlgrp);
  1008. if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) {
  1009. DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
  1010. priv->ndev->name,
  1011. GET_RXD_VLAN_ID(rxd_vlan),
  1012. GET_RXD_VTAG(rxd_val1),
  1013. vlan_group_get_device(priv->vlgrp,
  1014. GET_RXD_VLAN_ID(rxd_vlan))->name);
  1015. /* NAPI variant of receive functions */
  1016. vlan_hwaccel_receive_skb(skb, priv->vlgrp,
  1017. GET_RXD_VLAN_TCI(rxd_vlan));
  1018. } else {
  1019. netif_receive_skb(skb);
  1020. }
  1021. }
  1022. static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
  1023. {
  1024. struct rxf_desc *rxfd;
  1025. struct rx_map *dm;
  1026. struct rxf_fifo *f;
  1027. struct rxdb *db;
  1028. struct sk_buff *skb;
  1029. int delta;
  1030. ENTER;
  1031. DBG("priv=%p rxdd=%p\n", priv, rxdd);
  1032. f = &priv->rxf_fifo0;
  1033. db = priv->rxdb;
  1034. DBG("db=%p f=%p\n", db, f);
  1035. dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
  1036. DBG("dm=%p\n", dm);
  1037. skb = dm->skb;
  1038. rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
  1039. rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
  1040. rxfd->va_lo = rxdd->va_lo;
  1041. rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
  1042. rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
  1043. rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
  1044. print_rxfd(rxfd);
  1045. f->m.wptr += sizeof(struct rxf_desc);
  1046. delta = f->m.wptr - f->m.memsz;
  1047. if (unlikely(delta >= 0)) {
  1048. f->m.wptr = delta;
  1049. if (delta > 0) {
  1050. memcpy(f->m.va, f->m.va + f->m.memsz, delta);
  1051. DBG("wrapped descriptor\n");
  1052. }
  1053. }
  1054. RET();
  1055. }
  1056. /* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
  1057. * NOTE: a special treatment is given to non-continous descriptors
  1058. * that start near the end, wraps around and continue at the beginning. a second
  1059. * part is copied right after the first, and then descriptor is interpreted as
  1060. * normal. fifo has an extra space to allow such operations
  1061. * @priv - nic's private structure
  1062. * @f - RXF fifo that needs skbs
  1063. */
  1064. /* TBD: replace memcpy func call by explicite inline asm */
  1065. static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
  1066. {
  1067. struct sk_buff *skb, *skb2;
  1068. struct rxd_desc *rxdd;
  1069. struct rx_map *dm;
  1070. struct rxf_fifo *rxf_fifo;
  1071. int tmp_len, size;
  1072. int done = 0;
  1073. int max_done = BDX_MAX_RX_DONE;
  1074. struct rxdb *db = NULL;
  1075. /* Unmarshalled descriptor - copy of descriptor in host order */
  1076. u32 rxd_val1;
  1077. u16 len;
  1078. u16 rxd_vlan;
  1079. ENTER;
  1080. max_done = budget;
  1081. f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
  1082. size = f->m.wptr - f->m.rptr;
  1083. if (size < 0)
  1084. size = f->m.memsz + size; /* size is negative :-) */
  1085. while (size > 0) {
  1086. rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
  1087. rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
  1088. len = CPU_CHIP_SWAP16(rxdd->len);
  1089. rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
  1090. print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
  1091. tmp_len = GET_RXD_BC(rxd_val1) << 3;
  1092. BDX_ASSERT(tmp_len <= 0);
  1093. size -= tmp_len;
  1094. if (size < 0) /* test for partially arrived descriptor */
  1095. break;
  1096. f->m.rptr += tmp_len;
  1097. tmp_len = f->m.rptr - f->m.memsz;
  1098. if (unlikely(tmp_len >= 0)) {
  1099. f->m.rptr = tmp_len;
  1100. if (tmp_len > 0) {
  1101. DBG("wrapped desc rptr=%d tmp_len=%d\n",
  1102. f->m.rptr, tmp_len);
  1103. memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
  1104. }
  1105. }
  1106. if (unlikely(GET_RXD_ERR(rxd_val1))) {
  1107. DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
  1108. priv->net_stats.rx_errors++;
  1109. bdx_recycle_skb(priv, rxdd);
  1110. continue;
  1111. }
  1112. rxf_fifo = &priv->rxf_fifo0;
  1113. db = priv->rxdb;
  1114. dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
  1115. skb = dm->skb;
  1116. if (len < BDX_COPYBREAK &&
  1117. (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) {
  1118. skb_reserve(skb2, NET_IP_ALIGN);
  1119. /*skb_put(skb2, len); */
  1120. pci_dma_sync_single_for_cpu(priv->pdev,
  1121. dm->dma, rxf_fifo->m.pktsz,
  1122. PCI_DMA_FROMDEVICE);
  1123. memcpy(skb2->data, skb->data, len);
  1124. bdx_recycle_skb(priv, rxdd);
  1125. skb = skb2;
  1126. } else {
  1127. pci_unmap_single(priv->pdev,
  1128. dm->dma, rxf_fifo->m.pktsz,
  1129. PCI_DMA_FROMDEVICE);
  1130. bdx_rxdb_free_elem(db, rxdd->va_lo);
  1131. }
  1132. priv->net_stats.rx_bytes += len;
  1133. skb_put(skb, len);
  1134. skb->dev = priv->ndev;
  1135. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1136. skb->protocol = eth_type_trans(skb, priv->ndev);
  1137. /* Non-IP packets aren't checksum-offloaded */
  1138. if (GET_RXD_PKT_ID(rxd_val1) == 0)
  1139. skb->ip_summed = CHECKSUM_NONE;
  1140. NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
  1141. if (++done >= max_done)
  1142. break;
  1143. }
  1144. priv->net_stats.rx_packets += done;
  1145. /* FIXME: do smth to minimize pci accesses */
  1146. WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
  1147. bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
  1148. RET(done);
  1149. }
  1150. /*************************************************************************
  1151. * Debug / Temprorary Code *
  1152. *************************************************************************/
  1153. static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
  1154. u16 rxd_vlan)
  1155. {
  1156. DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d "
  1157. "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d "
  1158. "va_lo %d va_hi %d\n",
  1159. GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
  1160. GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
  1161. GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
  1162. GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
  1163. GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
  1164. rxdd->va_hi);
  1165. }
  1166. static void print_rxfd(struct rxf_desc *rxfd)
  1167. {
  1168. DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
  1169. "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
  1170. rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
  1171. }
  1172. /*
  1173. * TX HW/SW interaction overview
  1174. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  1175. * There are 2 types of TX communication channels betwean driver and NIC.
  1176. * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
  1177. * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
  1178. *
  1179. * Currently NIC supports TSO, checksuming and gather DMA
  1180. * UFO and IP fragmentation is on the way
  1181. *
  1182. * RX SW Data Structures
  1183. * ~~~~~~~~~~~~~~~~~~~~~
  1184. * txdb - used to keep track of all skbs owned by SW and their dma addresses.
  1185. * For TX case, ownership lasts from geting packet via hard_xmit and until HW
  1186. * acknowledges sent by TXF descriptors.
  1187. * Implemented as cyclic buffer.
  1188. * fifo - keeps info about fifo's size and location, relevant HW registers,
  1189. * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
  1190. * Implemented as simple struct.
  1191. *
  1192. * TX SW Execution Flow
  1193. * ~~~~~~~~~~~~~~~~~~~~
  1194. * OS calls driver's hard_xmit method with packet to sent.
  1195. * Driver creates DMA mappings, builds TXD descriptors and kicks HW
  1196. * by updating TXD WPTR.
  1197. * When packet is sent, HW write us TXF descriptor and SW frees original skb.
  1198. * To prevent TXD fifo overflow without reading HW registers every time,
  1199. * SW deploys "tx level" technique.
  1200. * Upon strart up, tx level is initialized to TXD fifo length.
  1201. * For every sent packet, SW gets its TXD descriptor sizei
  1202. * (from precalculated array) and substructs it from tx level.
  1203. * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
  1204. * original TXD descriptor from txdb and adds it to tx level.
  1205. * When Tx level drops under some predefined treshhold, the driver
  1206. * stops the TX queue. When TX level rises above that level,
  1207. * the tx queue is enabled again.
  1208. *
  1209. * This technique avoids eccessive reading of RPTR and WPTR registers.
  1210. * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
  1211. */
  1212. /*************************************************************************
  1213. * Tx DB *
  1214. *************************************************************************/
  1215. static inline int bdx_tx_db_size(struct txdb *db)
  1216. {
  1217. int taken = db->wptr - db->rptr;
  1218. if (taken < 0)
  1219. taken = db->size + 1 + taken; /* (size + 1) equals memsz */
  1220. return db->size - taken;
  1221. }
  1222. /* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
  1223. * @d - tx data base
  1224. * @ptr - read or write pointer
  1225. */
  1226. static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
  1227. {
  1228. BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
  1229. BDX_ASSERT(*pptr != db->rptr && /* expect either read */
  1230. *pptr != db->wptr); /* or write pointer */
  1231. BDX_ASSERT(*pptr < db->start || /* pointer has to be */
  1232. *pptr >= db->end); /* in range */
  1233. ++*pptr;
  1234. if (unlikely(*pptr == db->end))
  1235. *pptr = db->start;
  1236. }
  1237. /* bdx_tx_db_inc_rptr - increment read pointer
  1238. * @d - tx data base
  1239. */
  1240. static inline void bdx_tx_db_inc_rptr(struct txdb *db)
  1241. {
  1242. BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
  1243. __bdx_tx_db_ptr_next(db, &db->rptr);
  1244. }
  1245. /* bdx_tx_db_inc_rptr - increment write pointer
  1246. * @d - tx data base
  1247. */
  1248. static inline void bdx_tx_db_inc_wptr(struct txdb *db)
  1249. {
  1250. __bdx_tx_db_ptr_next(db, &db->wptr);
  1251. BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
  1252. a result of write */
  1253. }
  1254. /* bdx_tx_db_init - creates and initializes tx db
  1255. * @d - tx data base
  1256. * @sz_type - size of tx fifo
  1257. * Returns 0 on success, error code otherwise
  1258. */
  1259. static int bdx_tx_db_init(struct txdb *d, int sz_type)
  1260. {
  1261. int memsz = FIFO_SIZE * (1 << (sz_type + 1));
  1262. d->start = vmalloc(memsz);
  1263. if (!d->start)
  1264. return -ENOMEM;
  1265. /*
  1266. * In order to differentiate between db is empty and db is full
  1267. * states at least one element should always be empty in order to
  1268. * avoid rptr == wptr which means db is empty
  1269. */
  1270. d->size = memsz / sizeof(struct tx_map) - 1;
  1271. d->end = d->start + d->size + 1; /* just after last element */
  1272. /* all dbs are created equally empty */
  1273. d->rptr = d->start;
  1274. d->wptr = d->start;
  1275. return 0;
  1276. }
  1277. /* bdx_tx_db_close - closes tx db and frees all memory
  1278. * @d - tx data base
  1279. */
  1280. static void bdx_tx_db_close(struct txdb *d)
  1281. {
  1282. BDX_ASSERT(d == NULL);
  1283. vfree(d->start);
  1284. d->start = NULL;
  1285. }
  1286. /*************************************************************************
  1287. * Tx Engine *
  1288. *************************************************************************/
  1289. /* sizes of tx desc (including padding if needed) as function
  1290. * of skb's frag number */
  1291. static struct {
  1292. u16 bytes;
  1293. u16 qwords; /* qword = 64 bit */
  1294. } txd_sizes[MAX_SKB_FRAGS + 1];
  1295. /* txdb_map_skb - creates and stores dma mappings for skb's data blocks
  1296. * @priv - NIC private structure
  1297. * @skb - socket buffer to map
  1298. *
  1299. * It makes dma mappings for skb's data blocks and writes them to PBL of
  1300. * new tx descriptor. It also stores them in the tx db, so they could be
  1301. * unmaped after data was sent. It is reponsibility of a caller to make
  1302. * sure that there is enough space in the tx db. Last element holds pointer
  1303. * to skb itself and marked with zero length
  1304. */
  1305. static inline void
  1306. bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
  1307. struct txd_desc *txdd)
  1308. {
  1309. struct txdb *db = &priv->txdb;
  1310. struct pbl *pbl = &txdd->pbl[0];
  1311. int nr_frags = skb_shinfo(skb)->nr_frags;
  1312. int i;
  1313. db->wptr->len = skb->len - skb->data_len;
  1314. db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
  1315. db->wptr->len, PCI_DMA_TODEVICE);
  1316. pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
  1317. pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
  1318. pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
  1319. DBG("=== pbl len: 0x%x ================\n", pbl->len);
  1320. DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
  1321. DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
  1322. bdx_tx_db_inc_wptr(db);
  1323. for (i = 0; i < nr_frags; i++) {
  1324. struct skb_frag_struct *frag;
  1325. frag = &skb_shinfo(skb)->frags[i];
  1326. db->wptr->len = frag->size;
  1327. db->wptr->addr.dma =
  1328. pci_map_page(priv->pdev, frag->page, frag->page_offset,
  1329. frag->size, PCI_DMA_TODEVICE);
  1330. pbl++;
  1331. pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
  1332. pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
  1333. pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
  1334. bdx_tx_db_inc_wptr(db);
  1335. }
  1336. /* add skb clean up info. */
  1337. db->wptr->len = -txd_sizes[nr_frags].bytes;
  1338. db->wptr->addr.skb = skb;
  1339. bdx_tx_db_inc_wptr(db);
  1340. }
  1341. /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
  1342. * number of frags is used as index to fetch correct descriptors size,
  1343. * instead of calculating it each time */
  1344. static void __init init_txd_sizes(void)
  1345. {
  1346. int i, lwords;
  1347. /* 7 - is number of lwords in txd with one phys buffer
  1348. * 3 - is number of lwords used for every additional phys buffer */
  1349. for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
  1350. lwords = 7 + (i * 3);
  1351. if (lwords & 1)
  1352. lwords++; /* pad it with 1 lword */
  1353. txd_sizes[i].qwords = lwords >> 1;
  1354. txd_sizes[i].bytes = lwords << 2;
  1355. }
  1356. }
  1357. /* bdx_tx_init - initialize all Tx related stuff.
  1358. * Namely, TXD and TXF fifos, database etc */
  1359. static int bdx_tx_init(struct bdx_priv *priv)
  1360. {
  1361. if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
  1362. regTXD_CFG0_0,
  1363. regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
  1364. goto err_mem;
  1365. if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
  1366. regTXF_CFG0_0,
  1367. regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
  1368. goto err_mem;
  1369. /* The TX db has to keep mappings for all packets sent (on TxD)
  1370. * and not yet reclaimed (on TxF) */
  1371. if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
  1372. goto err_mem;
  1373. priv->tx_level = BDX_MAX_TX_LEVEL;
  1374. #ifdef BDX_DELAY_WPTR
  1375. priv->tx_update_mark = priv->tx_level - 1024;
  1376. #endif
  1377. return 0;
  1378. err_mem:
  1379. ERR("tehuti: %s: Tx init failed\n", priv->ndev->name);
  1380. return -ENOMEM;
  1381. }
  1382. /*
  1383. * bdx_tx_space - calculates avalable space in TX fifo
  1384. * @priv - NIC private structure
  1385. * Returns avaliable space in TX fifo in bytes
  1386. */
  1387. static inline int bdx_tx_space(struct bdx_priv *priv)
  1388. {
  1389. struct txd_fifo *f = &priv->txd_fifo0;
  1390. int fsize;
  1391. f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
  1392. fsize = f->m.rptr - f->m.wptr;
  1393. if (fsize <= 0)
  1394. fsize = f->m.memsz + fsize;
  1395. return (fsize);
  1396. }
  1397. /* bdx_tx_transmit - send packet to NIC
  1398. * @skb - packet to send
  1399. * ndev - network device assigned to NIC
  1400. * Return codes:
  1401. * o NETDEV_TX_OK everything ok.
  1402. * o NETDEV_TX_BUSY Cannot transmit packet, try later
  1403. * Usually a bug, means queue start/stop flow control is broken in
  1404. * the driver. Note: the driver must NOT put the skb in its DMA ring.
  1405. * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
  1406. */
  1407. static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
  1408. struct net_device *ndev)
  1409. {
  1410. struct bdx_priv *priv = netdev_priv(ndev);
  1411. struct txd_fifo *f = &priv->txd_fifo0;
  1412. int txd_checksum = 7; /* full checksum */
  1413. int txd_lgsnd = 0;
  1414. int txd_vlan_id = 0;
  1415. int txd_vtag = 0;
  1416. int txd_mss = 0;
  1417. int nr_frags = skb_shinfo(skb)->nr_frags;
  1418. struct txd_desc *txdd;
  1419. int len;
  1420. unsigned long flags;
  1421. ENTER;
  1422. local_irq_save(flags);
  1423. if (!spin_trylock(&priv->tx_lock)) {
  1424. local_irq_restore(flags);
  1425. DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
  1426. BDX_DRV_NAME, ndev->name);
  1427. return NETDEV_TX_LOCKED;
  1428. }
  1429. /* build tx descriptor */
  1430. BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
  1431. txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
  1432. if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
  1433. txd_checksum = 0;
  1434. if (skb_shinfo(skb)->gso_size) {
  1435. txd_mss = skb_shinfo(skb)->gso_size;
  1436. txd_lgsnd = 1;
  1437. DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
  1438. txd_mss);
  1439. }
  1440. if (vlan_tx_tag_present(skb)) {
  1441. /*Cut VLAN ID to 12 bits */
  1442. txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12);
  1443. txd_vtag = 1;
  1444. }
  1445. txdd->length = CPU_CHIP_SWAP16(skb->len);
  1446. txdd->mss = CPU_CHIP_SWAP16(txd_mss);
  1447. txdd->txd_val1 =
  1448. CPU_CHIP_SWAP32(TXD_W1_VAL
  1449. (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
  1450. txd_lgsnd, txd_vlan_id));
  1451. DBG("=== TxD desc =====================\n");
  1452. DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
  1453. DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
  1454. bdx_tx_map_skb(priv, skb, txdd);
  1455. /* increment TXD write pointer. In case of
  1456. fifo wrapping copy reminder of the descriptor
  1457. to the beginning */
  1458. f->m.wptr += txd_sizes[nr_frags].bytes;
  1459. len = f->m.wptr - f->m.memsz;
  1460. if (unlikely(len >= 0)) {
  1461. f->m.wptr = len;
  1462. if (len > 0) {
  1463. BDX_ASSERT(len > f->m.memsz);
  1464. memcpy(f->m.va, f->m.va + f->m.memsz, len);
  1465. }
  1466. }
  1467. BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
  1468. priv->tx_level -= txd_sizes[nr_frags].bytes;
  1469. BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
  1470. #ifdef BDX_DELAY_WPTR
  1471. if (priv->tx_level > priv->tx_update_mark) {
  1472. /* Force memory writes to complete before letting h/w
  1473. know there are new descriptors to fetch.
  1474. (might be needed on platforms like IA64)
  1475. wmb(); */
  1476. WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
  1477. } else {
  1478. if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
  1479. priv->tx_noupd = 0;
  1480. WRITE_REG(priv, f->m.reg_WPTR,
  1481. f->m.wptr & TXF_WPTR_WR_PTR);
  1482. }
  1483. }
  1484. #else
  1485. /* Force memory writes to complete before letting h/w
  1486. know there are new descriptors to fetch.
  1487. (might be needed on platforms like IA64)
  1488. wmb(); */
  1489. WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
  1490. #endif
  1491. #ifdef BDX_LLTX
  1492. ndev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
  1493. #endif
  1494. priv->net_stats.tx_packets++;
  1495. priv->net_stats.tx_bytes += skb->len;
  1496. if (priv->tx_level < BDX_MIN_TX_LEVEL) {
  1497. DBG("%s: %s: TX Q STOP level %d\n",
  1498. BDX_DRV_NAME, ndev->name, priv->tx_level);
  1499. netif_stop_queue(ndev);
  1500. }
  1501. spin_unlock_irqrestore(&priv->tx_lock, flags);
  1502. return NETDEV_TX_OK;
  1503. }
  1504. /* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
  1505. * @priv - bdx adapter
  1506. * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
  1507. * that those packets were sent
  1508. */
  1509. static void bdx_tx_cleanup(struct bdx_priv *priv)
  1510. {
  1511. struct txf_fifo *f = &priv->txf_fifo0;
  1512. struct txdb *db = &priv->txdb;
  1513. int tx_level = 0;
  1514. ENTER;
  1515. f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
  1516. BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
  1517. while (f->m.wptr != f->m.rptr) {
  1518. f->m.rptr += BDX_TXF_DESC_SZ;
  1519. f->m.rptr &= f->m.size_mask;
  1520. /* unmap all the fragments */
  1521. /* first has to come tx_maps containing dma */
  1522. BDX_ASSERT(db->rptr->len == 0);
  1523. do {
  1524. BDX_ASSERT(db->rptr->addr.dma == 0);
  1525. pci_unmap_page(priv->pdev, db->rptr->addr.dma,
  1526. db->rptr->len, PCI_DMA_TODEVICE);
  1527. bdx_tx_db_inc_rptr(db);
  1528. } while (db->rptr->len > 0);
  1529. tx_level -= db->rptr->len; /* '-' koz len is negative */
  1530. /* now should come skb pointer - free it */
  1531. dev_kfree_skb_irq(db->rptr->addr.skb);
  1532. bdx_tx_db_inc_rptr(db);
  1533. }
  1534. /* let h/w know which TXF descriptors were cleaned */
  1535. BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
  1536. WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
  1537. /* We reclaimed resources, so in case the Q is stopped by xmit callback,
  1538. * we resume the transmition and use tx_lock to synchronize with xmit.*/
  1539. spin_lock(&priv->tx_lock);
  1540. priv->tx_level += tx_level;
  1541. BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
  1542. #ifdef BDX_DELAY_WPTR
  1543. if (priv->tx_noupd) {
  1544. priv->tx_noupd = 0;
  1545. WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
  1546. priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
  1547. }
  1548. #endif
  1549. if (unlikely(netif_queue_stopped(priv->ndev)
  1550. && netif_carrier_ok(priv->ndev)
  1551. && (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
  1552. DBG("%s: %s: TX Q WAKE level %d\n",
  1553. BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
  1554. netif_wake_queue(priv->ndev);
  1555. }
  1556. spin_unlock(&priv->tx_lock);
  1557. }
  1558. /* bdx_tx_free_skbs - frees all skbs from TXD fifo.
  1559. * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
  1560. */
  1561. static void bdx_tx_free_skbs(struct bdx_priv *priv)
  1562. {
  1563. struct txdb *db = &priv->txdb;
  1564. ENTER;
  1565. while (db->rptr != db->wptr) {
  1566. if (likely(db->rptr->len))
  1567. pci_unmap_page(priv->pdev, db->rptr->addr.dma,
  1568. db->rptr->len, PCI_DMA_TODEVICE);
  1569. else
  1570. dev_kfree_skb(db->rptr->addr.skb);
  1571. bdx_tx_db_inc_rptr(db);
  1572. }
  1573. RET();
  1574. }
  1575. /* bdx_tx_free - frees all Tx resources */
  1576. static void bdx_tx_free(struct bdx_priv *priv)
  1577. {
  1578. ENTER;
  1579. bdx_tx_free_skbs(priv);
  1580. bdx_fifo_free(priv, &priv->txd_fifo0.m);
  1581. bdx_fifo_free(priv, &priv->txf_fifo0.m);
  1582. bdx_tx_db_close(&priv->txdb);
  1583. }
  1584. /* bdx_tx_push_desc - push descriptor to TxD fifo
  1585. * @priv - NIC private structure
  1586. * @data - desc's data
  1587. * @size - desc's size
  1588. *
  1589. * Pushes desc to TxD fifo and overlaps it if needed.
  1590. * NOTE: this func does not check for available space. this is responsibility
  1591. * of the caller. Neither does it check that data size is smaller than
  1592. * fifo size.
  1593. */
  1594. static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
  1595. {
  1596. struct txd_fifo *f = &priv->txd_fifo0;
  1597. int i = f->m.memsz - f->m.wptr;
  1598. if (size == 0)
  1599. return;
  1600. if (i > size) {
  1601. memcpy(f->m.va + f->m.wptr, data, size);
  1602. f->m.wptr += size;
  1603. } else {
  1604. memcpy(f->m.va + f->m.wptr, data, i);
  1605. f->m.wptr = size - i;
  1606. memcpy(f->m.va, data + i, f->m.wptr);
  1607. }
  1608. WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
  1609. }
  1610. /* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
  1611. * @priv - NIC private structure
  1612. * @data - desc's data
  1613. * @size - desc's size
  1614. *
  1615. * NOTE: this func does check for available space and, if neccessary, waits for
  1616. * NIC to read existing data before writing new one.
  1617. */
  1618. static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
  1619. {
  1620. int timer = 0;
  1621. ENTER;
  1622. while (size > 0) {
  1623. /* we substruct 8 because when fifo is full rptr == wptr
  1624. which also means that fifo is empty, we can understand
  1625. the difference, but could hw do the same ??? :) */
  1626. int avail = bdx_tx_space(priv) - 8;
  1627. if (avail <= 0) {
  1628. if (timer++ > 300) { /* prevent endless loop */
  1629. DBG("timeout while writing desc to TxD fifo\n");
  1630. break;
  1631. }
  1632. udelay(50); /* give hw a chance to clean fifo */
  1633. continue;
  1634. }
  1635. avail = MIN(avail, size);
  1636. DBG("about to push %d bytes starting %p size %d\n", avail,
  1637. data, size);
  1638. bdx_tx_push_desc(priv, data, avail);
  1639. size -= avail;
  1640. data += avail;
  1641. }
  1642. RET();
  1643. }
  1644. static const struct net_device_ops bdx_netdev_ops = {
  1645. .ndo_open = bdx_open,
  1646. .ndo_stop = bdx_close,
  1647. .ndo_start_xmit = bdx_tx_transmit,
  1648. .ndo_validate_addr = eth_validate_addr,
  1649. .ndo_do_ioctl = bdx_ioctl,
  1650. .ndo_set_multicast_list = bdx_setmulti,
  1651. .ndo_get_stats = bdx_get_stats,
  1652. .ndo_change_mtu = bdx_change_mtu,
  1653. .ndo_set_mac_address = bdx_set_mac,
  1654. .ndo_vlan_rx_register = bdx_vlan_rx_register,
  1655. .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
  1656. .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
  1657. };
  1658. /**
  1659. * bdx_probe - Device Initialization Routine
  1660. * @pdev: PCI device information struct
  1661. * @ent: entry in bdx_pci_tbl
  1662. *
  1663. * Returns 0 on success, negative on failure
  1664. *
  1665. * bdx_probe initializes an adapter identified by a pci_dev structure.
  1666. * The OS initialization, configuring of the adapter private structure,
  1667. * and a hardware reset occur.
  1668. *
  1669. * functions and their order used as explained in
  1670. * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
  1671. *
  1672. */
  1673. /* TBD: netif_msg should be checked and implemented. I disable it for now */
  1674. static int __devinit
  1675. bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1676. {
  1677. struct net_device *ndev;
  1678. struct bdx_priv *priv;
  1679. int err, pci_using_dac, port;
  1680. unsigned long pciaddr;
  1681. u32 regionSize;
  1682. struct pci_nic *nic;
  1683. ENTER;
  1684. nic = vmalloc(sizeof(*nic));
  1685. if (!nic)
  1686. RET(-ENOMEM);
  1687. /************** pci *****************/
  1688. if ((err = pci_enable_device(pdev))) /* it trigers interrupt, dunno why. */
  1689. goto err_pci; /* it's not a problem though */
  1690. if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
  1691. !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
  1692. pci_using_dac = 1;
  1693. } else {
  1694. if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
  1695. (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
  1696. printk(KERN_ERR "tehuti: No usable DMA configuration"
  1697. ", aborting\n");
  1698. goto err_dma;
  1699. }
  1700. pci_using_dac = 0;
  1701. }
  1702. if ((err = pci_request_regions(pdev, BDX_DRV_NAME)))
  1703. goto err_dma;
  1704. pci_set_master(pdev);
  1705. pciaddr = pci_resource_start(pdev, 0);
  1706. if (!pciaddr) {
  1707. err = -EIO;
  1708. ERR("tehuti: no MMIO resource\n");
  1709. goto err_out_res;
  1710. }
  1711. if ((regionSize = pci_resource_len(pdev, 0)) < BDX_REGS_SIZE) {
  1712. err = -EIO;
  1713. ERR("tehuti: MMIO resource (%x) too small\n", regionSize);
  1714. goto err_out_res;
  1715. }
  1716. nic->regs = ioremap(pciaddr, regionSize);
  1717. if (!nic->regs) {
  1718. err = -EIO;
  1719. ERR("tehuti: ioremap failed\n");
  1720. goto err_out_res;
  1721. }
  1722. if (pdev->irq < 2) {
  1723. err = -EIO;
  1724. ERR("tehuti: invalid irq (%d)\n", pdev->irq);
  1725. goto err_out_iomap;
  1726. }
  1727. pci_set_drvdata(pdev, nic);
  1728. if (pdev->device == 0x3014)
  1729. nic->port_num = 2;
  1730. else
  1731. nic->port_num = 1;
  1732. print_hw_id(pdev);
  1733. bdx_hw_reset_direct(nic->regs);
  1734. nic->irq_type = IRQ_INTX;
  1735. #ifdef BDX_MSI
  1736. if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
  1737. if ((err = pci_enable_msi(pdev)))
  1738. ERR("Tehuti: Can't eneble msi. error is %d\n", err);
  1739. else
  1740. nic->irq_type = IRQ_MSI;
  1741. } else
  1742. DBG("HW does not support MSI\n");
  1743. #endif
  1744. /************** netdev **************/
  1745. for (port = 0; port < nic->port_num; port++) {
  1746. if (!(ndev = alloc_etherdev(sizeof(struct bdx_priv)))) {
  1747. err = -ENOMEM;
  1748. printk(KERN_ERR "tehuti: alloc_etherdev failed\n");
  1749. goto err_out_iomap;
  1750. }
  1751. ndev->netdev_ops = &bdx_netdev_ops;
  1752. ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
  1753. bdx_ethtool_ops(ndev); /* ethtool interface */
  1754. /* these fields are used for info purposes only
  1755. * so we can have them same for all ports of the board */
  1756. ndev->if_port = port;
  1757. ndev->base_addr = pciaddr;
  1758. ndev->mem_start = pciaddr;
  1759. ndev->mem_end = pciaddr + regionSize;
  1760. ndev->irq = pdev->irq;
  1761. ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
  1762. | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
  1763. NETIF_F_HW_VLAN_FILTER
  1764. /*| NETIF_F_FRAGLIST */
  1765. ;
  1766. if (pci_using_dac)
  1767. ndev->features |= NETIF_F_HIGHDMA;
  1768. /************** priv ****************/
  1769. priv = nic->priv[port] = netdev_priv(ndev);
  1770. memset(priv, 0, sizeof(struct bdx_priv));
  1771. priv->pBdxRegs = nic->regs + port * 0x8000;
  1772. priv->port = port;
  1773. priv->pdev = pdev;
  1774. priv->ndev = ndev;
  1775. priv->nic = nic;
  1776. priv->msg_enable = BDX_DEF_MSG_ENABLE;
  1777. netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
  1778. if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
  1779. DBG("HW statistics not supported\n");
  1780. priv->stats_flag = 0;
  1781. } else {
  1782. priv->stats_flag = 1;
  1783. }
  1784. /* Initialize fifo sizes. */
  1785. priv->txd_size = 2;
  1786. priv->txf_size = 2;
  1787. priv->rxd_size = 2;
  1788. priv->rxf_size = 3;
  1789. /* Initialize the initial coalescing registers. */
  1790. priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
  1791. priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
  1792. /* ndev->xmit_lock spinlock is not used.
  1793. * Private priv->tx_lock is used for synchronization
  1794. * between transmit and TX irq cleanup. In addition
  1795. * set multicast list callback has to use priv->tx_lock.
  1796. */
  1797. #ifdef BDX_LLTX
  1798. ndev->features |= NETIF_F_LLTX;
  1799. #endif
  1800. spin_lock_init(&priv->tx_lock);
  1801. /*bdx_hw_reset(priv); */
  1802. if (bdx_read_mac(priv)) {
  1803. printk(KERN_ERR "tehuti: load MAC address failed\n");
  1804. goto err_out_iomap;
  1805. }
  1806. SET_NETDEV_DEV(ndev, &pdev->dev);
  1807. if ((err = register_netdev(ndev))) {
  1808. printk(KERN_ERR "tehuti: register_netdev failed\n");
  1809. goto err_out_free;
  1810. }
  1811. netif_carrier_off(ndev);
  1812. netif_stop_queue(ndev);
  1813. print_eth_id(ndev);
  1814. }
  1815. RET(0);
  1816. err_out_free:
  1817. free_netdev(ndev);
  1818. err_out_iomap:
  1819. iounmap(nic->regs);
  1820. err_out_res:
  1821. pci_release_regions(pdev);
  1822. err_dma:
  1823. pci_disable_device(pdev);
  1824. err_pci:
  1825. vfree(nic);
  1826. RET(err);
  1827. }
  1828. /****************** Ethtool interface *********************/
  1829. /* get strings for tests */
  1830. static const char
  1831. bdx_test_names[][ETH_GSTRING_LEN] = {
  1832. "No tests defined"
  1833. };
  1834. /* get strings for statistics counters */
  1835. static const char
  1836. bdx_stat_names[][ETH_GSTRING_LEN] = {
  1837. "InUCast", /* 0x7200 */
  1838. "InMCast", /* 0x7210 */
  1839. "InBCast", /* 0x7220 */
  1840. "InPkts", /* 0x7230 */
  1841. "InErrors", /* 0x7240 */
  1842. "InDropped", /* 0x7250 */
  1843. "FrameTooLong", /* 0x7260 */
  1844. "FrameSequenceErrors", /* 0x7270 */
  1845. "InVLAN", /* 0x7280 */
  1846. "InDroppedDFE", /* 0x7290 */
  1847. "InDroppedIntFull", /* 0x72A0 */
  1848. "InFrameAlignErrors", /* 0x72B0 */
  1849. /* 0x72C0-0x72E0 RSRV */
  1850. "OutUCast", /* 0x72F0 */
  1851. "OutMCast", /* 0x7300 */
  1852. "OutBCast", /* 0x7310 */
  1853. "OutPkts", /* 0x7320 */
  1854. /* 0x7330-0x7360 RSRV */
  1855. "OutVLAN", /* 0x7370 */
  1856. "InUCastOctects", /* 0x7380 */
  1857. "OutUCastOctects", /* 0x7390 */
  1858. /* 0x73A0-0x73B0 RSRV */
  1859. "InBCastOctects", /* 0x73C0 */
  1860. "OutBCastOctects", /* 0x73D0 */
  1861. "InOctects", /* 0x73E0 */
  1862. "OutOctects", /* 0x73F0 */
  1863. };
  1864. /*
  1865. * bdx_get_settings - get device-specific settings
  1866. * @netdev
  1867. * @ecmd
  1868. */
  1869. static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
  1870. {
  1871. u32 rdintcm;
  1872. u32 tdintcm;
  1873. struct bdx_priv *priv = netdev_priv(netdev);
  1874. rdintcm = priv->rdintcm;
  1875. tdintcm = priv->tdintcm;
  1876. ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  1877. ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
  1878. ecmd->speed = SPEED_10000;
  1879. ecmd->duplex = DUPLEX_FULL;
  1880. ecmd->port = PORT_FIBRE;
  1881. ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
  1882. ecmd->autoneg = AUTONEG_DISABLE;
  1883. /* PCK_TH measures in multiples of FIFO bytes
  1884. We translate to packets */
  1885. ecmd->maxtxpkt =
  1886. ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
  1887. ecmd->maxrxpkt =
  1888. ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
  1889. return 0;
  1890. }
  1891. /*
  1892. * bdx_get_drvinfo - report driver information
  1893. * @netdev
  1894. * @drvinfo
  1895. */
  1896. static void
  1897. bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
  1898. {
  1899. struct bdx_priv *priv = netdev_priv(netdev);
  1900. strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
  1901. strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
  1902. strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
  1903. strlcat(drvinfo->bus_info, pci_name(priv->pdev),
  1904. sizeof(drvinfo->bus_info));
  1905. drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
  1906. drvinfo->testinfo_len = 0;
  1907. drvinfo->regdump_len = 0;
  1908. drvinfo->eedump_len = 0;
  1909. }
  1910. /*
  1911. * bdx_get_rx_csum - report whether receive checksums are turned on or off
  1912. * @netdev
  1913. */
  1914. static u32 bdx_get_rx_csum(struct net_device *netdev)
  1915. {
  1916. return 1; /* always on */
  1917. }
  1918. /*
  1919. * bdx_get_tx_csum - report whether transmit checksums are turned on or off
  1920. * @netdev
  1921. */
  1922. static u32 bdx_get_tx_csum(struct net_device *netdev)
  1923. {
  1924. return (netdev->features & NETIF_F_IP_CSUM) != 0;
  1925. }
  1926. /*
  1927. * bdx_get_coalesce - get interrupt coalescing parameters
  1928. * @netdev
  1929. * @ecoal
  1930. */
  1931. static int
  1932. bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
  1933. {
  1934. u32 rdintcm;
  1935. u32 tdintcm;
  1936. struct bdx_priv *priv = netdev_priv(netdev);
  1937. rdintcm = priv->rdintcm;
  1938. tdintcm = priv->tdintcm;
  1939. /* PCK_TH measures in multiples of FIFO bytes
  1940. We translate to packets */
  1941. ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
  1942. ecoal->rx_max_coalesced_frames =
  1943. ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
  1944. ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
  1945. ecoal->tx_max_coalesced_frames =
  1946. ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
  1947. /* adaptive parameters ignored */
  1948. return 0;
  1949. }
  1950. /*
  1951. * bdx_set_coalesce - set interrupt coalescing parameters
  1952. * @netdev
  1953. * @ecoal
  1954. */
  1955. static int
  1956. bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
  1957. {
  1958. u32 rdintcm;
  1959. u32 tdintcm;
  1960. struct bdx_priv *priv = netdev_priv(netdev);
  1961. int rx_coal;
  1962. int tx_coal;
  1963. int rx_max_coal;
  1964. int tx_max_coal;
  1965. /* Check for valid input */
  1966. rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
  1967. tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
  1968. rx_max_coal = ecoal->rx_max_coalesced_frames;
  1969. tx_max_coal = ecoal->tx_max_coalesced_frames;
  1970. /* Translate from packets to multiples of FIFO bytes */
  1971. rx_max_coal =
  1972. (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
  1973. / PCK_TH_MULT);
  1974. tx_max_coal =
  1975. (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
  1976. / PCK_TH_MULT);
  1977. if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF)
  1978. || (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
  1979. return -EINVAL;
  1980. rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
  1981. GET_RXF_TH(priv->rdintcm), rx_max_coal);
  1982. tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
  1983. tx_max_coal);
  1984. priv->rdintcm = rdintcm;
  1985. priv->tdintcm = tdintcm;
  1986. WRITE_REG(priv, regRDINTCM0, rdintcm);
  1987. WRITE_REG(priv, regTDINTCM0, tdintcm);
  1988. return 0;
  1989. }
  1990. /* Convert RX fifo size to number of pending packets */
  1991. static inline int bdx_rx_fifo_size_to_packets(int rx_size)
  1992. {
  1993. return ((FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc));
  1994. }
  1995. /* Convert TX fifo size to number of pending packets */
  1996. static inline int bdx_tx_fifo_size_to_packets(int tx_size)
  1997. {
  1998. return ((FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ);
  1999. }
  2000. /*
  2001. * bdx_get_ringparam - report ring sizes
  2002. * @netdev
  2003. * @ring
  2004. */
  2005. static void
  2006. bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
  2007. {
  2008. struct bdx_priv *priv = netdev_priv(netdev);
  2009. /*max_pending - the maximum-sized FIFO we allow */
  2010. ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
  2011. ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
  2012. ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
  2013. ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
  2014. }
  2015. /*
  2016. * bdx_set_ringparam - set ring sizes
  2017. * @netdev
  2018. * @ring
  2019. */
  2020. static int
  2021. bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
  2022. {
  2023. struct bdx_priv *priv = netdev_priv(netdev);
  2024. int rx_size = 0;
  2025. int tx_size = 0;
  2026. for (; rx_size < 4; rx_size++) {
  2027. if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
  2028. break;
  2029. }
  2030. if (rx_size == 4)
  2031. rx_size = 3;
  2032. for (; tx_size < 4; tx_size++) {
  2033. if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
  2034. break;
  2035. }
  2036. if (tx_size == 4)
  2037. tx_size = 3;
  2038. /*Is there anything to do? */
  2039. if ((rx_size == priv->rxf_size)
  2040. && (tx_size == priv->txd_size))
  2041. return 0;
  2042. priv->rxf_size = rx_size;
  2043. if (rx_size > 1)
  2044. priv->rxd_size = rx_size - 1;
  2045. else
  2046. priv->rxd_size = rx_size;
  2047. priv->txf_size = priv->txd_size = tx_size;
  2048. if (netif_running(netdev)) {
  2049. bdx_close(netdev);
  2050. bdx_open(netdev);
  2051. }
  2052. return 0;
  2053. }
  2054. /*
  2055. * bdx_get_strings - return a set of strings that describe the requested objects
  2056. * @netdev
  2057. * @data
  2058. */
  2059. static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
  2060. {
  2061. switch (stringset) {
  2062. case ETH_SS_TEST:
  2063. memcpy(data, *bdx_test_names, sizeof(bdx_test_names));
  2064. break;
  2065. case ETH_SS_STATS:
  2066. memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
  2067. break;
  2068. }
  2069. }
  2070. /*
  2071. * bdx_get_stats_count - return number of 64bit statistics counters
  2072. * @netdev
  2073. */
  2074. static int bdx_get_stats_count(struct net_device *netdev)
  2075. {
  2076. struct bdx_priv *priv = netdev_priv(netdev);
  2077. BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
  2078. != sizeof(struct bdx_stats) / sizeof(u64));
  2079. return ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
  2080. }
  2081. /*
  2082. * bdx_get_ethtool_stats - return device's hardware L2 statistics
  2083. * @netdev
  2084. * @stats
  2085. * @data
  2086. */
  2087. static void bdx_get_ethtool_stats(struct net_device *netdev,
  2088. struct ethtool_stats *stats, u64 *data)
  2089. {
  2090. struct bdx_priv *priv = netdev_priv(netdev);
  2091. if (priv->stats_flag) {
  2092. /* Update stats from HW */
  2093. bdx_update_stats(priv);
  2094. /* Copy data to user buffer */
  2095. memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
  2096. }
  2097. }
  2098. /*
  2099. * bdx_ethtool_ops - ethtool interface implementation
  2100. * @netdev
  2101. */
  2102. static void bdx_ethtool_ops(struct net_device *netdev)
  2103. {
  2104. static const struct ethtool_ops bdx_ethtool_ops = {
  2105. .get_settings = bdx_get_settings,
  2106. .get_drvinfo = bdx_get_drvinfo,
  2107. .get_link = ethtool_op_get_link,
  2108. .get_coalesce = bdx_get_coalesce,
  2109. .set_coalesce = bdx_set_coalesce,
  2110. .get_ringparam = bdx_get_ringparam,
  2111. .set_ringparam = bdx_set_ringparam,
  2112. .get_rx_csum = bdx_get_rx_csum,
  2113. .get_tx_csum = bdx_get_tx_csum,
  2114. .get_sg = ethtool_op_get_sg,
  2115. .get_tso = ethtool_op_get_tso,
  2116. .get_strings = bdx_get_strings,
  2117. .get_stats_count = bdx_get_stats_count,
  2118. .get_ethtool_stats = bdx_get_ethtool_stats,
  2119. };
  2120. SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops);
  2121. }
  2122. /**
  2123. * bdx_remove - Device Removal Routine
  2124. * @pdev: PCI device information struct
  2125. *
  2126. * bdx_remove is called by the PCI subsystem to alert the driver
  2127. * that it should release a PCI device. The could be caused by a
  2128. * Hot-Plug event, or because the driver is going to be removed from
  2129. * memory.
  2130. **/
  2131. static void __devexit bdx_remove(struct pci_dev *pdev)
  2132. {
  2133. struct pci_nic *nic = pci_get_drvdata(pdev);
  2134. struct net_device *ndev;
  2135. int port;
  2136. for (port = 0; port < nic->port_num; port++) {
  2137. ndev = nic->priv[port]->ndev;
  2138. unregister_netdev(ndev);
  2139. free_netdev(ndev);
  2140. }
  2141. /*bdx_hw_reset_direct(nic->regs); */
  2142. #ifdef BDX_MSI
  2143. if (nic->irq_type == IRQ_MSI)
  2144. pci_disable_msi(pdev);
  2145. #endif
  2146. iounmap(nic->regs);
  2147. pci_release_regions(pdev);
  2148. pci_disable_device(pdev);
  2149. pci_set_drvdata(pdev, NULL);
  2150. vfree(nic);
  2151. RET();
  2152. }
  2153. static struct pci_driver bdx_pci_driver = {
  2154. .name = BDX_DRV_NAME,
  2155. .id_table = bdx_pci_tbl,
  2156. .probe = bdx_probe,
  2157. .remove = __devexit_p(bdx_remove),
  2158. };
  2159. /*
  2160. * print_driver_id - print parameters of the driver build
  2161. */
  2162. static void __init print_driver_id(void)
  2163. {
  2164. printk(KERN_INFO "%s: %s, %s\n", BDX_DRV_NAME, BDX_DRV_DESC,
  2165. BDX_DRV_VERSION);
  2166. printk(KERN_INFO "%s: Options: hw_csum %s\n", BDX_DRV_NAME,
  2167. BDX_MSI_STRING);
  2168. }
  2169. static int __init bdx_module_init(void)
  2170. {
  2171. ENTER;
  2172. init_txd_sizes();
  2173. print_driver_id();
  2174. RET(pci_register_driver(&bdx_pci_driver));
  2175. }
  2176. module_init(bdx_module_init);
  2177. static void __exit bdx_module_exit(void)
  2178. {
  2179. ENTER;
  2180. pci_unregister_driver(&bdx_pci_driver);
  2181. RET();
  2182. }
  2183. module_exit(bdx_module_exit);
  2184. MODULE_LICENSE("GPL");
  2185. MODULE_AUTHOR(DRIVER_AUTHOR);
  2186. MODULE_DESCRIPTION(BDX_DRV_DESC);
  2187. MODULE_FIRMWARE("tehuti/firmware.bin");