tx.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include "net_driver.h"
  17. #include "tx.h"
  18. #include "efx.h"
  19. #include "falcon.h"
  20. #include "workarounds.h"
  21. /*
  22. * TX descriptor ring full threshold
  23. *
  24. * The tx_queue descriptor ring fill-level must fall below this value
  25. * before we restart the netif queue
  26. */
  27. #define EFX_NETDEV_TX_THRESHOLD(_tx_queue) \
  28. (_tx_queue->efx->type->txd_ring_mask / 2u)
  29. /* We want to be able to nest calls to netif_stop_queue(), since each
  30. * channel can have an individual stop on the queue.
  31. */
  32. void efx_stop_queue(struct efx_nic *efx)
  33. {
  34. spin_lock_bh(&efx->netif_stop_lock);
  35. EFX_TRACE(efx, "stop TX queue\n");
  36. atomic_inc(&efx->netif_stop_count);
  37. netif_stop_queue(efx->net_dev);
  38. spin_unlock_bh(&efx->netif_stop_lock);
  39. }
  40. /* Wake netif's TX queue
  41. * We want to be able to nest calls to netif_stop_queue(), since each
  42. * channel can have an individual stop on the queue.
  43. */
  44. void efx_wake_queue(struct efx_nic *efx)
  45. {
  46. local_bh_disable();
  47. if (atomic_dec_and_lock(&efx->netif_stop_count,
  48. &efx->netif_stop_lock)) {
  49. EFX_TRACE(efx, "waking TX queue\n");
  50. netif_wake_queue(efx->net_dev);
  51. spin_unlock(&efx->netif_stop_lock);
  52. }
  53. local_bh_enable();
  54. }
  55. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  56. struct efx_tx_buffer *buffer)
  57. {
  58. if (buffer->unmap_len) {
  59. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  60. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  61. buffer->unmap_len);
  62. if (buffer->unmap_single)
  63. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  64. PCI_DMA_TODEVICE);
  65. else
  66. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  67. PCI_DMA_TODEVICE);
  68. buffer->unmap_len = 0;
  69. buffer->unmap_single = false;
  70. }
  71. if (buffer->skb) {
  72. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  73. buffer->skb = NULL;
  74. EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x "
  75. "complete\n", tx_queue->queue, read_ptr);
  76. }
  77. }
  78. /**
  79. * struct efx_tso_header - a DMA mapped buffer for packet headers
  80. * @next: Linked list of free ones.
  81. * The list is protected by the TX queue lock.
  82. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  83. * @dma_addr: The DMA address of the header below.
  84. *
  85. * This controls the memory used for a TSO header. Use TSOH_DATA()
  86. * to find the packet header data. Use TSOH_SIZE() to calculate the
  87. * total size required for a given packet header length. TSO headers
  88. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  89. */
  90. struct efx_tso_header {
  91. union {
  92. struct efx_tso_header *next;
  93. size_t unmap_len;
  94. };
  95. dma_addr_t dma_addr;
  96. };
  97. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  98. struct sk_buff *skb);
  99. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  100. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  101. struct efx_tso_header *tsoh);
  102. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  103. struct efx_tx_buffer *buffer)
  104. {
  105. if (buffer->tsoh) {
  106. if (likely(!buffer->tsoh->unmap_len)) {
  107. buffer->tsoh->next = tx_queue->tso_headers_free;
  108. tx_queue->tso_headers_free = buffer->tsoh;
  109. } else {
  110. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  111. }
  112. buffer->tsoh = NULL;
  113. }
  114. }
  115. /*
  116. * Add a socket buffer to a TX queue
  117. *
  118. * This maps all fragments of a socket buffer for DMA and adds them to
  119. * the TX queue. The queue's insert pointer will be incremented by
  120. * the number of fragments in the socket buffer.
  121. *
  122. * If any DMA mapping fails, any mapped fragments will be unmapped,
  123. * the queue's insert pointer will be restored to its original value.
  124. *
  125. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  126. * You must hold netif_tx_lock() to call this function.
  127. */
  128. static netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue,
  129. struct sk_buff *skb)
  130. {
  131. struct efx_nic *efx = tx_queue->efx;
  132. struct pci_dev *pci_dev = efx->pci_dev;
  133. struct efx_tx_buffer *buffer;
  134. skb_frag_t *fragment;
  135. struct page *page;
  136. int page_offset;
  137. unsigned int len, unmap_len = 0, fill_level, insert_ptr, misalign;
  138. dma_addr_t dma_addr, unmap_addr = 0;
  139. unsigned int dma_len;
  140. bool unmap_single;
  141. int q_space, i = 0;
  142. netdev_tx_t rc = NETDEV_TX_OK;
  143. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  144. if (skb_shinfo((struct sk_buff *)skb)->gso_size)
  145. return efx_enqueue_skb_tso(tx_queue, skb);
  146. /* Get size of the initial fragment */
  147. len = skb_headlen(skb);
  148. /* Pad if necessary */
  149. if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
  150. EFX_BUG_ON_PARANOID(skb->data_len);
  151. len = 32 + 1;
  152. if (skb_pad(skb, len - skb->len))
  153. return NETDEV_TX_OK;
  154. }
  155. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  156. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  157. /* Map for DMA. Use pci_map_single rather than pci_map_page
  158. * since this is more efficient on machines with sparse
  159. * memory.
  160. */
  161. unmap_single = true;
  162. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  163. /* Process all fragments */
  164. while (1) {
  165. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  166. goto pci_err;
  167. /* Store fields for marking in the per-fragment final
  168. * descriptor */
  169. unmap_len = len;
  170. unmap_addr = dma_addr;
  171. /* Add to TX queue, splitting across DMA boundaries */
  172. do {
  173. if (unlikely(q_space-- <= 0)) {
  174. /* It might be that completions have
  175. * happened since the xmit path last
  176. * checked. Update the xmit path's
  177. * copy of read_count.
  178. */
  179. ++tx_queue->stopped;
  180. /* This memory barrier protects the
  181. * change of stopped from the access
  182. * of read_count. */
  183. smp_mb();
  184. tx_queue->old_read_count =
  185. *(volatile unsigned *)
  186. &tx_queue->read_count;
  187. fill_level = (tx_queue->insert_count
  188. - tx_queue->old_read_count);
  189. q_space = (efx->type->txd_ring_mask - 1 -
  190. fill_level);
  191. if (unlikely(q_space-- <= 0))
  192. goto stop;
  193. smp_mb();
  194. --tx_queue->stopped;
  195. }
  196. insert_ptr = (tx_queue->insert_count &
  197. efx->type->txd_ring_mask);
  198. buffer = &tx_queue->buffer[insert_ptr];
  199. efx_tsoh_free(tx_queue, buffer);
  200. EFX_BUG_ON_PARANOID(buffer->tsoh);
  201. EFX_BUG_ON_PARANOID(buffer->skb);
  202. EFX_BUG_ON_PARANOID(buffer->len);
  203. EFX_BUG_ON_PARANOID(!buffer->continuation);
  204. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  205. dma_len = (((~dma_addr) & efx->type->tx_dma_mask) + 1);
  206. if (likely(dma_len > len))
  207. dma_len = len;
  208. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  209. if (misalign && dma_len + misalign > 512)
  210. dma_len = 512 - misalign;
  211. /* Fill out per descriptor fields */
  212. buffer->len = dma_len;
  213. buffer->dma_addr = dma_addr;
  214. len -= dma_len;
  215. dma_addr += dma_len;
  216. ++tx_queue->insert_count;
  217. } while (len);
  218. /* Transfer ownership of the unmapping to the final buffer */
  219. buffer->unmap_single = unmap_single;
  220. buffer->unmap_len = unmap_len;
  221. unmap_len = 0;
  222. /* Get address and size of next fragment */
  223. if (i >= skb_shinfo(skb)->nr_frags)
  224. break;
  225. fragment = &skb_shinfo(skb)->frags[i];
  226. len = fragment->size;
  227. page = fragment->page;
  228. page_offset = fragment->page_offset;
  229. i++;
  230. /* Map for DMA */
  231. unmap_single = false;
  232. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  233. PCI_DMA_TODEVICE);
  234. }
  235. /* Transfer ownership of the skb to the final buffer */
  236. buffer->skb = skb;
  237. buffer->continuation = false;
  238. /* Pass off to hardware */
  239. falcon_push_buffers(tx_queue);
  240. return NETDEV_TX_OK;
  241. pci_err:
  242. EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d "
  243. "fragments for DMA\n", tx_queue->queue, skb->len,
  244. skb_shinfo(skb)->nr_frags + 1);
  245. /* Mark the packet as transmitted, and free the SKB ourselves */
  246. dev_kfree_skb_any((struct sk_buff *)skb);
  247. goto unwind;
  248. stop:
  249. rc = NETDEV_TX_BUSY;
  250. if (tx_queue->stopped == 1)
  251. efx_stop_queue(efx);
  252. unwind:
  253. /* Work backwards until we hit the original insert pointer value */
  254. while (tx_queue->insert_count != tx_queue->write_count) {
  255. --tx_queue->insert_count;
  256. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  257. buffer = &tx_queue->buffer[insert_ptr];
  258. efx_dequeue_buffer(tx_queue, buffer);
  259. buffer->len = 0;
  260. }
  261. /* Free the fragment we were mid-way through pushing */
  262. if (unmap_len) {
  263. if (unmap_single)
  264. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  265. PCI_DMA_TODEVICE);
  266. else
  267. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  268. PCI_DMA_TODEVICE);
  269. }
  270. return rc;
  271. }
  272. /* Remove packets from the TX queue
  273. *
  274. * This removes packets from the TX queue, up to and including the
  275. * specified index.
  276. */
  277. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  278. unsigned int index)
  279. {
  280. struct efx_nic *efx = tx_queue->efx;
  281. unsigned int stop_index, read_ptr;
  282. unsigned int mask = tx_queue->efx->type->txd_ring_mask;
  283. stop_index = (index + 1) & mask;
  284. read_ptr = tx_queue->read_count & mask;
  285. while (read_ptr != stop_index) {
  286. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  287. if (unlikely(buffer->len == 0)) {
  288. EFX_ERR(tx_queue->efx, "TX queue %d spurious TX "
  289. "completion id %x\n", tx_queue->queue,
  290. read_ptr);
  291. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  292. return;
  293. }
  294. efx_dequeue_buffer(tx_queue, buffer);
  295. buffer->continuation = true;
  296. buffer->len = 0;
  297. ++tx_queue->read_count;
  298. read_ptr = tx_queue->read_count & mask;
  299. }
  300. }
  301. /* Initiate a packet transmission on the specified TX queue.
  302. * Note that returning anything other than NETDEV_TX_OK will cause the
  303. * OS to free the skb.
  304. *
  305. * This function is split out from efx_hard_start_xmit to allow the
  306. * loopback test to direct packets via specific TX queues. It is
  307. * therefore a non-static inline, so as not to penalise performance
  308. * for non-loopback transmissions.
  309. *
  310. * Context: netif_tx_lock held
  311. */
  312. inline netdev_tx_t efx_xmit(struct efx_nic *efx,
  313. struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  314. {
  315. /* Map fragments for DMA and add to TX queue */
  316. return efx_enqueue_skb(tx_queue, skb);
  317. }
  318. /* Initiate a packet transmission. We use one channel per CPU
  319. * (sharing when we have more CPUs than channels). On Falcon, the TX
  320. * completion events will be directed back to the CPU that transmitted
  321. * the packet, which should be cache-efficient.
  322. *
  323. * Context: non-blocking.
  324. * Note that returning anything other than NETDEV_TX_OK will cause the
  325. * OS to free the skb.
  326. */
  327. netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
  328. struct net_device *net_dev)
  329. {
  330. struct efx_nic *efx = netdev_priv(net_dev);
  331. struct efx_tx_queue *tx_queue;
  332. if (unlikely(efx->port_inhibited))
  333. return NETDEV_TX_BUSY;
  334. if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
  335. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_OFFLOAD_CSUM];
  336. else
  337. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_NO_CSUM];
  338. return efx_xmit(efx, tx_queue, skb);
  339. }
  340. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  341. {
  342. unsigned fill_level;
  343. struct efx_nic *efx = tx_queue->efx;
  344. EFX_BUG_ON_PARANOID(index > efx->type->txd_ring_mask);
  345. efx_dequeue_buffers(tx_queue, index);
  346. /* See if we need to restart the netif queue. This barrier
  347. * separates the update of read_count from the test of
  348. * stopped. */
  349. smp_mb();
  350. if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
  351. fill_level = tx_queue->insert_count - tx_queue->read_count;
  352. if (fill_level < EFX_NETDEV_TX_THRESHOLD(tx_queue)) {
  353. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  354. /* Do this under netif_tx_lock(), to avoid racing
  355. * with efx_xmit(). */
  356. netif_tx_lock(efx->net_dev);
  357. if (tx_queue->stopped) {
  358. tx_queue->stopped = 0;
  359. efx_wake_queue(efx);
  360. }
  361. netif_tx_unlock(efx->net_dev);
  362. }
  363. }
  364. }
  365. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  366. {
  367. struct efx_nic *efx = tx_queue->efx;
  368. unsigned int txq_size;
  369. int i, rc;
  370. EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue);
  371. /* Allocate software ring */
  372. txq_size = (efx->type->txd_ring_mask + 1) * sizeof(*tx_queue->buffer);
  373. tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL);
  374. if (!tx_queue->buffer)
  375. return -ENOMEM;
  376. for (i = 0; i <= efx->type->txd_ring_mask; ++i)
  377. tx_queue->buffer[i].continuation = true;
  378. /* Allocate hardware ring */
  379. rc = falcon_probe_tx(tx_queue);
  380. if (rc)
  381. goto fail;
  382. return 0;
  383. fail:
  384. kfree(tx_queue->buffer);
  385. tx_queue->buffer = NULL;
  386. return rc;
  387. }
  388. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  389. {
  390. EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue);
  391. tx_queue->insert_count = 0;
  392. tx_queue->write_count = 0;
  393. tx_queue->read_count = 0;
  394. tx_queue->old_read_count = 0;
  395. BUG_ON(tx_queue->stopped);
  396. /* Set up TX descriptor ring */
  397. falcon_init_tx(tx_queue);
  398. }
  399. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  400. {
  401. struct efx_tx_buffer *buffer;
  402. if (!tx_queue->buffer)
  403. return;
  404. /* Free any buffers left in the ring */
  405. while (tx_queue->read_count != tx_queue->write_count) {
  406. buffer = &tx_queue->buffer[tx_queue->read_count &
  407. tx_queue->efx->type->txd_ring_mask];
  408. efx_dequeue_buffer(tx_queue, buffer);
  409. buffer->continuation = true;
  410. buffer->len = 0;
  411. ++tx_queue->read_count;
  412. }
  413. }
  414. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  415. {
  416. EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue);
  417. /* Flush TX queue, remove descriptor ring */
  418. falcon_fini_tx(tx_queue);
  419. efx_release_tx_buffers(tx_queue);
  420. /* Free up TSO header cache */
  421. efx_fini_tso(tx_queue);
  422. /* Release queue's stop on port, if any */
  423. if (tx_queue->stopped) {
  424. tx_queue->stopped = 0;
  425. efx_wake_queue(tx_queue->efx);
  426. }
  427. }
  428. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  429. {
  430. EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue);
  431. falcon_remove_tx(tx_queue);
  432. kfree(tx_queue->buffer);
  433. tx_queue->buffer = NULL;
  434. }
  435. /* Efx TCP segmentation acceleration.
  436. *
  437. * Why? Because by doing it here in the driver we can go significantly
  438. * faster than the GSO.
  439. *
  440. * Requires TX checksum offload support.
  441. */
  442. /* Number of bytes inserted at the start of a TSO header buffer,
  443. * similar to NET_IP_ALIGN.
  444. */
  445. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  446. #define TSOH_OFFSET 0
  447. #else
  448. #define TSOH_OFFSET NET_IP_ALIGN
  449. #endif
  450. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  451. /* Total size of struct efx_tso_header, buffer and padding */
  452. #define TSOH_SIZE(hdr_len) \
  453. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  454. /* Size of blocks on free list. Larger blocks must be allocated from
  455. * the heap.
  456. */
  457. #define TSOH_STD_SIZE 128
  458. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  459. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  460. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  461. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  462. /**
  463. * struct tso_state - TSO state for an SKB
  464. * @out_len: Remaining length in current segment
  465. * @seqnum: Current sequence number
  466. * @ipv4_id: Current IPv4 ID, host endian
  467. * @packet_space: Remaining space in current packet
  468. * @dma_addr: DMA address of current position
  469. * @in_len: Remaining length in current SKB fragment
  470. * @unmap_len: Length of SKB fragment
  471. * @unmap_addr: DMA address of SKB fragment
  472. * @unmap_single: DMA single vs page mapping flag
  473. * @header_len: Number of bytes of header
  474. * @full_packet_size: Number of bytes to put in each outgoing segment
  475. *
  476. * The state used during segmentation. It is put into this data structure
  477. * just to make it easy to pass into inline functions.
  478. */
  479. struct tso_state {
  480. /* Output position */
  481. unsigned out_len;
  482. unsigned seqnum;
  483. unsigned ipv4_id;
  484. unsigned packet_space;
  485. /* Input position */
  486. dma_addr_t dma_addr;
  487. unsigned in_len;
  488. unsigned unmap_len;
  489. dma_addr_t unmap_addr;
  490. bool unmap_single;
  491. unsigned header_len;
  492. int full_packet_size;
  493. };
  494. /*
  495. * Verify that our various assumptions about sk_buffs and the conditions
  496. * under which TSO will be attempted hold true.
  497. */
  498. static void efx_tso_check_safe(struct sk_buff *skb)
  499. {
  500. __be16 protocol = skb->protocol;
  501. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  502. protocol);
  503. if (protocol == htons(ETH_P_8021Q)) {
  504. /* Find the encapsulated protocol; reset network header
  505. * and transport header based on that. */
  506. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  507. protocol = veh->h_vlan_encapsulated_proto;
  508. skb_set_network_header(skb, sizeof(*veh));
  509. if (protocol == htons(ETH_P_IP))
  510. skb_set_transport_header(skb, sizeof(*veh) +
  511. 4 * ip_hdr(skb)->ihl);
  512. }
  513. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IP));
  514. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  515. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  516. + (tcp_hdr(skb)->doff << 2u)) >
  517. skb_headlen(skb));
  518. }
  519. /*
  520. * Allocate a page worth of efx_tso_header structures, and string them
  521. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  522. */
  523. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  524. {
  525. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  526. struct efx_tso_header *tsoh;
  527. dma_addr_t dma_addr;
  528. u8 *base_kva, *kva;
  529. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  530. if (base_kva == NULL) {
  531. EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO"
  532. " headers\n");
  533. return -ENOMEM;
  534. }
  535. /* pci_alloc_consistent() allocates pages. */
  536. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  537. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  538. tsoh = (struct efx_tso_header *)kva;
  539. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  540. tsoh->next = tx_queue->tso_headers_free;
  541. tx_queue->tso_headers_free = tsoh;
  542. }
  543. return 0;
  544. }
  545. /* Free up a TSO header, and all others in the same page. */
  546. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  547. struct efx_tso_header *tsoh,
  548. struct pci_dev *pci_dev)
  549. {
  550. struct efx_tso_header **p;
  551. unsigned long base_kva;
  552. dma_addr_t base_dma;
  553. base_kva = (unsigned long)tsoh & PAGE_MASK;
  554. base_dma = tsoh->dma_addr & PAGE_MASK;
  555. p = &tx_queue->tso_headers_free;
  556. while (*p != NULL) {
  557. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  558. *p = (*p)->next;
  559. else
  560. p = &(*p)->next;
  561. }
  562. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  563. }
  564. static struct efx_tso_header *
  565. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  566. {
  567. struct efx_tso_header *tsoh;
  568. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  569. if (unlikely(!tsoh))
  570. return NULL;
  571. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  572. TSOH_BUFFER(tsoh), header_len,
  573. PCI_DMA_TODEVICE);
  574. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  575. tsoh->dma_addr))) {
  576. kfree(tsoh);
  577. return NULL;
  578. }
  579. tsoh->unmap_len = header_len;
  580. return tsoh;
  581. }
  582. static void
  583. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  584. {
  585. pci_unmap_single(tx_queue->efx->pci_dev,
  586. tsoh->dma_addr, tsoh->unmap_len,
  587. PCI_DMA_TODEVICE);
  588. kfree(tsoh);
  589. }
  590. /**
  591. * efx_tx_queue_insert - push descriptors onto the TX queue
  592. * @tx_queue: Efx TX queue
  593. * @dma_addr: DMA address of fragment
  594. * @len: Length of fragment
  595. * @final_buffer: The final buffer inserted into the queue
  596. *
  597. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  598. * @tx_queue full.
  599. */
  600. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  601. dma_addr_t dma_addr, unsigned len,
  602. struct efx_tx_buffer **final_buffer)
  603. {
  604. struct efx_tx_buffer *buffer;
  605. struct efx_nic *efx = tx_queue->efx;
  606. unsigned dma_len, fill_level, insert_ptr, misalign;
  607. int q_space;
  608. EFX_BUG_ON_PARANOID(len <= 0);
  609. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  610. /* -1 as there is no way to represent all descriptors used */
  611. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  612. while (1) {
  613. if (unlikely(q_space-- <= 0)) {
  614. /* It might be that completions have happened
  615. * since the xmit path last checked. Update
  616. * the xmit path's copy of read_count.
  617. */
  618. ++tx_queue->stopped;
  619. /* This memory barrier protects the change of
  620. * stopped from the access of read_count. */
  621. smp_mb();
  622. tx_queue->old_read_count =
  623. *(volatile unsigned *)&tx_queue->read_count;
  624. fill_level = (tx_queue->insert_count
  625. - tx_queue->old_read_count);
  626. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  627. if (unlikely(q_space-- <= 0)) {
  628. *final_buffer = NULL;
  629. return 1;
  630. }
  631. smp_mb();
  632. --tx_queue->stopped;
  633. }
  634. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  635. buffer = &tx_queue->buffer[insert_ptr];
  636. ++tx_queue->insert_count;
  637. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  638. tx_queue->read_count >
  639. efx->type->txd_ring_mask);
  640. efx_tsoh_free(tx_queue, buffer);
  641. EFX_BUG_ON_PARANOID(buffer->len);
  642. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  643. EFX_BUG_ON_PARANOID(buffer->skb);
  644. EFX_BUG_ON_PARANOID(!buffer->continuation);
  645. EFX_BUG_ON_PARANOID(buffer->tsoh);
  646. buffer->dma_addr = dma_addr;
  647. /* Ensure we do not cross a boundary unsupported by H/W */
  648. dma_len = (~dma_addr & efx->type->tx_dma_mask) + 1;
  649. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  650. if (misalign && dma_len + misalign > 512)
  651. dma_len = 512 - misalign;
  652. /* If there is enough space to send then do so */
  653. if (dma_len >= len)
  654. break;
  655. buffer->len = dma_len; /* Don't set the other members */
  656. dma_addr += dma_len;
  657. len -= dma_len;
  658. }
  659. EFX_BUG_ON_PARANOID(!len);
  660. buffer->len = len;
  661. *final_buffer = buffer;
  662. return 0;
  663. }
  664. /*
  665. * Put a TSO header into the TX queue.
  666. *
  667. * This is special-cased because we know that it is small enough to fit in
  668. * a single fragment, and we know it doesn't cross a page boundary. It
  669. * also allows us to not worry about end-of-packet etc.
  670. */
  671. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  672. struct efx_tso_header *tsoh, unsigned len)
  673. {
  674. struct efx_tx_buffer *buffer;
  675. buffer = &tx_queue->buffer[tx_queue->insert_count &
  676. tx_queue->efx->type->txd_ring_mask];
  677. efx_tsoh_free(tx_queue, buffer);
  678. EFX_BUG_ON_PARANOID(buffer->len);
  679. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  680. EFX_BUG_ON_PARANOID(buffer->skb);
  681. EFX_BUG_ON_PARANOID(!buffer->continuation);
  682. EFX_BUG_ON_PARANOID(buffer->tsoh);
  683. buffer->len = len;
  684. buffer->dma_addr = tsoh->dma_addr;
  685. buffer->tsoh = tsoh;
  686. ++tx_queue->insert_count;
  687. }
  688. /* Remove descriptors put into a tx_queue. */
  689. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  690. {
  691. struct efx_tx_buffer *buffer;
  692. dma_addr_t unmap_addr;
  693. /* Work backwards until we hit the original insert pointer value */
  694. while (tx_queue->insert_count != tx_queue->write_count) {
  695. --tx_queue->insert_count;
  696. buffer = &tx_queue->buffer[tx_queue->insert_count &
  697. tx_queue->efx->type->txd_ring_mask];
  698. efx_tsoh_free(tx_queue, buffer);
  699. EFX_BUG_ON_PARANOID(buffer->skb);
  700. buffer->len = 0;
  701. buffer->continuation = true;
  702. if (buffer->unmap_len) {
  703. unmap_addr = (buffer->dma_addr + buffer->len -
  704. buffer->unmap_len);
  705. if (buffer->unmap_single)
  706. pci_unmap_single(tx_queue->efx->pci_dev,
  707. unmap_addr, buffer->unmap_len,
  708. PCI_DMA_TODEVICE);
  709. else
  710. pci_unmap_page(tx_queue->efx->pci_dev,
  711. unmap_addr, buffer->unmap_len,
  712. PCI_DMA_TODEVICE);
  713. buffer->unmap_len = 0;
  714. }
  715. }
  716. }
  717. /* Parse the SKB header and initialise state. */
  718. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  719. {
  720. /* All ethernet/IP/TCP headers combined size is TCP header size
  721. * plus offset of TCP header relative to start of packet.
  722. */
  723. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  724. + PTR_DIFF(tcp_hdr(skb), skb->data));
  725. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  726. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  727. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  728. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  729. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  730. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  731. st->packet_space = st->full_packet_size;
  732. st->out_len = skb->len - st->header_len;
  733. st->unmap_len = 0;
  734. st->unmap_single = false;
  735. }
  736. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  737. skb_frag_t *frag)
  738. {
  739. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  740. frag->page_offset, frag->size,
  741. PCI_DMA_TODEVICE);
  742. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  743. st->unmap_single = false;
  744. st->unmap_len = frag->size;
  745. st->in_len = frag->size;
  746. st->dma_addr = st->unmap_addr;
  747. return 0;
  748. }
  749. return -ENOMEM;
  750. }
  751. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  752. const struct sk_buff *skb)
  753. {
  754. int hl = st->header_len;
  755. int len = skb_headlen(skb) - hl;
  756. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  757. len, PCI_DMA_TODEVICE);
  758. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  759. st->unmap_single = true;
  760. st->unmap_len = len;
  761. st->in_len = len;
  762. st->dma_addr = st->unmap_addr;
  763. return 0;
  764. }
  765. return -ENOMEM;
  766. }
  767. /**
  768. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  769. * @tx_queue: Efx TX queue
  770. * @skb: Socket buffer
  771. * @st: TSO state
  772. *
  773. * Form descriptors for the current fragment, until we reach the end
  774. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  775. * space in @tx_queue.
  776. */
  777. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  778. const struct sk_buff *skb,
  779. struct tso_state *st)
  780. {
  781. struct efx_tx_buffer *buffer;
  782. int n, end_of_packet, rc;
  783. if (st->in_len == 0)
  784. return 0;
  785. if (st->packet_space == 0)
  786. return 0;
  787. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  788. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  789. n = min(st->in_len, st->packet_space);
  790. st->packet_space -= n;
  791. st->out_len -= n;
  792. st->in_len -= n;
  793. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  794. if (likely(rc == 0)) {
  795. if (st->out_len == 0)
  796. /* Transfer ownership of the skb */
  797. buffer->skb = skb;
  798. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  799. buffer->continuation = !end_of_packet;
  800. if (st->in_len == 0) {
  801. /* Transfer ownership of the pci mapping */
  802. buffer->unmap_len = st->unmap_len;
  803. buffer->unmap_single = st->unmap_single;
  804. st->unmap_len = 0;
  805. }
  806. }
  807. st->dma_addr += n;
  808. return rc;
  809. }
  810. /**
  811. * tso_start_new_packet - generate a new header and prepare for the new packet
  812. * @tx_queue: Efx TX queue
  813. * @skb: Socket buffer
  814. * @st: TSO state
  815. *
  816. * Generate a new header and prepare for the new packet. Return 0 on
  817. * success, or -1 if failed to alloc header.
  818. */
  819. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  820. const struct sk_buff *skb,
  821. struct tso_state *st)
  822. {
  823. struct efx_tso_header *tsoh;
  824. struct iphdr *tsoh_iph;
  825. struct tcphdr *tsoh_th;
  826. unsigned ip_length;
  827. u8 *header;
  828. /* Allocate a DMA-mapped header buffer. */
  829. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  830. if (tx_queue->tso_headers_free == NULL) {
  831. if (efx_tsoh_block_alloc(tx_queue))
  832. return -1;
  833. }
  834. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  835. tsoh = tx_queue->tso_headers_free;
  836. tx_queue->tso_headers_free = tsoh->next;
  837. tsoh->unmap_len = 0;
  838. } else {
  839. tx_queue->tso_long_headers++;
  840. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  841. if (unlikely(!tsoh))
  842. return -1;
  843. }
  844. header = TSOH_BUFFER(tsoh);
  845. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  846. tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  847. /* Copy and update the headers. */
  848. memcpy(header, skb->data, st->header_len);
  849. tsoh_th->seq = htonl(st->seqnum);
  850. st->seqnum += skb_shinfo(skb)->gso_size;
  851. if (st->out_len > skb_shinfo(skb)->gso_size) {
  852. /* This packet will not finish the TSO burst. */
  853. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  854. tsoh_th->fin = 0;
  855. tsoh_th->psh = 0;
  856. } else {
  857. /* This packet will be the last in the TSO burst. */
  858. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  859. tsoh_th->fin = tcp_hdr(skb)->fin;
  860. tsoh_th->psh = tcp_hdr(skb)->psh;
  861. }
  862. tsoh_iph->tot_len = htons(ip_length);
  863. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  864. tsoh_iph->id = htons(st->ipv4_id);
  865. st->ipv4_id++;
  866. st->packet_space = skb_shinfo(skb)->gso_size;
  867. ++tx_queue->tso_packets;
  868. /* Form a descriptor for this header. */
  869. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  870. return 0;
  871. }
  872. /**
  873. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  874. * @tx_queue: Efx TX queue
  875. * @skb: Socket buffer
  876. *
  877. * Context: You must hold netif_tx_lock() to call this function.
  878. *
  879. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  880. * @skb was not enqueued. In all cases @skb is consumed. Return
  881. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  882. */
  883. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  884. struct sk_buff *skb)
  885. {
  886. struct efx_nic *efx = tx_queue->efx;
  887. int frag_i, rc, rc2 = NETDEV_TX_OK;
  888. struct tso_state state;
  889. /* Verify TSO is safe - these checks should never fail. */
  890. efx_tso_check_safe(skb);
  891. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  892. tso_start(&state, skb);
  893. /* Assume that skb header area contains exactly the headers, and
  894. * all payload is in the frag list.
  895. */
  896. if (skb_headlen(skb) == state.header_len) {
  897. /* Grab the first payload fragment. */
  898. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  899. frag_i = 0;
  900. rc = tso_get_fragment(&state, efx,
  901. skb_shinfo(skb)->frags + frag_i);
  902. if (rc)
  903. goto mem_err;
  904. } else {
  905. rc = tso_get_head_fragment(&state, efx, skb);
  906. if (rc)
  907. goto mem_err;
  908. frag_i = -1;
  909. }
  910. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  911. goto mem_err;
  912. while (1) {
  913. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  914. if (unlikely(rc))
  915. goto stop;
  916. /* Move onto the next fragment? */
  917. if (state.in_len == 0) {
  918. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  919. /* End of payload reached. */
  920. break;
  921. rc = tso_get_fragment(&state, efx,
  922. skb_shinfo(skb)->frags + frag_i);
  923. if (rc)
  924. goto mem_err;
  925. }
  926. /* Start at new packet? */
  927. if (state.packet_space == 0 &&
  928. tso_start_new_packet(tx_queue, skb, &state) < 0)
  929. goto mem_err;
  930. }
  931. /* Pass off to hardware */
  932. falcon_push_buffers(tx_queue);
  933. tx_queue->tso_bursts++;
  934. return NETDEV_TX_OK;
  935. mem_err:
  936. EFX_ERR(efx, "Out of memory for TSO headers, or PCI mapping error\n");
  937. dev_kfree_skb_any((struct sk_buff *)skb);
  938. goto unwind;
  939. stop:
  940. rc2 = NETDEV_TX_BUSY;
  941. /* Stop the queue if it wasn't stopped before. */
  942. if (tx_queue->stopped == 1)
  943. efx_stop_queue(efx);
  944. unwind:
  945. /* Free the DMA mapping we were in the process of writing out */
  946. if (state.unmap_len) {
  947. if (state.unmap_single)
  948. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  949. state.unmap_len, PCI_DMA_TODEVICE);
  950. else
  951. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  952. state.unmap_len, PCI_DMA_TODEVICE);
  953. }
  954. efx_enqueue_unwind(tx_queue);
  955. return rc2;
  956. }
  957. /*
  958. * Free up all TSO datastructures associated with tx_queue. This
  959. * routine should be called only once the tx_queue is both empty and
  960. * will no longer be used.
  961. */
  962. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  963. {
  964. unsigned i;
  965. if (tx_queue->buffer) {
  966. for (i = 0; i <= tx_queue->efx->type->txd_ring_mask; ++i)
  967. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  968. }
  969. while (tx_queue->tso_headers_free != NULL)
  970. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  971. tx_queue->efx->pci_dev);
  972. }