mdio_10g.c 9.4 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2006-2008 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. /*
  10. * Useful functions for working with MDIO clause 45 PHYs
  11. */
  12. #include <linux/types.h>
  13. #include <linux/ethtool.h>
  14. #include <linux/delay.h>
  15. #include "net_driver.h"
  16. #include "mdio_10g.h"
  17. #include "boards.h"
  18. #include "workarounds.h"
  19. unsigned efx_mdio_id_oui(u32 id)
  20. {
  21. unsigned oui = 0;
  22. int i;
  23. /* The bits of the OUI are designated a..x, with a=0 and b variable.
  24. * In the id register c is the MSB but the OUI is conventionally
  25. * written as bytes h..a, p..i, x..q. Reorder the bits accordingly. */
  26. for (i = 0; i < 22; ++i)
  27. if (id & (1 << (i + 10)))
  28. oui |= 1 << (i ^ 7);
  29. return oui;
  30. }
  31. int efx_mdio_reset_mmd(struct efx_nic *port, int mmd,
  32. int spins, int spintime)
  33. {
  34. u32 ctrl;
  35. /* Catch callers passing values in the wrong units (or just silly) */
  36. EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
  37. efx_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET);
  38. /* Wait for the reset bit to clear. */
  39. do {
  40. msleep(spintime);
  41. ctrl = efx_mdio_read(port, mmd, MDIO_CTRL1);
  42. spins--;
  43. } while (spins && (ctrl & MDIO_CTRL1_RESET));
  44. return spins ? spins : -ETIMEDOUT;
  45. }
  46. static int efx_mdio_check_mmd(struct efx_nic *efx, int mmd, int fault_fatal)
  47. {
  48. int status;
  49. if (LOOPBACK_INTERNAL(efx))
  50. return 0;
  51. if (mmd != MDIO_MMD_AN) {
  52. /* Read MMD STATUS2 to check it is responding. */
  53. status = efx_mdio_read(efx, mmd, MDIO_STAT2);
  54. if ((status & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) {
  55. EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
  56. return -EIO;
  57. }
  58. }
  59. /* Read MMD STATUS 1 to check for fault. */
  60. status = efx_mdio_read(efx, mmd, MDIO_STAT1);
  61. if (status & MDIO_STAT1_FAULT) {
  62. if (fault_fatal) {
  63. EFX_ERR(efx, "PHY MMD %d reporting fatal"
  64. " fault: status %x\n", mmd, status);
  65. return -EIO;
  66. } else {
  67. EFX_LOG(efx, "PHY MMD %d reporting status"
  68. " %x (expected)\n", mmd, status);
  69. }
  70. }
  71. return 0;
  72. }
  73. /* This ought to be ridiculous overkill. We expect it to fail rarely */
  74. #define MDIO45_RESET_TIME 1000 /* ms */
  75. #define MDIO45_RESET_ITERS 100
  76. int efx_mdio_wait_reset_mmds(struct efx_nic *efx, unsigned int mmd_mask)
  77. {
  78. const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
  79. int tries = MDIO45_RESET_ITERS;
  80. int rc = 0;
  81. int in_reset;
  82. while (tries) {
  83. int mask = mmd_mask;
  84. int mmd = 0;
  85. int stat;
  86. in_reset = 0;
  87. while (mask) {
  88. if (mask & 1) {
  89. stat = efx_mdio_read(efx, mmd, MDIO_CTRL1);
  90. if (stat < 0) {
  91. EFX_ERR(efx, "failed to read status of"
  92. " MMD %d\n", mmd);
  93. return -EIO;
  94. }
  95. if (stat & MDIO_CTRL1_RESET)
  96. in_reset |= (1 << mmd);
  97. }
  98. mask = mask >> 1;
  99. mmd++;
  100. }
  101. if (!in_reset)
  102. break;
  103. tries--;
  104. msleep(spintime);
  105. }
  106. if (in_reset != 0) {
  107. EFX_ERR(efx, "not all MMDs came out of reset in time."
  108. " MMDs still in reset: %x\n", in_reset);
  109. rc = -ETIMEDOUT;
  110. }
  111. return rc;
  112. }
  113. int efx_mdio_check_mmds(struct efx_nic *efx,
  114. unsigned int mmd_mask, unsigned int fatal_mask)
  115. {
  116. int mmd = 0, probe_mmd, devs1, devs2;
  117. u32 devices;
  118. /* Historically we have probed the PHYXS to find out what devices are
  119. * present,but that doesn't work so well if the PHYXS isn't expected
  120. * to exist, if so just find the first item in the list supplied. */
  121. probe_mmd = (mmd_mask & MDIO_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
  122. __ffs(mmd_mask);
  123. /* Check all the expected MMDs are present */
  124. devs1 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS1);
  125. devs2 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS2);
  126. if (devs1 < 0 || devs2 < 0) {
  127. EFX_ERR(efx, "failed to read devices present\n");
  128. return -EIO;
  129. }
  130. devices = devs1 | (devs2 << 16);
  131. if ((devices & mmd_mask) != mmd_mask) {
  132. EFX_ERR(efx, "required MMDs not present: got %x, "
  133. "wanted %x\n", devices, mmd_mask);
  134. return -ENODEV;
  135. }
  136. EFX_TRACE(efx, "Devices present: %x\n", devices);
  137. /* Check all required MMDs are responding and happy. */
  138. while (mmd_mask) {
  139. if (mmd_mask & 1) {
  140. int fault_fatal = fatal_mask & 1;
  141. if (efx_mdio_check_mmd(efx, mmd, fault_fatal))
  142. return -EIO;
  143. }
  144. mmd_mask = mmd_mask >> 1;
  145. fatal_mask = fatal_mask >> 1;
  146. mmd++;
  147. }
  148. return 0;
  149. }
  150. bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
  151. {
  152. /* If the port is in loopback, then we should only consider a subset
  153. * of mmd's */
  154. if (LOOPBACK_INTERNAL(efx))
  155. return true;
  156. else if (efx->loopback_mode == LOOPBACK_NETWORK)
  157. return false;
  158. else if (efx_phy_mode_disabled(efx->phy_mode))
  159. return false;
  160. else if (efx->loopback_mode == LOOPBACK_PHYXS)
  161. mmd_mask &= ~(MDIO_DEVS_PHYXS |
  162. MDIO_DEVS_PCS |
  163. MDIO_DEVS_PMAPMD |
  164. MDIO_DEVS_AN);
  165. else if (efx->loopback_mode == LOOPBACK_PCS)
  166. mmd_mask &= ~(MDIO_DEVS_PCS |
  167. MDIO_DEVS_PMAPMD |
  168. MDIO_DEVS_AN);
  169. else if (efx->loopback_mode == LOOPBACK_PMAPMD)
  170. mmd_mask &= ~(MDIO_DEVS_PMAPMD |
  171. MDIO_DEVS_AN);
  172. return mdio45_links_ok(&efx->mdio, mmd_mask);
  173. }
  174. void efx_mdio_transmit_disable(struct efx_nic *efx)
  175. {
  176. efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
  177. MDIO_PMA_TXDIS, MDIO_PMD_TXDIS_GLOBAL,
  178. efx->phy_mode & PHY_MODE_TX_DISABLED);
  179. }
  180. void efx_mdio_phy_reconfigure(struct efx_nic *efx)
  181. {
  182. efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
  183. MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK,
  184. efx->loopback_mode == LOOPBACK_PMAPMD);
  185. efx_mdio_set_flag(efx, MDIO_MMD_PCS,
  186. MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK,
  187. efx->loopback_mode == LOOPBACK_PCS);
  188. efx_mdio_set_flag(efx, MDIO_MMD_PHYXS,
  189. MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK,
  190. efx->loopback_mode == LOOPBACK_NETWORK);
  191. }
  192. static void efx_mdio_set_mmd_lpower(struct efx_nic *efx,
  193. int lpower, int mmd)
  194. {
  195. int stat = efx_mdio_read(efx, mmd, MDIO_STAT1);
  196. EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n",
  197. mmd, lpower);
  198. if (stat & MDIO_STAT1_LPOWERABLE) {
  199. efx_mdio_set_flag(efx, mmd, MDIO_CTRL1,
  200. MDIO_CTRL1_LPOWER, lpower);
  201. }
  202. }
  203. void efx_mdio_set_mmds_lpower(struct efx_nic *efx,
  204. int low_power, unsigned int mmd_mask)
  205. {
  206. int mmd = 0;
  207. mmd_mask &= ~MDIO_DEVS_AN;
  208. while (mmd_mask) {
  209. if (mmd_mask & 1)
  210. efx_mdio_set_mmd_lpower(efx, low_power, mmd);
  211. mmd_mask = (mmd_mask >> 1);
  212. mmd++;
  213. }
  214. }
  215. /**
  216. * efx_mdio_set_settings - Set (some of) the PHY settings over MDIO.
  217. * @efx: Efx NIC
  218. * @ecmd: New settings
  219. */
  220. int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
  221. {
  222. struct ethtool_cmd prev;
  223. u32 required;
  224. int reg;
  225. efx->phy_op->get_settings(efx, &prev);
  226. if (ecmd->advertising == prev.advertising &&
  227. ecmd->speed == prev.speed &&
  228. ecmd->duplex == prev.duplex &&
  229. ecmd->port == prev.port &&
  230. ecmd->autoneg == prev.autoneg)
  231. return 0;
  232. /* We can only change these settings for -T PHYs */
  233. if (prev.port != PORT_TP || ecmd->port != PORT_TP)
  234. return -EINVAL;
  235. /* Check that PHY supports these settings */
  236. if (ecmd->autoneg) {
  237. required = SUPPORTED_Autoneg;
  238. } else if (ecmd->duplex) {
  239. switch (ecmd->speed) {
  240. case SPEED_10: required = SUPPORTED_10baseT_Full; break;
  241. case SPEED_100: required = SUPPORTED_100baseT_Full; break;
  242. default: return -EINVAL;
  243. }
  244. } else {
  245. switch (ecmd->speed) {
  246. case SPEED_10: required = SUPPORTED_10baseT_Half; break;
  247. case SPEED_100: required = SUPPORTED_100baseT_Half; break;
  248. default: return -EINVAL;
  249. }
  250. }
  251. required |= ecmd->advertising;
  252. if (required & ~prev.supported)
  253. return -EINVAL;
  254. if (ecmd->autoneg) {
  255. bool xnp = (ecmd->advertising & ADVERTISED_10000baseT_Full
  256. || EFX_WORKAROUND_13204(efx));
  257. /* Set up the base page */
  258. reg = ADVERTISE_CSMA;
  259. if (ecmd->advertising & ADVERTISED_10baseT_Half)
  260. reg |= ADVERTISE_10HALF;
  261. if (ecmd->advertising & ADVERTISED_10baseT_Full)
  262. reg |= ADVERTISE_10FULL;
  263. if (ecmd->advertising & ADVERTISED_100baseT_Half)
  264. reg |= ADVERTISE_100HALF;
  265. if (ecmd->advertising & ADVERTISED_100baseT_Full)
  266. reg |= ADVERTISE_100FULL;
  267. if (xnp)
  268. reg |= ADVERTISE_RESV;
  269. else if (ecmd->advertising & (ADVERTISED_1000baseT_Half |
  270. ADVERTISED_1000baseT_Full))
  271. reg |= ADVERTISE_NPAGE;
  272. reg |= mii_advertise_flowctrl(efx->wanted_fc);
  273. efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
  274. /* Set up the (extended) next page if necessary */
  275. if (efx->phy_op->set_npage_adv)
  276. efx->phy_op->set_npage_adv(efx, ecmd->advertising);
  277. /* Enable and restart AN */
  278. reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
  279. reg |= MDIO_AN_CTRL1_ENABLE;
  280. if (!(EFX_WORKAROUND_15195(efx) &&
  281. LOOPBACK_MASK(efx) & efx->phy_op->loopbacks))
  282. reg |= MDIO_AN_CTRL1_RESTART;
  283. if (xnp)
  284. reg |= MDIO_AN_CTRL1_XNP;
  285. else
  286. reg &= ~MDIO_AN_CTRL1_XNP;
  287. efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
  288. } else {
  289. /* Disable AN */
  290. efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_CTRL1,
  291. MDIO_AN_CTRL1_ENABLE, false);
  292. /* Set the basic control bits */
  293. reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1);
  294. reg &= ~(MDIO_CTRL1_SPEEDSEL | MDIO_CTRL1_FULLDPLX);
  295. if (ecmd->speed == SPEED_100)
  296. reg |= MDIO_PMA_CTRL1_SPEED100;
  297. if (ecmd->duplex)
  298. reg |= MDIO_CTRL1_FULLDPLX;
  299. efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, reg);
  300. }
  301. return 0;
  302. }
  303. enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx)
  304. {
  305. int lpa;
  306. if (!(efx->phy_op->mmds & MDIO_DEVS_AN))
  307. return efx->wanted_fc;
  308. lpa = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA);
  309. return efx_fc_resolve(efx->wanted_fc, lpa);
  310. }