falcon_xmac.c 12 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/delay.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "falcon.h"
  14. #include "falcon_hwdefs.h"
  15. #include "falcon_io.h"
  16. #include "mac.h"
  17. #include "mdio_10g.h"
  18. #include "phy.h"
  19. #include "boards.h"
  20. #include "workarounds.h"
  21. /**************************************************************************
  22. *
  23. * MAC operations
  24. *
  25. *************************************************************************/
  26. /* Configure the XAUI driver that is an output from Falcon */
  27. static void falcon_setup_xaui(struct efx_nic *efx)
  28. {
  29. efx_oword_t sdctl, txdrv;
  30. /* Move the XAUI into low power, unless there is no PHY, in
  31. * which case the XAUI will have to drive a cable. */
  32. if (efx->phy_type == PHY_TYPE_NONE)
  33. return;
  34. falcon_read(efx, &sdctl, XX_SD_CTL_REG);
  35. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
  36. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
  37. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
  38. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
  39. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
  40. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
  41. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
  42. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
  43. falcon_write(efx, &sdctl, XX_SD_CTL_REG);
  44. EFX_POPULATE_OWORD_8(txdrv,
  45. XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
  46. XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
  47. XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
  48. XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
  49. XX_DTXD, XX_TXDRV_DTX_DEFAULT,
  50. XX_DTXC, XX_TXDRV_DTX_DEFAULT,
  51. XX_DTXB, XX_TXDRV_DTX_DEFAULT,
  52. XX_DTXA, XX_TXDRV_DTX_DEFAULT);
  53. falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);
  54. }
  55. int falcon_reset_xaui(struct efx_nic *efx)
  56. {
  57. efx_oword_t reg;
  58. int count;
  59. /* Start reset sequence */
  60. EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
  61. falcon_write(efx, &reg, XX_PWR_RST_REG);
  62. /* Wait up to 10 ms for completion, then reinitialise */
  63. for (count = 0; count < 1000; count++) {
  64. falcon_read(efx, &reg, XX_PWR_RST_REG);
  65. if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0 &&
  66. EFX_OWORD_FIELD(reg, XX_SD_RST_ACT) == 0) {
  67. falcon_setup_xaui(efx);
  68. return 0;
  69. }
  70. udelay(10);
  71. }
  72. EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
  73. return -ETIMEDOUT;
  74. }
  75. static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
  76. {
  77. efx_oword_t reg;
  78. if ((falcon_rev(efx) != FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
  79. return;
  80. /* We expect xgmii faults if the wireside link is up */
  81. if (!EFX_WORKAROUND_5147(efx) || !efx->link_up)
  82. return;
  83. /* We can only use this interrupt to signal the negative edge of
  84. * xaui_align [we have to poll the positive edge]. */
  85. if (!efx->mac_up)
  86. return;
  87. /* Flush the ISR */
  88. if (enable)
  89. falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
  90. EFX_POPULATE_OWORD_2(reg,
  91. XM_MSK_RMTFLT, !enable,
  92. XM_MSK_LCLFLT, !enable);
  93. falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0);
  94. }
  95. /* Get status of XAUI link */
  96. bool falcon_xaui_link_ok(struct efx_nic *efx)
  97. {
  98. efx_oword_t reg;
  99. bool align_done, link_ok = false;
  100. int sync_status;
  101. if (LOOPBACK_INTERNAL(efx))
  102. return true;
  103. /* Read link status */
  104. falcon_read(efx, &reg, XX_CORE_STAT_REG);
  105. align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);
  106. sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);
  107. if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
  108. link_ok = true;
  109. /* Clear link status ready for next read */
  110. EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
  111. EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
  112. EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
  113. falcon_write(efx, &reg, XX_CORE_STAT_REG);
  114. /* If the link is up, then check the phy side of the xaui link */
  115. if (efx->link_up && link_ok)
  116. if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
  117. link_ok = efx_mdio_phyxgxs_lane_sync(efx);
  118. return link_ok;
  119. }
  120. static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
  121. {
  122. unsigned int max_frame_len;
  123. efx_oword_t reg;
  124. bool rx_fc = !!(efx->link_fc & EFX_FC_RX);
  125. /* Configure MAC - cut-thru mode is hard wired on */
  126. EFX_POPULATE_DWORD_3(reg,
  127. XM_RX_JUMBO_MODE, 1,
  128. XM_TX_STAT_EN, 1,
  129. XM_RX_STAT_EN, 1);
  130. falcon_write(efx, &reg, XM_GLB_CFG_REG);
  131. /* Configure TX */
  132. EFX_POPULATE_DWORD_6(reg,
  133. XM_TXEN, 1,
  134. XM_TX_PRMBL, 1,
  135. XM_AUTO_PAD, 1,
  136. XM_TXCRC, 1,
  137. XM_FCNTL, 1,
  138. XM_IPG, 0x3);
  139. falcon_write(efx, &reg, XM_TX_CFG_REG);
  140. /* Configure RX */
  141. EFX_POPULATE_DWORD_5(reg,
  142. XM_RXEN, 1,
  143. XM_AUTO_DEPAD, 0,
  144. XM_ACPT_ALL_MCAST, 1,
  145. XM_ACPT_ALL_UCAST, efx->promiscuous,
  146. XM_PASS_CRC_ERR, 1);
  147. falcon_write(efx, &reg, XM_RX_CFG_REG);
  148. /* Set frame length */
  149. max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
  150. EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
  151. falcon_write(efx, &reg, XM_RX_PARAM_REG);
  152. EFX_POPULATE_DWORD_2(reg,
  153. XM_MAX_TX_FRM_SIZE, max_frame_len,
  154. XM_TX_JUMBO_MODE, 1);
  155. falcon_write(efx, &reg, XM_TX_PARAM_REG);
  156. EFX_POPULATE_DWORD_2(reg,
  157. XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
  158. XM_DIS_FCNTL, !rx_fc);
  159. falcon_write(efx, &reg, XM_FC_REG);
  160. /* Set MAC address */
  161. EFX_POPULATE_DWORD_4(reg,
  162. XM_ADR_0, efx->net_dev->dev_addr[0],
  163. XM_ADR_1, efx->net_dev->dev_addr[1],
  164. XM_ADR_2, efx->net_dev->dev_addr[2],
  165. XM_ADR_3, efx->net_dev->dev_addr[3]);
  166. falcon_write(efx, &reg, XM_ADR_LO_REG);
  167. EFX_POPULATE_DWORD_2(reg,
  168. XM_ADR_4, efx->net_dev->dev_addr[4],
  169. XM_ADR_5, efx->net_dev->dev_addr[5]);
  170. falcon_write(efx, &reg, XM_ADR_HI_REG);
  171. }
  172. static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
  173. {
  174. efx_oword_t reg;
  175. bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
  176. bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
  177. bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
  178. /* XGXS block is flaky and will need to be reset if moving
  179. * into our out of XGMII, XGXS or XAUI loopbacks. */
  180. if (EFX_WORKAROUND_5147(efx)) {
  181. bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
  182. bool reset_xgxs;
  183. falcon_read(efx, &reg, XX_CORE_STAT_REG);
  184. old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);
  185. old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);
  186. falcon_read(efx, &reg, XX_SD_CTL_REG);
  187. old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);
  188. /* The PHY driver may have turned XAUI off */
  189. reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
  190. (xaui_loopback != old_xaui_loopback) ||
  191. (xgmii_loopback != old_xgmii_loopback));
  192. if (reset_xgxs)
  193. falcon_reset_xaui(efx);
  194. }
  195. falcon_read(efx, &reg, XX_CORE_STAT_REG);
  196. EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,
  197. (xgxs_loopback || xaui_loopback) ?
  198. XX_FORCE_SIG_DECODE_FORCED : 0);
  199. EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
  200. EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
  201. falcon_write(efx, &reg, XX_CORE_STAT_REG);
  202. falcon_read(efx, &reg, XX_SD_CTL_REG);
  203. EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
  204. EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
  205. EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
  206. EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
  207. falcon_write(efx, &reg, XX_SD_CTL_REG);
  208. }
  209. /* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
  210. * to come back up. Bash it until it comes back up */
  211. static void falcon_check_xaui_link_up(struct efx_nic *efx, int tries)
  212. {
  213. efx->mac_up = falcon_xaui_link_ok(efx);
  214. if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
  215. efx_phy_mode_disabled(efx->phy_mode))
  216. /* XAUI link is expected to be down */
  217. return;
  218. while (!efx->mac_up && tries) {
  219. EFX_LOG(efx, "bashing xaui\n");
  220. falcon_reset_xaui(efx);
  221. udelay(200);
  222. efx->mac_up = falcon_xaui_link_ok(efx);
  223. --tries;
  224. }
  225. }
  226. static void falcon_reconfigure_xmac(struct efx_nic *efx)
  227. {
  228. falcon_mask_status_intr(efx, false);
  229. falcon_reconfigure_xgxs_core(efx);
  230. falcon_reconfigure_xmac_core(efx);
  231. falcon_reconfigure_mac_wrapper(efx);
  232. falcon_check_xaui_link_up(efx, 5);
  233. falcon_mask_status_intr(efx, true);
  234. }
  235. static void falcon_update_stats_xmac(struct efx_nic *efx)
  236. {
  237. struct efx_mac_stats *mac_stats = &efx->mac_stats;
  238. int rc;
  239. rc = falcon_dma_stats(efx, XgDmaDone_offset);
  240. if (rc)
  241. return;
  242. /* Update MAC stats from DMAed values */
  243. FALCON_STAT(efx, XgRxOctets, rx_bytes);
  244. FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
  245. FALCON_STAT(efx, XgRxPkts, rx_packets);
  246. FALCON_STAT(efx, XgRxPktsOK, rx_good);
  247. FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
  248. FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
  249. FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
  250. FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
  251. FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
  252. FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
  253. FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
  254. FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
  255. FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
  256. FALCON_STAT(efx, XgRxAlignError, rx_align_error);
  257. FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
  258. FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
  259. FALCON_STAT(efx, XgRxControlPkts, rx_control);
  260. FALCON_STAT(efx, XgRxPausePkts, rx_pause);
  261. FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
  262. FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
  263. FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
  264. FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
  265. FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
  266. FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
  267. FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
  268. FALCON_STAT(efx, XgRxLengthError, rx_length_error);
  269. FALCON_STAT(efx, XgTxPkts, tx_packets);
  270. FALCON_STAT(efx, XgTxOctets, tx_bytes);
  271. FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
  272. FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
  273. FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
  274. FALCON_STAT(efx, XgTxControlPkts, tx_control);
  275. FALCON_STAT(efx, XgTxPausePkts, tx_pause);
  276. FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
  277. FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
  278. FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
  279. FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
  280. FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
  281. FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
  282. FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
  283. FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
  284. FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
  285. FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
  286. FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
  287. FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
  288. /* Update derived statistics */
  289. mac_stats->tx_good_bytes =
  290. (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
  291. mac_stats->tx_control * 64);
  292. mac_stats->rx_bad_bytes =
  293. (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
  294. mac_stats->rx_control * 64);
  295. }
  296. static void falcon_xmac_irq(struct efx_nic *efx)
  297. {
  298. /* The XGMII link has a transient fault, which indicates either:
  299. * - there's a transient xgmii fault
  300. * - falcon's end of the xaui link may need a kick
  301. * - the wire-side link may have gone down, but the lasi/poll()
  302. * hasn't noticed yet.
  303. *
  304. * We only want to even bother polling XAUI if we're confident it's
  305. * not (1) or (3). In both cases, the only reliable way to spot this
  306. * is to wait a bit. We do this here by forcing the mac link state
  307. * to down, and waiting for the mac poll to come round and check
  308. */
  309. efx->mac_up = false;
  310. }
  311. static void falcon_poll_xmac(struct efx_nic *efx)
  312. {
  313. if (!EFX_WORKAROUND_5147(efx) || !efx->link_up || efx->mac_up)
  314. return;
  315. falcon_mask_status_intr(efx, false);
  316. falcon_check_xaui_link_up(efx, 1);
  317. falcon_mask_status_intr(efx, true);
  318. }
  319. struct efx_mac_operations falcon_xmac_operations = {
  320. .reconfigure = falcon_reconfigure_xmac,
  321. .update_stats = falcon_update_stats_xmac,
  322. .irq = falcon_xmac_irq,
  323. .poll = falcon_poll_xmac,
  324. };