marvell.c 14 KB

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  1. /*
  2. * drivers/net/phy/marvell.c
  3. *
  4. * Driver for Marvell PHYs
  5. *
  6. * Author: Andy Fleming
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/unistd.h>
  20. #include <linux/slab.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/init.h>
  23. #include <linux/delay.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/skbuff.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/mm.h>
  29. #include <linux/module.h>
  30. #include <linux/mii.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/phy.h>
  33. #include <asm/io.h>
  34. #include <asm/irq.h>
  35. #include <asm/uaccess.h>
  36. #define MII_M1011_IEVENT 0x13
  37. #define MII_M1011_IEVENT_CLEAR 0x0000
  38. #define MII_M1011_IMASK 0x12
  39. #define MII_M1011_IMASK_INIT 0x6400
  40. #define MII_M1011_IMASK_CLEAR 0x0000
  41. #define MII_M1011_PHY_SCR 0x10
  42. #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
  43. #define MII_M1145_PHY_EXT_CR 0x14
  44. #define MII_M1145_RGMII_RX_DELAY 0x0080
  45. #define MII_M1145_RGMII_TX_DELAY 0x0002
  46. #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
  47. #define MII_M1111_PHY_LED_CONTROL 0x18
  48. #define MII_M1111_PHY_LED_DIRECT 0x4100
  49. #define MII_M1111_PHY_LED_COMBINE 0x411c
  50. #define MII_M1111_PHY_EXT_CR 0x14
  51. #define MII_M1111_RX_DELAY 0x80
  52. #define MII_M1111_TX_DELAY 0x2
  53. #define MII_M1111_PHY_EXT_SR 0x1b
  54. #define MII_M1111_HWCFG_MODE_MASK 0xf
  55. #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
  56. #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
  57. #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
  58. #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
  59. #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
  60. #define MII_M1111_COPPER 0
  61. #define MII_M1111_FIBER 1
  62. #define MII_88E1121_PHY_LED_CTRL 16
  63. #define MII_88E1121_PHY_LED_PAGE 3
  64. #define MII_88E1121_PHY_LED_DEF 0x0030
  65. #define MII_88E1121_PHY_PAGE 22
  66. #define MII_M1011_PHY_STATUS 0x11
  67. #define MII_M1011_PHY_STATUS_1000 0x8000
  68. #define MII_M1011_PHY_STATUS_100 0x4000
  69. #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
  70. #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
  71. #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
  72. #define MII_M1011_PHY_STATUS_LINK 0x0400
  73. MODULE_DESCRIPTION("Marvell PHY driver");
  74. MODULE_AUTHOR("Andy Fleming");
  75. MODULE_LICENSE("GPL");
  76. static int marvell_ack_interrupt(struct phy_device *phydev)
  77. {
  78. int err;
  79. /* Clear the interrupts by reading the reg */
  80. err = phy_read(phydev, MII_M1011_IEVENT);
  81. if (err < 0)
  82. return err;
  83. return 0;
  84. }
  85. static int marvell_config_intr(struct phy_device *phydev)
  86. {
  87. int err;
  88. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  89. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
  90. else
  91. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
  92. return err;
  93. }
  94. static int marvell_config_aneg(struct phy_device *phydev)
  95. {
  96. int err;
  97. /* The Marvell PHY has an errata which requires
  98. * that certain registers get written in order
  99. * to restart autonegotiation */
  100. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  101. if (err < 0)
  102. return err;
  103. err = phy_write(phydev, 0x1d, 0x1f);
  104. if (err < 0)
  105. return err;
  106. err = phy_write(phydev, 0x1e, 0x200c);
  107. if (err < 0)
  108. return err;
  109. err = phy_write(phydev, 0x1d, 0x5);
  110. if (err < 0)
  111. return err;
  112. err = phy_write(phydev, 0x1e, 0);
  113. if (err < 0)
  114. return err;
  115. err = phy_write(phydev, 0x1e, 0x100);
  116. if (err < 0)
  117. return err;
  118. err = phy_write(phydev, MII_M1011_PHY_SCR,
  119. MII_M1011_PHY_SCR_AUTO_CROSS);
  120. if (err < 0)
  121. return err;
  122. err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
  123. MII_M1111_PHY_LED_DIRECT);
  124. if (err < 0)
  125. return err;
  126. err = genphy_config_aneg(phydev);
  127. if (err < 0)
  128. return err;
  129. if (phydev->autoneg != AUTONEG_ENABLE) {
  130. int bmcr;
  131. /*
  132. * A write to speed/duplex bits (that is performed by
  133. * genphy_config_aneg() call above) must be followed by
  134. * a software reset. Otherwise, the write has no effect.
  135. */
  136. bmcr = phy_read(phydev, MII_BMCR);
  137. if (bmcr < 0)
  138. return bmcr;
  139. err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
  140. if (err < 0)
  141. return err;
  142. }
  143. return 0;
  144. }
  145. static int m88e1121_config_aneg(struct phy_device *phydev)
  146. {
  147. int err, temp;
  148. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  149. if (err < 0)
  150. return err;
  151. err = phy_write(phydev, MII_M1011_PHY_SCR,
  152. MII_M1011_PHY_SCR_AUTO_CROSS);
  153. if (err < 0)
  154. return err;
  155. temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
  156. phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
  157. phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
  158. phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
  159. err = genphy_config_aneg(phydev);
  160. return err;
  161. }
  162. static int m88e1111_config_init(struct phy_device *phydev)
  163. {
  164. int err;
  165. int temp;
  166. /* Enable Fiber/Copper auto selection */
  167. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  168. temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  169. phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  170. temp = phy_read(phydev, MII_BMCR);
  171. temp |= BMCR_RESET;
  172. phy_write(phydev, MII_BMCR, temp);
  173. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  174. (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  175. (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
  176. (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
  177. temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
  178. if (temp < 0)
  179. return temp;
  180. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  181. temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
  182. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  183. temp &= ~MII_M1111_TX_DELAY;
  184. temp |= MII_M1111_RX_DELAY;
  185. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  186. temp &= ~MII_M1111_RX_DELAY;
  187. temp |= MII_M1111_TX_DELAY;
  188. }
  189. err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
  190. if (err < 0)
  191. return err;
  192. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  193. if (temp < 0)
  194. return temp;
  195. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  196. if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
  197. temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
  198. else
  199. temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
  200. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  201. if (err < 0)
  202. return err;
  203. }
  204. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  205. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  206. if (temp < 0)
  207. return temp;
  208. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  209. temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
  210. temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  211. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  212. if (err < 0)
  213. return err;
  214. }
  215. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  216. if (err < 0)
  217. return err;
  218. return 0;
  219. }
  220. static int m88e1118_config_aneg(struct phy_device *phydev)
  221. {
  222. int err;
  223. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  224. if (err < 0)
  225. return err;
  226. err = phy_write(phydev, MII_M1011_PHY_SCR,
  227. MII_M1011_PHY_SCR_AUTO_CROSS);
  228. if (err < 0)
  229. return err;
  230. err = genphy_config_aneg(phydev);
  231. return 0;
  232. }
  233. static int m88e1118_config_init(struct phy_device *phydev)
  234. {
  235. int err;
  236. /* Change address */
  237. err = phy_write(phydev, 0x16, 0x0002);
  238. if (err < 0)
  239. return err;
  240. /* Enable 1000 Mbit */
  241. err = phy_write(phydev, 0x15, 0x1070);
  242. if (err < 0)
  243. return err;
  244. /* Change address */
  245. err = phy_write(phydev, 0x16, 0x0003);
  246. if (err < 0)
  247. return err;
  248. /* Adjust LED Control */
  249. err = phy_write(phydev, 0x10, 0x021e);
  250. if (err < 0)
  251. return err;
  252. /* Reset address */
  253. err = phy_write(phydev, 0x16, 0x0);
  254. if (err < 0)
  255. return err;
  256. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  257. if (err < 0)
  258. return err;
  259. return 0;
  260. }
  261. static int m88e1145_config_init(struct phy_device *phydev)
  262. {
  263. int err;
  264. /* Take care of errata E0 & E1 */
  265. err = phy_write(phydev, 0x1d, 0x001b);
  266. if (err < 0)
  267. return err;
  268. err = phy_write(phydev, 0x1e, 0x418f);
  269. if (err < 0)
  270. return err;
  271. err = phy_write(phydev, 0x1d, 0x0016);
  272. if (err < 0)
  273. return err;
  274. err = phy_write(phydev, 0x1e, 0xa2da);
  275. if (err < 0)
  276. return err;
  277. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  278. int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
  279. if (temp < 0)
  280. return temp;
  281. temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
  282. err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
  283. if (err < 0)
  284. return err;
  285. if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
  286. err = phy_write(phydev, 0x1d, 0x0012);
  287. if (err < 0)
  288. return err;
  289. temp = phy_read(phydev, 0x1e);
  290. if (temp < 0)
  291. return temp;
  292. temp &= 0xf03f;
  293. temp |= 2 << 9; /* 36 ohm */
  294. temp |= 2 << 6; /* 39 ohm */
  295. err = phy_write(phydev, 0x1e, temp);
  296. if (err < 0)
  297. return err;
  298. err = phy_write(phydev, 0x1d, 0x3);
  299. if (err < 0)
  300. return err;
  301. err = phy_write(phydev, 0x1e, 0x8000);
  302. if (err < 0)
  303. return err;
  304. }
  305. }
  306. return 0;
  307. }
  308. /* marvell_read_status
  309. *
  310. * Generic status code does not detect Fiber correctly!
  311. * Description:
  312. * Check the link, then figure out the current state
  313. * by comparing what we advertise with what the link partner
  314. * advertises. Start by checking the gigabit possibilities,
  315. * then move on to 10/100.
  316. */
  317. static int marvell_read_status(struct phy_device *phydev)
  318. {
  319. int adv;
  320. int err;
  321. int lpa;
  322. int status = 0;
  323. /* Update the link, but return if there
  324. * was an error */
  325. err = genphy_update_link(phydev);
  326. if (err)
  327. return err;
  328. if (AUTONEG_ENABLE == phydev->autoneg) {
  329. status = phy_read(phydev, MII_M1011_PHY_STATUS);
  330. if (status < 0)
  331. return status;
  332. lpa = phy_read(phydev, MII_LPA);
  333. if (lpa < 0)
  334. return lpa;
  335. adv = phy_read(phydev, MII_ADVERTISE);
  336. if (adv < 0)
  337. return adv;
  338. lpa &= adv;
  339. if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
  340. phydev->duplex = DUPLEX_FULL;
  341. else
  342. phydev->duplex = DUPLEX_HALF;
  343. status = status & MII_M1011_PHY_STATUS_SPD_MASK;
  344. phydev->pause = phydev->asym_pause = 0;
  345. switch (status) {
  346. case MII_M1011_PHY_STATUS_1000:
  347. phydev->speed = SPEED_1000;
  348. break;
  349. case MII_M1011_PHY_STATUS_100:
  350. phydev->speed = SPEED_100;
  351. break;
  352. default:
  353. phydev->speed = SPEED_10;
  354. break;
  355. }
  356. if (phydev->duplex == DUPLEX_FULL) {
  357. phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
  358. phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
  359. }
  360. } else {
  361. int bmcr = phy_read(phydev, MII_BMCR);
  362. if (bmcr < 0)
  363. return bmcr;
  364. if (bmcr & BMCR_FULLDPLX)
  365. phydev->duplex = DUPLEX_FULL;
  366. else
  367. phydev->duplex = DUPLEX_HALF;
  368. if (bmcr & BMCR_SPEED1000)
  369. phydev->speed = SPEED_1000;
  370. else if (bmcr & BMCR_SPEED100)
  371. phydev->speed = SPEED_100;
  372. else
  373. phydev->speed = SPEED_10;
  374. phydev->pause = phydev->asym_pause = 0;
  375. }
  376. return 0;
  377. }
  378. static int m88e1121_did_interrupt(struct phy_device *phydev)
  379. {
  380. int imask;
  381. imask = phy_read(phydev, MII_M1011_IEVENT);
  382. if (imask & MII_M1011_IMASK_INIT)
  383. return 1;
  384. return 0;
  385. }
  386. static struct phy_driver marvell_drivers[] = {
  387. {
  388. .phy_id = 0x01410c60,
  389. .phy_id_mask = 0xfffffff0,
  390. .name = "Marvell 88E1101",
  391. .features = PHY_GBIT_FEATURES,
  392. .flags = PHY_HAS_INTERRUPT,
  393. .config_aneg = &marvell_config_aneg,
  394. .read_status = &genphy_read_status,
  395. .ack_interrupt = &marvell_ack_interrupt,
  396. .config_intr = &marvell_config_intr,
  397. .driver = { .owner = THIS_MODULE },
  398. },
  399. {
  400. .phy_id = 0x01410c90,
  401. .phy_id_mask = 0xfffffff0,
  402. .name = "Marvell 88E1112",
  403. .features = PHY_GBIT_FEATURES,
  404. .flags = PHY_HAS_INTERRUPT,
  405. .config_init = &m88e1111_config_init,
  406. .config_aneg = &marvell_config_aneg,
  407. .read_status = &genphy_read_status,
  408. .ack_interrupt = &marvell_ack_interrupt,
  409. .config_intr = &marvell_config_intr,
  410. .driver = { .owner = THIS_MODULE },
  411. },
  412. {
  413. .phy_id = 0x01410cc0,
  414. .phy_id_mask = 0xfffffff0,
  415. .name = "Marvell 88E1111",
  416. .features = PHY_GBIT_FEATURES,
  417. .flags = PHY_HAS_INTERRUPT,
  418. .config_init = &m88e1111_config_init,
  419. .config_aneg = &marvell_config_aneg,
  420. .read_status = &marvell_read_status,
  421. .ack_interrupt = &marvell_ack_interrupt,
  422. .config_intr = &marvell_config_intr,
  423. .driver = { .owner = THIS_MODULE },
  424. },
  425. {
  426. .phy_id = 0x01410e10,
  427. .phy_id_mask = 0xfffffff0,
  428. .name = "Marvell 88E1118",
  429. .features = PHY_GBIT_FEATURES,
  430. .flags = PHY_HAS_INTERRUPT,
  431. .config_init = &m88e1118_config_init,
  432. .config_aneg = &m88e1118_config_aneg,
  433. .read_status = &genphy_read_status,
  434. .ack_interrupt = &marvell_ack_interrupt,
  435. .config_intr = &marvell_config_intr,
  436. .driver = {.owner = THIS_MODULE,},
  437. },
  438. {
  439. .phy_id = 0x01410cb0,
  440. .phy_id_mask = 0xfffffff0,
  441. .name = "Marvell 88E1121R",
  442. .features = PHY_GBIT_FEATURES,
  443. .flags = PHY_HAS_INTERRUPT,
  444. .config_aneg = &m88e1121_config_aneg,
  445. .read_status = &marvell_read_status,
  446. .ack_interrupt = &marvell_ack_interrupt,
  447. .config_intr = &marvell_config_intr,
  448. .did_interrupt = &m88e1121_did_interrupt,
  449. .driver = { .owner = THIS_MODULE },
  450. },
  451. {
  452. .phy_id = 0x01410cd0,
  453. .phy_id_mask = 0xfffffff0,
  454. .name = "Marvell 88E1145",
  455. .features = PHY_GBIT_FEATURES,
  456. .flags = PHY_HAS_INTERRUPT,
  457. .config_init = &m88e1145_config_init,
  458. .config_aneg = &marvell_config_aneg,
  459. .read_status = &genphy_read_status,
  460. .ack_interrupt = &marvell_ack_interrupt,
  461. .config_intr = &marvell_config_intr,
  462. .driver = { .owner = THIS_MODULE },
  463. },
  464. {
  465. .phy_id = 0x01410e30,
  466. .phy_id_mask = 0xfffffff0,
  467. .name = "Marvell 88E1240",
  468. .features = PHY_GBIT_FEATURES,
  469. .flags = PHY_HAS_INTERRUPT,
  470. .config_init = &m88e1111_config_init,
  471. .config_aneg = &marvell_config_aneg,
  472. .read_status = &genphy_read_status,
  473. .ack_interrupt = &marvell_ack_interrupt,
  474. .config_intr = &marvell_config_intr,
  475. .driver = { .owner = THIS_MODULE },
  476. },
  477. };
  478. static int __init marvell_init(void)
  479. {
  480. int ret;
  481. int i;
  482. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
  483. ret = phy_driver_register(&marvell_drivers[i]);
  484. if (ret) {
  485. while (i-- > 0)
  486. phy_driver_unregister(&marvell_drivers[i]);
  487. return ret;
  488. }
  489. }
  490. return 0;
  491. }
  492. static void __exit marvell_exit(void)
  493. {
  494. int i;
  495. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
  496. phy_driver_unregister(&marvell_drivers[i]);
  497. }
  498. module_init(marvell_init);
  499. module_exit(marvell_exit);