netxen_nic_init.c 38 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include "netxen_nic.h"
  28. #include "netxen_nic_hw.h"
  29. struct crb_addr_pair {
  30. u32 addr;
  31. u32 data;
  32. };
  33. #define NETXEN_MAX_CRB_XFORM 60
  34. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  35. #define NETXEN_ADDR_ERROR (0xffffffff)
  36. #define crb_addr_transform(name) \
  37. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  38. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  39. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  40. static void
  41. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  42. struct nx_host_rds_ring *rds_ring);
  43. static void crb_addr_transform_setup(void)
  44. {
  45. crb_addr_transform(XDMA);
  46. crb_addr_transform(TIMR);
  47. crb_addr_transform(SRE);
  48. crb_addr_transform(SQN3);
  49. crb_addr_transform(SQN2);
  50. crb_addr_transform(SQN1);
  51. crb_addr_transform(SQN0);
  52. crb_addr_transform(SQS3);
  53. crb_addr_transform(SQS2);
  54. crb_addr_transform(SQS1);
  55. crb_addr_transform(SQS0);
  56. crb_addr_transform(RPMX7);
  57. crb_addr_transform(RPMX6);
  58. crb_addr_transform(RPMX5);
  59. crb_addr_transform(RPMX4);
  60. crb_addr_transform(RPMX3);
  61. crb_addr_transform(RPMX2);
  62. crb_addr_transform(RPMX1);
  63. crb_addr_transform(RPMX0);
  64. crb_addr_transform(ROMUSB);
  65. crb_addr_transform(SN);
  66. crb_addr_transform(QMN);
  67. crb_addr_transform(QMS);
  68. crb_addr_transform(PGNI);
  69. crb_addr_transform(PGND);
  70. crb_addr_transform(PGN3);
  71. crb_addr_transform(PGN2);
  72. crb_addr_transform(PGN1);
  73. crb_addr_transform(PGN0);
  74. crb_addr_transform(PGSI);
  75. crb_addr_transform(PGSD);
  76. crb_addr_transform(PGS3);
  77. crb_addr_transform(PGS2);
  78. crb_addr_transform(PGS1);
  79. crb_addr_transform(PGS0);
  80. crb_addr_transform(PS);
  81. crb_addr_transform(PH);
  82. crb_addr_transform(NIU);
  83. crb_addr_transform(I2Q);
  84. crb_addr_transform(EG);
  85. crb_addr_transform(MN);
  86. crb_addr_transform(MS);
  87. crb_addr_transform(CAS2);
  88. crb_addr_transform(CAS1);
  89. crb_addr_transform(CAS0);
  90. crb_addr_transform(CAM);
  91. crb_addr_transform(C2C1);
  92. crb_addr_transform(C2C0);
  93. crb_addr_transform(SMB);
  94. crb_addr_transform(OCM0);
  95. crb_addr_transform(I2C0);
  96. }
  97. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  98. {
  99. struct netxen_recv_context *recv_ctx;
  100. struct nx_host_rds_ring *rds_ring;
  101. struct netxen_rx_buffer *rx_buf;
  102. int i, ring;
  103. recv_ctx = &adapter->recv_ctx;
  104. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  105. rds_ring = &recv_ctx->rds_rings[ring];
  106. for (i = 0; i < rds_ring->num_desc; ++i) {
  107. rx_buf = &(rds_ring->rx_buf_arr[i]);
  108. if (rx_buf->state == NETXEN_BUFFER_FREE)
  109. continue;
  110. pci_unmap_single(adapter->pdev,
  111. rx_buf->dma,
  112. rds_ring->dma_size,
  113. PCI_DMA_FROMDEVICE);
  114. if (rx_buf->skb != NULL)
  115. dev_kfree_skb_any(rx_buf->skb);
  116. }
  117. }
  118. }
  119. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  120. {
  121. struct netxen_cmd_buffer *cmd_buf;
  122. struct netxen_skb_frag *buffrag;
  123. int i, j;
  124. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  125. cmd_buf = tx_ring->cmd_buf_arr;
  126. for (i = 0; i < tx_ring->num_desc; i++) {
  127. buffrag = cmd_buf->frag_array;
  128. if (buffrag->dma) {
  129. pci_unmap_single(adapter->pdev, buffrag->dma,
  130. buffrag->length, PCI_DMA_TODEVICE);
  131. buffrag->dma = 0ULL;
  132. }
  133. for (j = 0; j < cmd_buf->frag_count; j++) {
  134. buffrag++;
  135. if (buffrag->dma) {
  136. pci_unmap_page(adapter->pdev, buffrag->dma,
  137. buffrag->length,
  138. PCI_DMA_TODEVICE);
  139. buffrag->dma = 0ULL;
  140. }
  141. }
  142. if (cmd_buf->skb) {
  143. dev_kfree_skb_any(cmd_buf->skb);
  144. cmd_buf->skb = NULL;
  145. }
  146. cmd_buf++;
  147. }
  148. }
  149. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  150. {
  151. struct netxen_recv_context *recv_ctx;
  152. struct nx_host_rds_ring *rds_ring;
  153. struct nx_host_tx_ring *tx_ring;
  154. int ring;
  155. recv_ctx = &adapter->recv_ctx;
  156. if (recv_ctx->rds_rings == NULL)
  157. goto skip_rds;
  158. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  159. rds_ring = &recv_ctx->rds_rings[ring];
  160. vfree(rds_ring->rx_buf_arr);
  161. rds_ring->rx_buf_arr = NULL;
  162. }
  163. kfree(recv_ctx->rds_rings);
  164. skip_rds:
  165. if (adapter->tx_ring == NULL)
  166. return;
  167. tx_ring = adapter->tx_ring;
  168. vfree(tx_ring->cmd_buf_arr);
  169. }
  170. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  171. {
  172. struct netxen_recv_context *recv_ctx;
  173. struct nx_host_rds_ring *rds_ring;
  174. struct nx_host_sds_ring *sds_ring;
  175. struct nx_host_tx_ring *tx_ring;
  176. struct netxen_rx_buffer *rx_buf;
  177. int ring, i, size;
  178. struct netxen_cmd_buffer *cmd_buf_arr;
  179. struct net_device *netdev = adapter->netdev;
  180. struct pci_dev *pdev = adapter->pdev;
  181. size = sizeof(struct nx_host_tx_ring);
  182. tx_ring = kzalloc(size, GFP_KERNEL);
  183. if (tx_ring == NULL) {
  184. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  185. netdev->name);
  186. return -ENOMEM;
  187. }
  188. adapter->tx_ring = tx_ring;
  189. tx_ring->num_desc = adapter->num_txd;
  190. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  191. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  192. if (cmd_buf_arr == NULL) {
  193. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  194. netdev->name);
  195. return -ENOMEM;
  196. }
  197. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  198. tx_ring->cmd_buf_arr = cmd_buf_arr;
  199. recv_ctx = &adapter->recv_ctx;
  200. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  201. rds_ring = kzalloc(size, GFP_KERNEL);
  202. if (rds_ring == NULL) {
  203. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  204. netdev->name);
  205. return -ENOMEM;
  206. }
  207. recv_ctx->rds_rings = rds_ring;
  208. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  209. rds_ring = &recv_ctx->rds_rings[ring];
  210. switch (ring) {
  211. case RCV_RING_NORMAL:
  212. rds_ring->num_desc = adapter->num_rxd;
  213. if (adapter->ahw.cut_through) {
  214. rds_ring->dma_size =
  215. NX_CT_DEFAULT_RX_BUF_LEN;
  216. rds_ring->skb_size =
  217. NX_CT_DEFAULT_RX_BUF_LEN;
  218. } else {
  219. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  220. rds_ring->dma_size =
  221. NX_P3_RX_BUF_MAX_LEN;
  222. else
  223. rds_ring->dma_size =
  224. NX_P2_RX_BUF_MAX_LEN;
  225. rds_ring->skb_size =
  226. rds_ring->dma_size + NET_IP_ALIGN;
  227. }
  228. break;
  229. case RCV_RING_JUMBO:
  230. rds_ring->num_desc = adapter->num_jumbo_rxd;
  231. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  232. rds_ring->dma_size =
  233. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  234. else
  235. rds_ring->dma_size =
  236. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  237. if (adapter->capabilities & NX_CAP0_HW_LRO)
  238. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  239. rds_ring->skb_size =
  240. rds_ring->dma_size + NET_IP_ALIGN;
  241. break;
  242. case RCV_RING_LRO:
  243. rds_ring->num_desc = adapter->num_lro_rxd;
  244. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  245. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  246. break;
  247. }
  248. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  249. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  250. if (rds_ring->rx_buf_arr == NULL) {
  251. printk(KERN_ERR "%s: Failed to allocate "
  252. "rx buffer ring %d\n",
  253. netdev->name, ring);
  254. /* free whatever was already allocated */
  255. goto err_out;
  256. }
  257. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  258. INIT_LIST_HEAD(&rds_ring->free_list);
  259. /*
  260. * Now go through all of them, set reference handles
  261. * and put them in the queues.
  262. */
  263. rx_buf = rds_ring->rx_buf_arr;
  264. for (i = 0; i < rds_ring->num_desc; i++) {
  265. list_add_tail(&rx_buf->list,
  266. &rds_ring->free_list);
  267. rx_buf->ref_handle = i;
  268. rx_buf->state = NETXEN_BUFFER_FREE;
  269. rx_buf++;
  270. }
  271. spin_lock_init(&rds_ring->lock);
  272. }
  273. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  274. sds_ring = &recv_ctx->sds_rings[ring];
  275. sds_ring->irq = adapter->msix_entries[ring].vector;
  276. sds_ring->adapter = adapter;
  277. sds_ring->num_desc = adapter->num_rxd;
  278. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  279. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  280. }
  281. return 0;
  282. err_out:
  283. netxen_free_sw_resources(adapter);
  284. return -ENOMEM;
  285. }
  286. /*
  287. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  288. * address to external PCI CRB address.
  289. */
  290. static u32 netxen_decode_crb_addr(u32 addr)
  291. {
  292. int i;
  293. u32 base_addr, offset, pci_base;
  294. crb_addr_transform_setup();
  295. pci_base = NETXEN_ADDR_ERROR;
  296. base_addr = addr & 0xfff00000;
  297. offset = addr & 0x000fffff;
  298. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  299. if (crb_addr_xform[i] == base_addr) {
  300. pci_base = i << 20;
  301. break;
  302. }
  303. }
  304. if (pci_base == NETXEN_ADDR_ERROR)
  305. return pci_base;
  306. else
  307. return (pci_base + offset);
  308. }
  309. #define NETXEN_MAX_ROM_WAIT_USEC 100
  310. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  311. {
  312. long timeout = 0;
  313. long done = 0;
  314. cond_resched();
  315. while (done == 0) {
  316. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  317. done &= 2;
  318. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  319. dev_err(&adapter->pdev->dev,
  320. "Timeout reached waiting for rom done");
  321. return -EIO;
  322. }
  323. udelay(1);
  324. }
  325. return 0;
  326. }
  327. static int do_rom_fast_read(struct netxen_adapter *adapter,
  328. int addr, int *valp)
  329. {
  330. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  331. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  332. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  334. if (netxen_wait_rom_done(adapter)) {
  335. printk("Error waiting for rom done\n");
  336. return -EIO;
  337. }
  338. /* reset abyte_cnt and dummy_byte_cnt */
  339. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  340. udelay(10);
  341. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  342. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  343. return 0;
  344. }
  345. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  346. u8 *bytes, size_t size)
  347. {
  348. int addridx;
  349. int ret = 0;
  350. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  351. int v;
  352. ret = do_rom_fast_read(adapter, addridx, &v);
  353. if (ret != 0)
  354. break;
  355. *(__le32 *)bytes = cpu_to_le32(v);
  356. bytes += 4;
  357. }
  358. return ret;
  359. }
  360. int
  361. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  362. u8 *bytes, size_t size)
  363. {
  364. int ret;
  365. ret = netxen_rom_lock(adapter);
  366. if (ret < 0)
  367. return ret;
  368. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  369. netxen_rom_unlock(adapter);
  370. return ret;
  371. }
  372. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  373. {
  374. int ret;
  375. if (netxen_rom_lock(adapter) != 0)
  376. return -EIO;
  377. ret = do_rom_fast_read(adapter, addr, valp);
  378. netxen_rom_unlock(adapter);
  379. return ret;
  380. }
  381. #define NETXEN_BOARDTYPE 0x4008
  382. #define NETXEN_BOARDNUM 0x400c
  383. #define NETXEN_CHIPNUM 0x4010
  384. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  385. {
  386. int addr, val;
  387. int i, n, init_delay = 0;
  388. struct crb_addr_pair *buf;
  389. unsigned offset;
  390. u32 off;
  391. /* resetall */
  392. netxen_rom_lock(adapter);
  393. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  394. netxen_rom_unlock(adapter);
  395. if (verbose) {
  396. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  397. printk("P2 ROM board type: 0x%08x\n", val);
  398. else
  399. printk("Could not read board type\n");
  400. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  401. printk("P2 ROM board num: 0x%08x\n", val);
  402. else
  403. printk("Could not read board number\n");
  404. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  405. printk("P2 ROM chip num: 0x%08x\n", val);
  406. else
  407. printk("Could not read chip number\n");
  408. }
  409. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  410. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  411. (n != 0xcafecafe) ||
  412. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  413. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  414. "n: %08x\n", netxen_nic_driver_name, n);
  415. return -EIO;
  416. }
  417. offset = n & 0xffffU;
  418. n = (n >> 16) & 0xffffU;
  419. } else {
  420. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  421. !(n & 0x80000000)) {
  422. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  423. "n: %08x\n", netxen_nic_driver_name, n);
  424. return -EIO;
  425. }
  426. offset = 1;
  427. n &= ~0x80000000;
  428. }
  429. if (n < 1024) {
  430. if (verbose)
  431. printk(KERN_DEBUG "%s: %d CRB init values found"
  432. " in ROM.\n", netxen_nic_driver_name, n);
  433. } else {
  434. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  435. " initialized.\n", __func__, n);
  436. return -EIO;
  437. }
  438. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  439. if (buf == NULL) {
  440. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  441. netxen_nic_driver_name);
  442. return -ENOMEM;
  443. }
  444. for (i = 0; i < n; i++) {
  445. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  446. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  447. kfree(buf);
  448. return -EIO;
  449. }
  450. buf[i].addr = addr;
  451. buf[i].data = val;
  452. if (verbose)
  453. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  454. netxen_nic_driver_name,
  455. (u32)netxen_decode_crb_addr(addr), val);
  456. }
  457. for (i = 0; i < n; i++) {
  458. off = netxen_decode_crb_addr(buf[i].addr);
  459. if (off == NETXEN_ADDR_ERROR) {
  460. printk(KERN_ERR"CRB init value out of range %x\n",
  461. buf[i].addr);
  462. continue;
  463. }
  464. off += NETXEN_PCI_CRBSPACE;
  465. /* skipping cold reboot MAGIC */
  466. if (off == NETXEN_CAM_RAM(0x1fc))
  467. continue;
  468. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  469. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  470. continue;
  471. /* do not reset PCI */
  472. if (off == (ROMUSB_GLB + 0xbc))
  473. continue;
  474. if (off == (ROMUSB_GLB + 0xa8))
  475. continue;
  476. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  477. continue;
  478. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  479. continue;
  480. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  481. continue;
  482. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  483. continue;
  484. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  485. buf[i].data = 0x1020;
  486. /* skip the function enable register */
  487. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  488. continue;
  489. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  490. continue;
  491. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  492. continue;
  493. }
  494. init_delay = 1;
  495. /* After writing this register, HW needs time for CRB */
  496. /* to quiet down (else crb_window returns 0xffffffff) */
  497. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  498. init_delay = 1000;
  499. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  500. /* hold xdma in reset also */
  501. buf[i].data = NETXEN_NIC_XDMA_RESET;
  502. buf[i].data = 0x8000ff;
  503. }
  504. }
  505. NXWR32(adapter, off, buf[i].data);
  506. msleep(init_delay);
  507. }
  508. kfree(buf);
  509. /* disable_peg_cache_all */
  510. /* unreset_net_cache */
  511. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  512. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  513. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  514. }
  515. /* p2dn replyCount */
  516. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  517. /* disable_peg_cache 0 */
  518. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  519. /* disable_peg_cache 1 */
  520. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  521. /* peg_clr_all */
  522. /* peg_clr 0 */
  523. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  524. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  525. /* peg_clr 1 */
  526. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  527. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  528. /* peg_clr 2 */
  529. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  530. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  531. /* peg_clr 3 */
  532. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  533. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  534. return 0;
  535. }
  536. int
  537. netxen_need_fw_reset(struct netxen_adapter *adapter)
  538. {
  539. u32 count, old_count;
  540. u32 val, version, major, minor, build;
  541. int i, timeout;
  542. u8 fw_type;
  543. /* NX2031 firmware doesn't support heartbit */
  544. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  545. return 1;
  546. /* last attempt had failed */
  547. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  548. return 1;
  549. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  550. for (i = 0; i < 10; i++) {
  551. timeout = msleep_interruptible(200);
  552. if (timeout) {
  553. NXWR32(adapter, CRB_CMDPEG_STATE,
  554. PHAN_INITIALIZE_FAILED);
  555. return -EINTR;
  556. }
  557. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  558. if (count != old_count)
  559. break;
  560. }
  561. /* firmware is dead */
  562. if (count == old_count)
  563. return 1;
  564. /* check if we have got newer or different file firmware */
  565. if (adapter->fw) {
  566. const struct firmware *fw = adapter->fw;
  567. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  568. version = NETXEN_DECODE_VERSION(val);
  569. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  570. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  571. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  572. if (version > NETXEN_VERSION_CODE(major, minor, build))
  573. return 1;
  574. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  575. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  576. fw_type = (val & 0x4) ?
  577. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  578. if (adapter->fw_type != fw_type)
  579. return 1;
  580. }
  581. }
  582. return 0;
  583. }
  584. static char *fw_name[] = {
  585. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  586. };
  587. int
  588. netxen_load_firmware(struct netxen_adapter *adapter)
  589. {
  590. u64 *ptr64;
  591. u32 i, flashaddr, size;
  592. const struct firmware *fw = adapter->fw;
  593. struct pci_dev *pdev = adapter->pdev;
  594. dev_info(&pdev->dev, "loading firmware from %s\n",
  595. fw_name[adapter->fw_type]);
  596. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  597. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  598. if (fw) {
  599. __le64 data;
  600. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  601. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  602. flashaddr = NETXEN_BOOTLD_START;
  603. for (i = 0; i < size; i++) {
  604. data = cpu_to_le64(ptr64[i]);
  605. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  606. flashaddr += 8;
  607. }
  608. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  609. size = (__force u32)cpu_to_le32(size) / 8;
  610. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  611. flashaddr = NETXEN_IMAGE_START;
  612. for (i = 0; i < size; i++) {
  613. data = cpu_to_le64(ptr64[i]);
  614. if (adapter->pci_mem_write(adapter,
  615. flashaddr, &data, 8))
  616. return -EIO;
  617. flashaddr += 8;
  618. }
  619. } else {
  620. u64 data;
  621. u32 hi, lo;
  622. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  623. flashaddr = NETXEN_BOOTLD_START;
  624. for (i = 0; i < size; i++) {
  625. if (netxen_rom_fast_read(adapter,
  626. flashaddr, &lo) != 0)
  627. return -EIO;
  628. if (netxen_rom_fast_read(adapter,
  629. flashaddr + 4, &hi) != 0)
  630. return -EIO;
  631. /* hi, lo are already in host endian byteorder */
  632. data = (((u64)hi << 32) | lo);
  633. if (adapter->pci_mem_write(adapter,
  634. flashaddr, &data, 8))
  635. return -EIO;
  636. flashaddr += 8;
  637. }
  638. }
  639. msleep(1);
  640. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  641. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  642. else {
  643. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  644. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  645. }
  646. return 0;
  647. }
  648. static int
  649. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  650. {
  651. __le32 val;
  652. u32 ver, min_ver, bios;
  653. struct pci_dev *pdev = adapter->pdev;
  654. const struct firmware *fw = adapter->fw;
  655. if (fw->size < NX_FW_MIN_SIZE)
  656. return -EINVAL;
  657. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  658. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  659. return -EINVAL;
  660. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  661. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  662. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  663. else
  664. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  665. ver = NETXEN_DECODE_VERSION(val);
  666. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  667. dev_err(&pdev->dev,
  668. "%s: firmware version %d.%d.%d unsupported\n",
  669. fwname, _major(ver), _minor(ver), _build(ver));
  670. return -EINVAL;
  671. }
  672. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  673. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  674. if ((__force u32)val != bios) {
  675. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  676. fwname);
  677. return -EINVAL;
  678. }
  679. /* check if flashed firmware is newer */
  680. if (netxen_rom_fast_read(adapter,
  681. NX_FW_VERSION_OFFSET, (int *)&val))
  682. return -EIO;
  683. val = NETXEN_DECODE_VERSION(val);
  684. if (val > ver) {
  685. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  686. fwname);
  687. return -EINVAL;
  688. }
  689. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  690. return 0;
  691. }
  692. static int
  693. netxen_p3_has_mn(struct netxen_adapter *adapter)
  694. {
  695. u32 capability, flashed_ver;
  696. capability = 0;
  697. netxen_rom_fast_read(adapter,
  698. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  699. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  700. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  701. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  702. if (capability & NX_PEG_TUNE_MN_PRESENT)
  703. return 1;
  704. }
  705. return 0;
  706. }
  707. void netxen_request_firmware(struct netxen_adapter *adapter)
  708. {
  709. u8 fw_type;
  710. struct pci_dev *pdev = adapter->pdev;
  711. int rc = 0;
  712. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  713. fw_type = NX_P2_MN_ROMIMAGE;
  714. goto request_fw;
  715. }
  716. fw_type = netxen_p3_has_mn(adapter) ?
  717. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  718. request_fw:
  719. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  720. if (rc != 0) {
  721. if (fw_type == NX_P3_MN_ROMIMAGE) {
  722. msleep(1);
  723. fw_type = NX_P3_CT_ROMIMAGE;
  724. goto request_fw;
  725. }
  726. fw_type = NX_FLASH_ROMIMAGE;
  727. adapter->fw = NULL;
  728. goto done;
  729. }
  730. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  731. if (rc != 0) {
  732. release_firmware(adapter->fw);
  733. if (fw_type == NX_P3_MN_ROMIMAGE) {
  734. msleep(1);
  735. fw_type = NX_P3_CT_ROMIMAGE;
  736. goto request_fw;
  737. }
  738. fw_type = NX_FLASH_ROMIMAGE;
  739. adapter->fw = NULL;
  740. goto done;
  741. }
  742. done:
  743. adapter->fw_type = fw_type;
  744. }
  745. void
  746. netxen_release_firmware(struct netxen_adapter *adapter)
  747. {
  748. if (adapter->fw)
  749. release_firmware(adapter->fw);
  750. adapter->fw = NULL;
  751. }
  752. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  753. {
  754. u64 addr;
  755. u32 hi, lo;
  756. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  757. return 0;
  758. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  759. NETXEN_HOST_DUMMY_DMA_SIZE,
  760. &adapter->dummy_dma.phys_addr);
  761. if (adapter->dummy_dma.addr == NULL) {
  762. dev_err(&adapter->pdev->dev,
  763. "ERROR: Could not allocate dummy DMA memory\n");
  764. return -ENOMEM;
  765. }
  766. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  767. hi = (addr >> 32) & 0xffffffff;
  768. lo = addr & 0xffffffff;
  769. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  770. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  771. return 0;
  772. }
  773. /*
  774. * NetXen DMA watchdog control:
  775. *
  776. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  777. * Bit 1 : disable_request => 1 req disable dma watchdog
  778. * Bit 2 : enable_request => 1 req enable dma watchdog
  779. * Bit 3-31 : unused
  780. */
  781. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  782. {
  783. int i = 100;
  784. u32 ctrl;
  785. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  786. return;
  787. if (!adapter->dummy_dma.addr)
  788. return;
  789. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  790. if ((ctrl & 0x1) != 0) {
  791. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  792. while ((ctrl & 0x1) != 0) {
  793. msleep(50);
  794. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  795. if (--i == 0)
  796. break;
  797. };
  798. }
  799. if (i) {
  800. pci_free_consistent(adapter->pdev,
  801. NETXEN_HOST_DUMMY_DMA_SIZE,
  802. adapter->dummy_dma.addr,
  803. adapter->dummy_dma.phys_addr);
  804. adapter->dummy_dma.addr = NULL;
  805. } else
  806. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  807. }
  808. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  809. {
  810. u32 val = 0;
  811. int retries = 60;
  812. if (pegtune_val)
  813. return 0;
  814. do {
  815. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  816. switch (val) {
  817. case PHAN_INITIALIZE_COMPLETE:
  818. case PHAN_INITIALIZE_ACK:
  819. return 0;
  820. case PHAN_INITIALIZE_FAILED:
  821. goto out_err;
  822. default:
  823. break;
  824. }
  825. msleep(500);
  826. } while (--retries);
  827. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  828. out_err:
  829. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  830. return -EIO;
  831. }
  832. static int
  833. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  834. {
  835. u32 val = 0;
  836. int retries = 2000;
  837. do {
  838. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  839. if (val == PHAN_PEG_RCV_INITIALIZED)
  840. return 0;
  841. msleep(10);
  842. } while (--retries);
  843. if (!retries) {
  844. printk(KERN_ERR "Receive Peg initialization not "
  845. "complete, state: 0x%x.\n", val);
  846. return -EIO;
  847. }
  848. return 0;
  849. }
  850. int netxen_init_firmware(struct netxen_adapter *adapter)
  851. {
  852. int err;
  853. err = netxen_receive_peg_ready(adapter);
  854. if (err)
  855. return err;
  856. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  857. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  858. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  859. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  860. return err;
  861. }
  862. static void
  863. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  864. {
  865. u32 cable_OUI;
  866. u16 cable_len;
  867. u16 link_speed;
  868. u8 link_status, module, duplex, autoneg;
  869. struct net_device *netdev = adapter->netdev;
  870. adapter->has_link_events = 1;
  871. cable_OUI = msg->body[1] & 0xffffffff;
  872. cable_len = (msg->body[1] >> 32) & 0xffff;
  873. link_speed = (msg->body[1] >> 48) & 0xffff;
  874. link_status = msg->body[2] & 0xff;
  875. duplex = (msg->body[2] >> 16) & 0xff;
  876. autoneg = (msg->body[2] >> 24) & 0xff;
  877. module = (msg->body[2] >> 8) & 0xff;
  878. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  879. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  880. netdev->name, cable_OUI, cable_len);
  881. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  882. printk(KERN_INFO "%s: unsupported cable length %d\n",
  883. netdev->name, cable_len);
  884. }
  885. netxen_advert_link_change(adapter, link_status);
  886. /* update link parameters */
  887. if (duplex == LINKEVENT_FULL_DUPLEX)
  888. adapter->link_duplex = DUPLEX_FULL;
  889. else
  890. adapter->link_duplex = DUPLEX_HALF;
  891. adapter->module_type = module;
  892. adapter->link_autoneg = autoneg;
  893. adapter->link_speed = link_speed;
  894. }
  895. static void
  896. netxen_handle_fw_message(int desc_cnt, int index,
  897. struct nx_host_sds_ring *sds_ring)
  898. {
  899. nx_fw_msg_t msg;
  900. struct status_desc *desc;
  901. int i = 0, opcode;
  902. while (desc_cnt > 0 && i < 8) {
  903. desc = &sds_ring->desc_head[index];
  904. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  905. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  906. index = get_next_index(index, sds_ring->num_desc);
  907. desc_cnt--;
  908. }
  909. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  910. switch (opcode) {
  911. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  912. netxen_handle_linkevent(sds_ring->adapter, &msg);
  913. break;
  914. default:
  915. break;
  916. }
  917. }
  918. static int
  919. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  920. struct nx_host_rds_ring *rds_ring,
  921. struct netxen_rx_buffer *buffer)
  922. {
  923. struct sk_buff *skb;
  924. dma_addr_t dma;
  925. struct pci_dev *pdev = adapter->pdev;
  926. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  927. if (!buffer->skb)
  928. return 1;
  929. skb = buffer->skb;
  930. if (!adapter->ahw.cut_through)
  931. skb_reserve(skb, 2);
  932. dma = pci_map_single(pdev, skb->data,
  933. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  934. if (pci_dma_mapping_error(pdev, dma)) {
  935. dev_kfree_skb_any(skb);
  936. buffer->skb = NULL;
  937. return 1;
  938. }
  939. buffer->skb = skb;
  940. buffer->dma = dma;
  941. buffer->state = NETXEN_BUFFER_BUSY;
  942. return 0;
  943. }
  944. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  945. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  946. {
  947. struct netxen_rx_buffer *buffer;
  948. struct sk_buff *skb;
  949. buffer = &rds_ring->rx_buf_arr[index];
  950. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  951. PCI_DMA_FROMDEVICE);
  952. skb = buffer->skb;
  953. if (!skb)
  954. goto no_skb;
  955. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  956. adapter->stats.csummed++;
  957. skb->ip_summed = CHECKSUM_UNNECESSARY;
  958. } else
  959. skb->ip_summed = CHECKSUM_NONE;
  960. skb->dev = adapter->netdev;
  961. buffer->skb = NULL;
  962. no_skb:
  963. buffer->state = NETXEN_BUFFER_FREE;
  964. return skb;
  965. }
  966. static struct netxen_rx_buffer *
  967. netxen_process_rcv(struct netxen_adapter *adapter,
  968. struct nx_host_sds_ring *sds_ring,
  969. int ring, u64 sts_data0)
  970. {
  971. struct net_device *netdev = adapter->netdev;
  972. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  973. struct netxen_rx_buffer *buffer;
  974. struct sk_buff *skb;
  975. struct nx_host_rds_ring *rds_ring;
  976. int index, length, cksum, pkt_offset;
  977. if (unlikely(ring >= adapter->max_rds_rings))
  978. return NULL;
  979. rds_ring = &recv_ctx->rds_rings[ring];
  980. index = netxen_get_sts_refhandle(sts_data0);
  981. if (unlikely(index >= rds_ring->num_desc))
  982. return NULL;
  983. buffer = &rds_ring->rx_buf_arr[index];
  984. length = netxen_get_sts_totallength(sts_data0);
  985. cksum = netxen_get_sts_status(sts_data0);
  986. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  987. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  988. if (!skb)
  989. return buffer;
  990. if (length > rds_ring->skb_size)
  991. skb_put(skb, rds_ring->skb_size);
  992. else
  993. skb_put(skb, length);
  994. if (pkt_offset)
  995. skb_pull(skb, pkt_offset);
  996. skb->truesize = skb->len + sizeof(struct sk_buff);
  997. skb->protocol = eth_type_trans(skb, netdev);
  998. napi_gro_receive(&sds_ring->napi, skb);
  999. adapter->stats.rx_pkts++;
  1000. adapter->stats.rxbytes += length;
  1001. return buffer;
  1002. }
  1003. #define TCP_HDR_SIZE 20
  1004. #define TCP_TS_OPTION_SIZE 12
  1005. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1006. static struct netxen_rx_buffer *
  1007. netxen_process_lro(struct netxen_adapter *adapter,
  1008. struct nx_host_sds_ring *sds_ring,
  1009. int ring, u64 sts_data0, u64 sts_data1)
  1010. {
  1011. struct net_device *netdev = adapter->netdev;
  1012. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1013. struct netxen_rx_buffer *buffer;
  1014. struct sk_buff *skb;
  1015. struct nx_host_rds_ring *rds_ring;
  1016. struct iphdr *iph;
  1017. struct tcphdr *th;
  1018. bool push, timestamp;
  1019. int l2_hdr_offset, l4_hdr_offset;
  1020. int index;
  1021. u16 lro_length, length, data_offset;
  1022. u32 seq_number;
  1023. if (unlikely(ring > adapter->max_rds_rings))
  1024. return NULL;
  1025. rds_ring = &recv_ctx->rds_rings[ring];
  1026. index = netxen_get_lro_sts_refhandle(sts_data0);
  1027. if (unlikely(index > rds_ring->num_desc))
  1028. return NULL;
  1029. buffer = &rds_ring->rx_buf_arr[index];
  1030. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1031. lro_length = netxen_get_lro_sts_length(sts_data0);
  1032. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1033. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1034. push = netxen_get_lro_sts_push_flag(sts_data0);
  1035. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1036. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1037. if (!skb)
  1038. return buffer;
  1039. if (timestamp)
  1040. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1041. else
  1042. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1043. skb_put(skb, lro_length + data_offset);
  1044. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1045. skb_pull(skb, l2_hdr_offset);
  1046. skb->protocol = eth_type_trans(skb, netdev);
  1047. iph = (struct iphdr *)skb->data;
  1048. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1049. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1050. iph->tot_len = htons(length);
  1051. iph->check = 0;
  1052. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1053. th->psh = push;
  1054. th->seq = htonl(seq_number);
  1055. length = skb->len;
  1056. netif_receive_skb(skb);
  1057. adapter->stats.lro_pkts++;
  1058. adapter->stats.rxbytes += length;
  1059. return buffer;
  1060. }
  1061. #define netxen_merge_rx_buffers(list, head) \
  1062. do { list_splice_tail_init(list, head); } while (0);
  1063. int
  1064. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1065. {
  1066. struct netxen_adapter *adapter = sds_ring->adapter;
  1067. struct list_head *cur;
  1068. struct status_desc *desc;
  1069. struct netxen_rx_buffer *rxbuf;
  1070. u32 consumer = sds_ring->consumer;
  1071. int count = 0;
  1072. u64 sts_data0, sts_data1;
  1073. int opcode, ring = 0, desc_cnt;
  1074. while (count < max) {
  1075. desc = &sds_ring->desc_head[consumer];
  1076. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1077. if (!(sts_data0 & STATUS_OWNER_HOST))
  1078. break;
  1079. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1080. opcode = netxen_get_sts_opcode(sts_data0);
  1081. switch (opcode) {
  1082. case NETXEN_NIC_RXPKT_DESC:
  1083. case NETXEN_OLD_RXPKT_DESC:
  1084. case NETXEN_NIC_SYN_OFFLOAD:
  1085. ring = netxen_get_sts_type(sts_data0);
  1086. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1087. ring, sts_data0);
  1088. break;
  1089. case NETXEN_NIC_LRO_DESC:
  1090. ring = netxen_get_lro_sts_type(sts_data0);
  1091. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1092. rxbuf = netxen_process_lro(adapter, sds_ring,
  1093. ring, sts_data0, sts_data1);
  1094. break;
  1095. case NETXEN_NIC_RESPONSE_DESC:
  1096. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1097. default:
  1098. goto skip;
  1099. }
  1100. WARN_ON(desc_cnt > 1);
  1101. if (rxbuf)
  1102. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1103. skip:
  1104. for (; desc_cnt > 0; desc_cnt--) {
  1105. desc = &sds_ring->desc_head[consumer];
  1106. desc->status_desc_data[0] =
  1107. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1108. consumer = get_next_index(consumer, sds_ring->num_desc);
  1109. }
  1110. count++;
  1111. }
  1112. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1113. struct nx_host_rds_ring *rds_ring =
  1114. &adapter->recv_ctx.rds_rings[ring];
  1115. if (!list_empty(&sds_ring->free_list[ring])) {
  1116. list_for_each(cur, &sds_ring->free_list[ring]) {
  1117. rxbuf = list_entry(cur,
  1118. struct netxen_rx_buffer, list);
  1119. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1120. }
  1121. spin_lock(&rds_ring->lock);
  1122. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1123. &rds_ring->free_list);
  1124. spin_unlock(&rds_ring->lock);
  1125. }
  1126. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1127. }
  1128. if (count) {
  1129. sds_ring->consumer = consumer;
  1130. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1131. }
  1132. return count;
  1133. }
  1134. /* Process Command status ring */
  1135. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1136. {
  1137. u32 sw_consumer, hw_consumer;
  1138. int count = 0, i;
  1139. struct netxen_cmd_buffer *buffer;
  1140. struct pci_dev *pdev = adapter->pdev;
  1141. struct net_device *netdev = adapter->netdev;
  1142. struct netxen_skb_frag *frag;
  1143. int done = 0;
  1144. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1145. if (!spin_trylock(&adapter->tx_clean_lock))
  1146. return 1;
  1147. sw_consumer = tx_ring->sw_consumer;
  1148. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1149. while (sw_consumer != hw_consumer) {
  1150. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1151. if (buffer->skb) {
  1152. frag = &buffer->frag_array[0];
  1153. pci_unmap_single(pdev, frag->dma, frag->length,
  1154. PCI_DMA_TODEVICE);
  1155. frag->dma = 0ULL;
  1156. for (i = 1; i < buffer->frag_count; i++) {
  1157. frag++; /* Get the next frag */
  1158. pci_unmap_page(pdev, frag->dma, frag->length,
  1159. PCI_DMA_TODEVICE);
  1160. frag->dma = 0ULL;
  1161. }
  1162. adapter->stats.xmitfinished++;
  1163. dev_kfree_skb_any(buffer->skb);
  1164. buffer->skb = NULL;
  1165. }
  1166. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1167. if (++count >= MAX_STATUS_HANDLE)
  1168. break;
  1169. }
  1170. if (count && netif_running(netdev)) {
  1171. tx_ring->sw_consumer = sw_consumer;
  1172. smp_mb();
  1173. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1174. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1175. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1176. netif_wake_queue(netdev);
  1177. adapter->tx_timeo_cnt = 0;
  1178. }
  1179. __netif_tx_unlock(tx_ring->txq);
  1180. }
  1181. }
  1182. /*
  1183. * If everything is freed up to consumer then check if the ring is full
  1184. * If the ring is full then check if more needs to be freed and
  1185. * schedule the call back again.
  1186. *
  1187. * This happens when there are 2 CPUs. One could be freeing and the
  1188. * other filling it. If the ring is full when we get out of here and
  1189. * the card has already interrupted the host then the host can miss the
  1190. * interrupt.
  1191. *
  1192. * There is still a possible race condition and the host could miss an
  1193. * interrupt. The card has to take care of this.
  1194. */
  1195. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1196. done = (sw_consumer == hw_consumer);
  1197. spin_unlock(&adapter->tx_clean_lock);
  1198. return (done);
  1199. }
  1200. void
  1201. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1202. struct nx_host_rds_ring *rds_ring)
  1203. {
  1204. struct rcv_desc *pdesc;
  1205. struct netxen_rx_buffer *buffer;
  1206. int producer, count = 0;
  1207. netxen_ctx_msg msg = 0;
  1208. struct list_head *head;
  1209. producer = rds_ring->producer;
  1210. spin_lock(&rds_ring->lock);
  1211. head = &rds_ring->free_list;
  1212. while (!list_empty(head)) {
  1213. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1214. if (!buffer->skb) {
  1215. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1216. break;
  1217. }
  1218. count++;
  1219. list_del(&buffer->list);
  1220. /* make a rcv descriptor */
  1221. pdesc = &rds_ring->desc_head[producer];
  1222. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1223. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1224. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1225. producer = get_next_index(producer, rds_ring->num_desc);
  1226. }
  1227. spin_unlock(&rds_ring->lock);
  1228. if (count) {
  1229. rds_ring->producer = producer;
  1230. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1231. (producer-1) & (rds_ring->num_desc-1));
  1232. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1233. /*
  1234. * Write a doorbell msg to tell phanmon of change in
  1235. * receive ring producer
  1236. * Only for firmware version < 4.0.0
  1237. */
  1238. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1239. netxen_set_msg_privid(msg);
  1240. netxen_set_msg_count(msg,
  1241. ((producer - 1) &
  1242. (rds_ring->num_desc - 1)));
  1243. netxen_set_msg_ctxid(msg, adapter->portnum);
  1244. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1245. read_lock(&adapter->adapter_lock);
  1246. writel(msg, DB_NORMALIZE(adapter,
  1247. NETXEN_RCV_PRODUCER_OFFSET));
  1248. read_unlock(&adapter->adapter_lock);
  1249. }
  1250. }
  1251. }
  1252. static void
  1253. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1254. struct nx_host_rds_ring *rds_ring)
  1255. {
  1256. struct rcv_desc *pdesc;
  1257. struct netxen_rx_buffer *buffer;
  1258. int producer, count = 0;
  1259. struct list_head *head;
  1260. producer = rds_ring->producer;
  1261. if (!spin_trylock(&rds_ring->lock))
  1262. return;
  1263. head = &rds_ring->free_list;
  1264. while (!list_empty(head)) {
  1265. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1266. if (!buffer->skb) {
  1267. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1268. break;
  1269. }
  1270. count++;
  1271. list_del(&buffer->list);
  1272. /* make a rcv descriptor */
  1273. pdesc = &rds_ring->desc_head[producer];
  1274. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1275. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1276. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1277. producer = get_next_index(producer, rds_ring->num_desc);
  1278. }
  1279. if (count) {
  1280. rds_ring->producer = producer;
  1281. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1282. (producer - 1) & (rds_ring->num_desc - 1));
  1283. }
  1284. spin_unlock(&rds_ring->lock);
  1285. }
  1286. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1287. {
  1288. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1289. return;
  1290. }