via-ircc.c 42 KB

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  1. /********************************************************************
  2. Filename: via-ircc.c
  3. Version: 1.0
  4. Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
  5. Author: VIA Technologies,inc
  6. Date : 08/06/2003
  7. Copyright (c) 1998-2003 VIA Technologies, Inc.
  8. This program is free software; you can redistribute it and/or modify it under
  9. the terms of the GNU General Public License as published by the Free Software
  10. Foundation; either version 2, or (at your option) any later version.
  11. This program is distributed in the hope that it will be useful, but WITHOUT
  12. ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14. See the GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License along with
  16. this program; if not, write to the Free Software Foundation, Inc.,
  17. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  19. F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  20. Comment :
  21. jul/09/2002 : only implement two kind of dongle currently.
  22. Oct/02/2002 : work on VT8231 and VT8233 .
  23. Aug/06/2003 : change driver format to pci driver .
  24. 2004-02-16: <sda@bdit.de>
  25. - Removed unneeded 'legacy' pci stuff.
  26. - Make sure SIR mode is set (hw_init()) before calling mode-dependant stuff.
  27. - On speed change from core, don't send SIR frame with new speed.
  28. Use current speed and change speeds later.
  29. - Make module-param dongle_id actually work.
  30. - New dongle_id 17 (0x11): TDFS4500. Single-ended SIR only.
  31. Tested with home-grown PCB on EPIA boards.
  32. - Code cleanup.
  33. ********************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/kernel.h>
  36. #include <linux/types.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/ioport.h>
  40. #include <linux/delay.h>
  41. #include <linux/slab.h>
  42. #include <linux/init.h>
  43. #include <linux/rtnetlink.h>
  44. #include <linux/pci.h>
  45. #include <linux/dma-mapping.h>
  46. #include <asm/io.h>
  47. #include <asm/dma.h>
  48. #include <asm/byteorder.h>
  49. #include <linux/pm.h>
  50. #include <net/irda/wrapper.h>
  51. #include <net/irda/irda.h>
  52. #include <net/irda/irda_device.h>
  53. #include "via-ircc.h"
  54. #define VIA_MODULE_NAME "via-ircc"
  55. #define CHIP_IO_EXTENT 0x40
  56. static char *driver_name = VIA_MODULE_NAME;
  57. /* Module parameters */
  58. static int qos_mtt_bits = 0x07; /* 1 ms or more */
  59. static int dongle_id = 0; /* default: probe */
  60. /* We can't guess the type of connected dongle, user *must* supply it. */
  61. module_param(dongle_id, int, 0);
  62. /* FIXME : we should not need this, because instances should be automatically
  63. * managed by the PCI layer. Especially that we seem to only be using the
  64. * first entry. Jean II */
  65. /* Max 4 instances for now */
  66. static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  67. /* Some prototypes */
  68. static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  69. static int via_ircc_close(struct via_ircc_cb *self);
  70. static int via_ircc_dma_receive(struct via_ircc_cb *self);
  71. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  72. int iobase);
  73. static netdev_tx_t via_ircc_hard_xmit_sir(struct sk_buff *skb,
  74. struct net_device *dev);
  75. static netdev_tx_t via_ircc_hard_xmit_fir(struct sk_buff *skb,
  76. struct net_device *dev);
  77. static void via_hw_init(struct via_ircc_cb *self);
  78. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  79. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id);
  80. static int via_ircc_is_receiving(struct via_ircc_cb *self);
  81. static int via_ircc_read_dongle_id(int iobase);
  82. static int via_ircc_net_open(struct net_device *dev);
  83. static int via_ircc_net_close(struct net_device *dev);
  84. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  85. int cmd);
  86. static void via_ircc_change_dongle_speed(int iobase, int speed,
  87. int dongle_id);
  88. static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
  89. static void hwreset(struct via_ircc_cb *self);
  90. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
  91. static int upload_rxdata(struct via_ircc_cb *self, int iobase);
  92. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
  93. static void __devexit via_remove_one (struct pci_dev *pdev);
  94. /* FIXME : Should use udelay() instead, even if we are x86 only - Jean II */
  95. static void iodelay(int udelay)
  96. {
  97. u8 data;
  98. int i;
  99. for (i = 0; i < udelay; i++) {
  100. data = inb(0x80);
  101. }
  102. }
  103. static struct pci_device_id via_pci_tbl[] = {
  104. { PCI_VENDOR_ID_VIA, 0x8231, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
  105. { PCI_VENDOR_ID_VIA, 0x3109, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
  106. { PCI_VENDOR_ID_VIA, 0x3074, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
  107. { PCI_VENDOR_ID_VIA, 0x3147, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
  108. { PCI_VENDOR_ID_VIA, 0x3177, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
  109. { 0, }
  110. };
  111. MODULE_DEVICE_TABLE(pci,via_pci_tbl);
  112. static struct pci_driver via_driver = {
  113. .name = VIA_MODULE_NAME,
  114. .id_table = via_pci_tbl,
  115. .probe = via_init_one,
  116. .remove = __devexit_p(via_remove_one),
  117. };
  118. /*
  119. * Function via_ircc_init ()
  120. *
  121. * Initialize chip. Just find out chip type and resource.
  122. */
  123. static int __init via_ircc_init(void)
  124. {
  125. int rc;
  126. IRDA_DEBUG(3, "%s()\n", __func__);
  127. rc = pci_register_driver(&via_driver);
  128. if (rc < 0) {
  129. IRDA_DEBUG(0, "%s(): error rc = %d, returning -ENODEV...\n",
  130. __func__, rc);
  131. return -ENODEV;
  132. }
  133. return 0;
  134. }
  135. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
  136. {
  137. int rc;
  138. u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
  139. u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
  140. chipio_t info;
  141. IRDA_DEBUG(2, "%s(): Device ID=(0X%X)\n", __func__, id->device);
  142. rc = pci_enable_device (pcidev);
  143. if (rc) {
  144. IRDA_DEBUG(0, "%s(): error rc = %d\n", __func__, rc);
  145. return -ENODEV;
  146. }
  147. // South Bridge exist
  148. if ( ReadLPCReg(0x20) != 0x3C )
  149. Chipset=0x3096;
  150. else
  151. Chipset=0x3076;
  152. if (Chipset==0x3076) {
  153. IRDA_DEBUG(2, "%s(): Chipset = 3076\n", __func__);
  154. WriteLPCReg(7,0x0c );
  155. temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
  156. if((temp&0x01)==1) { // BIOS close or no FIR
  157. WriteLPCReg(0x1d, 0x82 );
  158. WriteLPCReg(0x23,0x18);
  159. temp=ReadLPCReg(0xF0);
  160. if((temp&0x01)==0) {
  161. temp=(ReadLPCReg(0x74)&0x03); //DMA
  162. FirDRQ0=temp + 4;
  163. temp=(ReadLPCReg(0x74)&0x0C) >> 2;
  164. FirDRQ1=temp + 4;
  165. } else {
  166. temp=(ReadLPCReg(0x74)&0x0C) >> 2; //DMA
  167. FirDRQ0=temp + 4;
  168. FirDRQ1=FirDRQ0;
  169. }
  170. FirIRQ=(ReadLPCReg(0x70)&0x0f); //IRQ
  171. FirIOBase=ReadLPCReg(0x60 ) << 8; //IO Space :high byte
  172. FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
  173. FirIOBase=FirIOBase ;
  174. info.fir_base=FirIOBase;
  175. info.irq=FirIRQ;
  176. info.dma=FirDRQ1;
  177. info.dma2=FirDRQ0;
  178. pci_read_config_byte(pcidev,0x40,&bTmp);
  179. pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
  180. pci_read_config_byte(pcidev,0x42,&bTmp);
  181. pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
  182. pci_write_config_byte(pcidev,0x5a,0xc0);
  183. WriteLPCReg(0x28, 0x70 );
  184. if (via_ircc_open(0, &info,0x3076) == 0)
  185. rc=0;
  186. } else
  187. rc = -ENODEV; //IR not turn on
  188. } else { //Not VT1211
  189. IRDA_DEBUG(2, "%s(): Chipset = 3096\n", __func__);
  190. pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
  191. if((bTmp&0x01)==1) { // BIOS enable FIR
  192. //Enable Double DMA clock
  193. pci_read_config_byte(pcidev,0x42,&oldPCI_40);
  194. pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
  195. pci_read_config_byte(pcidev,0x40,&oldPCI_40);
  196. pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
  197. pci_read_config_byte(pcidev,0x44,&oldPCI_44);
  198. pci_write_config_byte(pcidev,0x44,0x4e);
  199. //---------- read configuration from Function0 of south bridge
  200. if((bTmp&0x02)==0) {
  201. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  202. FirDRQ0 = (bTmp1 & 0x30) >> 4;
  203. pci_read_config_byte(pcidev,0x44,&bTmp1);
  204. FirDRQ1 = (bTmp1 & 0xc0) >> 6;
  205. } else {
  206. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  207. FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
  208. FirDRQ1=0;
  209. }
  210. pci_read_config_byte(pcidev,0x47,&bTmp1); //IRQ
  211. FirIRQ = bTmp1 & 0x0f;
  212. pci_read_config_byte(pcidev,0x69,&bTmp);
  213. FirIOBase = bTmp << 8;//hight byte
  214. pci_read_config_byte(pcidev,0x68,&bTmp);
  215. FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
  216. //-------------------------
  217. info.fir_base=FirIOBase;
  218. info.irq=FirIRQ;
  219. info.dma=FirDRQ1;
  220. info.dma2=FirDRQ0;
  221. if (via_ircc_open(0, &info,0x3096) == 0)
  222. rc=0;
  223. } else
  224. rc = -ENODEV; //IR not turn on !!!!!
  225. }//Not VT1211
  226. IRDA_DEBUG(2, "%s(): End - rc = %d\n", __func__, rc);
  227. return rc;
  228. }
  229. /*
  230. * Function via_ircc_clean ()
  231. *
  232. * Close all configured chips
  233. *
  234. */
  235. static void via_ircc_clean(void)
  236. {
  237. int i;
  238. IRDA_DEBUG(3, "%s()\n", __func__);
  239. for (i=0; i < ARRAY_SIZE(dev_self); i++) {
  240. if (dev_self[i])
  241. via_ircc_close(dev_self[i]);
  242. }
  243. }
  244. static void __devexit via_remove_one (struct pci_dev *pdev)
  245. {
  246. IRDA_DEBUG(3, "%s()\n", __func__);
  247. /* FIXME : This is ugly. We should use pci_get_drvdata(pdev);
  248. * to get our driver instance and call directly via_ircc_close().
  249. * See vlsi_ir for details...
  250. * Jean II */
  251. via_ircc_clean();
  252. /* FIXME : This should be in via_ircc_close(), because here we may
  253. * theoritically disable still configured devices :-( - Jean II */
  254. pci_disable_device(pdev);
  255. }
  256. static void __exit via_ircc_cleanup(void)
  257. {
  258. IRDA_DEBUG(3, "%s()\n", __func__);
  259. /* FIXME : This should be redundant, as pci_unregister_driver()
  260. * should call via_remove_one() on each device.
  261. * Jean II */
  262. via_ircc_clean();
  263. /* Cleanup all instances of the driver */
  264. pci_unregister_driver (&via_driver);
  265. }
  266. static const struct net_device_ops via_ircc_sir_ops = {
  267. .ndo_start_xmit = via_ircc_hard_xmit_sir,
  268. .ndo_open = via_ircc_net_open,
  269. .ndo_stop = via_ircc_net_close,
  270. .ndo_do_ioctl = via_ircc_net_ioctl,
  271. };
  272. static const struct net_device_ops via_ircc_fir_ops = {
  273. .ndo_start_xmit = via_ircc_hard_xmit_fir,
  274. .ndo_open = via_ircc_net_open,
  275. .ndo_stop = via_ircc_net_close,
  276. .ndo_do_ioctl = via_ircc_net_ioctl,
  277. };
  278. /*
  279. * Function via_ircc_open (iobase, irq)
  280. *
  281. * Open driver instance
  282. *
  283. */
  284. static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
  285. {
  286. struct net_device *dev;
  287. struct via_ircc_cb *self;
  288. int err;
  289. IRDA_DEBUG(3, "%s()\n", __func__);
  290. if (i >= ARRAY_SIZE(dev_self))
  291. return -ENOMEM;
  292. /* Allocate new instance of the driver */
  293. dev = alloc_irdadev(sizeof(struct via_ircc_cb));
  294. if (dev == NULL)
  295. return -ENOMEM;
  296. self = netdev_priv(dev);
  297. self->netdev = dev;
  298. spin_lock_init(&self->lock);
  299. /* FIXME : We should store our driver instance in the PCI layer,
  300. * using pci_set_drvdata(), not in this array.
  301. * See vlsi_ir for details... - Jean II */
  302. /* FIXME : 'i' is always 0 (see via_init_one()) :-( - Jean II */
  303. /* Need to store self somewhere */
  304. dev_self[i] = self;
  305. self->index = i;
  306. /* Initialize Resource */
  307. self->io.cfg_base = info->cfg_base;
  308. self->io.fir_base = info->fir_base;
  309. self->io.irq = info->irq;
  310. self->io.fir_ext = CHIP_IO_EXTENT;
  311. self->io.dma = info->dma;
  312. self->io.dma2 = info->dma2;
  313. self->io.fifo_size = 32;
  314. self->chip_id = id;
  315. self->st_fifo.len = 0;
  316. self->RxDataReady = 0;
  317. /* Reserve the ioports that we need */
  318. if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
  319. IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
  320. __func__, self->io.fir_base);
  321. err = -ENODEV;
  322. goto err_out1;
  323. }
  324. /* Initialize QoS for this device */
  325. irda_init_max_qos_capabilies(&self->qos);
  326. /* Check if user has supplied the dongle id or not */
  327. if (!dongle_id)
  328. dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
  329. self->io.dongle_id = dongle_id;
  330. /* The only value we must override it the baudrate */
  331. /* Maximum speeds and capabilities are dongle-dependant. */
  332. switch( self->io.dongle_id ){
  333. case 0x0d:
  334. self->qos.baud_rate.bits =
  335. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
  336. IR_576000 | IR_1152000 | (IR_4000000 << 8);
  337. break;
  338. default:
  339. self->qos.baud_rate.bits =
  340. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
  341. break;
  342. }
  343. /* Following was used for testing:
  344. *
  345. * self->qos.baud_rate.bits = IR_9600;
  346. *
  347. * Is is no good, as it prohibits (error-prone) speed-changes.
  348. */
  349. self->qos.min_turn_time.bits = qos_mtt_bits;
  350. irda_qos_bits_to_value(&self->qos);
  351. /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
  352. self->rx_buff.truesize = 14384 + 2048;
  353. self->tx_buff.truesize = 14384 + 2048;
  354. /* Allocate memory if needed */
  355. self->rx_buff.head =
  356. dma_alloc_coherent(NULL, self->rx_buff.truesize,
  357. &self->rx_buff_dma, GFP_KERNEL);
  358. if (self->rx_buff.head == NULL) {
  359. err = -ENOMEM;
  360. goto err_out2;
  361. }
  362. memset(self->rx_buff.head, 0, self->rx_buff.truesize);
  363. self->tx_buff.head =
  364. dma_alloc_coherent(NULL, self->tx_buff.truesize,
  365. &self->tx_buff_dma, GFP_KERNEL);
  366. if (self->tx_buff.head == NULL) {
  367. err = -ENOMEM;
  368. goto err_out3;
  369. }
  370. memset(self->tx_buff.head, 0, self->tx_buff.truesize);
  371. self->rx_buff.in_frame = FALSE;
  372. self->rx_buff.state = OUTSIDE_FRAME;
  373. self->tx_buff.data = self->tx_buff.head;
  374. self->rx_buff.data = self->rx_buff.head;
  375. /* Reset Tx queue info */
  376. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  377. self->tx_fifo.tail = self->tx_buff.head;
  378. /* Override the network functions we need to use */
  379. dev->netdev_ops = &via_ircc_sir_ops;
  380. err = register_netdev(dev);
  381. if (err)
  382. goto err_out4;
  383. IRDA_MESSAGE("IrDA: Registered device %s (via-ircc)\n", dev->name);
  384. /* Initialise the hardware..
  385. */
  386. self->io.speed = 9600;
  387. via_hw_init(self);
  388. return 0;
  389. err_out4:
  390. dma_free_coherent(NULL, self->tx_buff.truesize,
  391. self->tx_buff.head, self->tx_buff_dma);
  392. err_out3:
  393. dma_free_coherent(NULL, self->rx_buff.truesize,
  394. self->rx_buff.head, self->rx_buff_dma);
  395. err_out2:
  396. release_region(self->io.fir_base, self->io.fir_ext);
  397. err_out1:
  398. free_netdev(dev);
  399. dev_self[i] = NULL;
  400. return err;
  401. }
  402. /*
  403. * Function via_ircc_close (self)
  404. *
  405. * Close driver instance
  406. *
  407. */
  408. static int via_ircc_close(struct via_ircc_cb *self)
  409. {
  410. int iobase;
  411. IRDA_DEBUG(3, "%s()\n", __func__);
  412. IRDA_ASSERT(self != NULL, return -1;);
  413. iobase = self->io.fir_base;
  414. ResetChip(iobase, 5); //hardware reset.
  415. /* Remove netdevice */
  416. unregister_netdev(self->netdev);
  417. /* Release the PORT that this driver is using */
  418. IRDA_DEBUG(2, "%s(), Releasing Region %03x\n",
  419. __func__, self->io.fir_base);
  420. release_region(self->io.fir_base, self->io.fir_ext);
  421. if (self->tx_buff.head)
  422. dma_free_coherent(NULL, self->tx_buff.truesize,
  423. self->tx_buff.head, self->tx_buff_dma);
  424. if (self->rx_buff.head)
  425. dma_free_coherent(NULL, self->rx_buff.truesize,
  426. self->rx_buff.head, self->rx_buff_dma);
  427. dev_self[self->index] = NULL;
  428. free_netdev(self->netdev);
  429. return 0;
  430. }
  431. /*
  432. * Function via_hw_init(self)
  433. *
  434. * Returns non-negative on success.
  435. *
  436. * Formerly via_ircc_setup
  437. */
  438. static void via_hw_init(struct via_ircc_cb *self)
  439. {
  440. int iobase = self->io.fir_base;
  441. IRDA_DEBUG(3, "%s()\n", __func__);
  442. SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
  443. // FIFO Init
  444. EnRXFIFOReadyInt(iobase, OFF);
  445. EnRXFIFOHalfLevelInt(iobase, OFF);
  446. EnTXFIFOHalfLevelInt(iobase, OFF);
  447. EnTXFIFOUnderrunEOMInt(iobase, ON);
  448. EnTXFIFOReadyInt(iobase, OFF);
  449. InvertTX(iobase, OFF);
  450. InvertRX(iobase, OFF);
  451. if (ReadLPCReg(0x20) == 0x3c)
  452. WriteLPCReg(0xF0, 0); // for VT1211
  453. /* Int Init */
  454. EnRXSpecInt(iobase, ON);
  455. /* The following is basically hwreset */
  456. /* If this is the case, why not just call hwreset() ? Jean II */
  457. ResetChip(iobase, 5);
  458. EnableDMA(iobase, OFF);
  459. EnableTX(iobase, OFF);
  460. EnableRX(iobase, OFF);
  461. EnRXDMA(iobase, OFF);
  462. EnTXDMA(iobase, OFF);
  463. RXStart(iobase, OFF);
  464. TXStart(iobase, OFF);
  465. InitCard(iobase);
  466. CommonInit(iobase);
  467. SIRFilter(iobase, ON);
  468. SetSIR(iobase, ON);
  469. CRC16(iobase, ON);
  470. EnTXCRC(iobase, 0);
  471. WriteReg(iobase, I_ST_CT_0, 0x00);
  472. SetBaudRate(iobase, 9600);
  473. SetPulseWidth(iobase, 12);
  474. SetSendPreambleCount(iobase, 0);
  475. self->io.speed = 9600;
  476. self->st_fifo.len = 0;
  477. via_ircc_change_dongle_speed(iobase, self->io.speed,
  478. self->io.dongle_id);
  479. WriteReg(iobase, I_ST_CT_0, 0x80);
  480. }
  481. /*
  482. * Function via_ircc_read_dongle_id (void)
  483. *
  484. */
  485. static int via_ircc_read_dongle_id(int iobase)
  486. {
  487. int dongle_id = 9; /* Default to IBM */
  488. IRDA_ERROR("via-ircc: dongle probing not supported, please specify dongle_id module parameter.\n");
  489. return dongle_id;
  490. }
  491. /*
  492. * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
  493. * Change speed of the attach dongle
  494. * only implement two type of dongle currently.
  495. */
  496. static void via_ircc_change_dongle_speed(int iobase, int speed,
  497. int dongle_id)
  498. {
  499. u8 mode = 0;
  500. /* speed is unused, as we use IsSIROn()/IsMIROn() */
  501. speed = speed;
  502. IRDA_DEBUG(1, "%s(): change_dongle_speed to %d for 0x%x, %d\n",
  503. __func__, speed, iobase, dongle_id);
  504. switch (dongle_id) {
  505. /* Note: The dongle_id's listed here are derived from
  506. * nsc-ircc.c */
  507. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  508. UseOneRX(iobase, ON); // use one RX pin RX1,RX2
  509. InvertTX(iobase, OFF);
  510. InvertRX(iobase, OFF);
  511. EnRX2(iobase, ON); //sir to rx2
  512. EnGPIOtoRX2(iobase, OFF);
  513. if (IsSIROn(iobase)) { //sir
  514. // Mode select Off
  515. SlowIRRXLowActive(iobase, ON);
  516. udelay(1000);
  517. SlowIRRXLowActive(iobase, OFF);
  518. } else {
  519. if (IsMIROn(iobase)) { //mir
  520. // Mode select On
  521. SlowIRRXLowActive(iobase, OFF);
  522. udelay(20);
  523. } else { // fir
  524. if (IsFIROn(iobase)) { //fir
  525. // Mode select On
  526. SlowIRRXLowActive(iobase, OFF);
  527. udelay(20);
  528. }
  529. }
  530. }
  531. break;
  532. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  533. UseOneRX(iobase, ON); //use ONE RX....RX1
  534. InvertTX(iobase, OFF);
  535. InvertRX(iobase, OFF); // invert RX pin
  536. EnRX2(iobase, ON);
  537. EnGPIOtoRX2(iobase, OFF);
  538. if (IsSIROn(iobase)) { //sir
  539. // Mode select On
  540. SlowIRRXLowActive(iobase, ON);
  541. udelay(20);
  542. // Mode select Off
  543. SlowIRRXLowActive(iobase, OFF);
  544. }
  545. if (IsMIROn(iobase)) { //mir
  546. // Mode select On
  547. SlowIRRXLowActive(iobase, OFF);
  548. udelay(20);
  549. // Mode select Off
  550. SlowIRRXLowActive(iobase, ON);
  551. } else { // fir
  552. if (IsFIROn(iobase)) { //fir
  553. // Mode select On
  554. SlowIRRXLowActive(iobase, OFF);
  555. // TX On
  556. WriteTX(iobase, ON);
  557. udelay(20);
  558. // Mode select OFF
  559. SlowIRRXLowActive(iobase, ON);
  560. udelay(20);
  561. // TX Off
  562. WriteTX(iobase, OFF);
  563. }
  564. }
  565. break;
  566. case 0x0d:
  567. UseOneRX(iobase, OFF); // use two RX pin RX1,RX2
  568. InvertTX(iobase, OFF);
  569. InvertRX(iobase, OFF);
  570. SlowIRRXLowActive(iobase, OFF);
  571. if (IsSIROn(iobase)) { //sir
  572. EnGPIOtoRX2(iobase, OFF);
  573. WriteGIO(iobase, OFF);
  574. EnRX2(iobase, OFF); //sir to rx2
  575. } else { // fir mir
  576. EnGPIOtoRX2(iobase, OFF);
  577. WriteGIO(iobase, OFF);
  578. EnRX2(iobase, OFF); //fir to rx
  579. }
  580. break;
  581. case 0x11: /* Temic TFDS4500 */
  582. IRDA_DEBUG(2, "%s: Temic TFDS4500: One RX pin, TX normal, RX inverted.\n", __func__);
  583. UseOneRX(iobase, ON); //use ONE RX....RX1
  584. InvertTX(iobase, OFF);
  585. InvertRX(iobase, ON); // invert RX pin
  586. EnRX2(iobase, ON); //sir to rx2
  587. EnGPIOtoRX2(iobase, OFF);
  588. if( IsSIROn(iobase) ){ //sir
  589. // Mode select On
  590. SlowIRRXLowActive(iobase, ON);
  591. udelay(20);
  592. // Mode select Off
  593. SlowIRRXLowActive(iobase, OFF);
  594. } else{
  595. IRDA_DEBUG(0, "%s: Warning: TFDS4500 not running in SIR mode !\n", __func__);
  596. }
  597. break;
  598. case 0x0ff: /* Vishay */
  599. if (IsSIROn(iobase))
  600. mode = 0;
  601. else if (IsMIROn(iobase))
  602. mode = 1;
  603. else if (IsFIROn(iobase))
  604. mode = 2;
  605. else if (IsVFIROn(iobase))
  606. mode = 5; //VFIR-16
  607. SI_SetMode(iobase, mode);
  608. break;
  609. default:
  610. IRDA_ERROR("%s: Error: dongle_id %d unsupported !\n",
  611. __func__, dongle_id);
  612. }
  613. }
  614. /*
  615. * Function via_ircc_change_speed (self, baud)
  616. *
  617. * Change the speed of the device
  618. *
  619. */
  620. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
  621. {
  622. struct net_device *dev = self->netdev;
  623. u16 iobase;
  624. u8 value = 0, bTmp;
  625. iobase = self->io.fir_base;
  626. /* Update accounting for new speed */
  627. self->io.speed = speed;
  628. IRDA_DEBUG(1, "%s: change_speed to %d bps.\n", __func__, speed);
  629. WriteReg(iobase, I_ST_CT_0, 0x0);
  630. /* Controller mode sellection */
  631. switch (speed) {
  632. case 2400:
  633. case 9600:
  634. case 19200:
  635. case 38400:
  636. case 57600:
  637. case 115200:
  638. value = (115200/speed)-1;
  639. SetSIR(iobase, ON);
  640. CRC16(iobase, ON);
  641. break;
  642. case 576000:
  643. /* FIXME: this can't be right, as it's the same as 115200,
  644. * and 576000 is MIR, not SIR. */
  645. value = 0;
  646. SetSIR(iobase, ON);
  647. CRC16(iobase, ON);
  648. break;
  649. case 1152000:
  650. value = 0;
  651. SetMIR(iobase, ON);
  652. /* FIXME: CRC ??? */
  653. break;
  654. case 4000000:
  655. value = 0;
  656. SetFIR(iobase, ON);
  657. SetPulseWidth(iobase, 0);
  658. SetSendPreambleCount(iobase, 14);
  659. CRC16(iobase, OFF);
  660. EnTXCRC(iobase, ON);
  661. break;
  662. case 16000000:
  663. value = 0;
  664. SetVFIR(iobase, ON);
  665. /* FIXME: CRC ??? */
  666. break;
  667. default:
  668. value = 0;
  669. break;
  670. }
  671. /* Set baudrate to 0x19[2..7] */
  672. bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
  673. bTmp |= value << 2;
  674. WriteReg(iobase, I_CF_H_1, bTmp);
  675. /* Some dongles may need to be informed about speed changes. */
  676. via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
  677. /* Set FIFO size to 64 */
  678. SetFIFO(iobase, 64);
  679. /* Enable IR */
  680. WriteReg(iobase, I_ST_CT_0, 0x80);
  681. // EnTXFIFOHalfLevelInt(iobase,ON);
  682. /* Enable some interrupts so we can receive frames */
  683. //EnAllInt(iobase,ON);
  684. if (IsSIROn(iobase)) {
  685. SIRFilter(iobase, ON);
  686. SIRRecvAny(iobase, ON);
  687. } else {
  688. SIRFilter(iobase, OFF);
  689. SIRRecvAny(iobase, OFF);
  690. }
  691. if (speed > 115200) {
  692. /* Install FIR xmit handler */
  693. dev->netdev_ops = &via_ircc_fir_ops;
  694. via_ircc_dma_receive(self);
  695. } else {
  696. /* Install SIR xmit handler */
  697. dev->netdev_ops = &via_ircc_sir_ops;
  698. }
  699. netif_wake_queue(dev);
  700. }
  701. /*
  702. * Function via_ircc_hard_xmit (skb, dev)
  703. *
  704. * Transmit the frame!
  705. *
  706. */
  707. static netdev_tx_t via_ircc_hard_xmit_sir(struct sk_buff *skb,
  708. struct net_device *dev)
  709. {
  710. struct via_ircc_cb *self;
  711. unsigned long flags;
  712. u16 iobase;
  713. __u32 speed;
  714. self = netdev_priv(dev);
  715. IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
  716. iobase = self->io.fir_base;
  717. netif_stop_queue(dev);
  718. /* Check if we need to change the speed */
  719. speed = irda_get_next_speed(skb);
  720. if ((speed != self->io.speed) && (speed != -1)) {
  721. /* Check for empty frame */
  722. if (!skb->len) {
  723. via_ircc_change_speed(self, speed);
  724. dev->trans_start = jiffies;
  725. dev_kfree_skb(skb);
  726. return NETDEV_TX_OK;
  727. } else
  728. self->new_speed = speed;
  729. }
  730. InitCard(iobase);
  731. CommonInit(iobase);
  732. SIRFilter(iobase, ON);
  733. SetSIR(iobase, ON);
  734. CRC16(iobase, ON);
  735. EnTXCRC(iobase, 0);
  736. WriteReg(iobase, I_ST_CT_0, 0x00);
  737. spin_lock_irqsave(&self->lock, flags);
  738. self->tx_buff.data = self->tx_buff.head;
  739. self->tx_buff.len =
  740. async_wrap_skb(skb, self->tx_buff.data,
  741. self->tx_buff.truesize);
  742. dev->stats.tx_bytes += self->tx_buff.len;
  743. /* Send this frame with old speed */
  744. SetBaudRate(iobase, self->io.speed);
  745. SetPulseWidth(iobase, 12);
  746. SetSendPreambleCount(iobase, 0);
  747. WriteReg(iobase, I_ST_CT_0, 0x80);
  748. EnableTX(iobase, ON);
  749. EnableRX(iobase, OFF);
  750. ResetChip(iobase, 0);
  751. ResetChip(iobase, 1);
  752. ResetChip(iobase, 2);
  753. ResetChip(iobase, 3);
  754. ResetChip(iobase, 4);
  755. EnAllInt(iobase, ON);
  756. EnTXDMA(iobase, ON);
  757. EnRXDMA(iobase, OFF);
  758. irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
  759. DMA_TX_MODE);
  760. SetSendByte(iobase, self->tx_buff.len);
  761. RXStart(iobase, OFF);
  762. TXStart(iobase, ON);
  763. dev->trans_start = jiffies;
  764. spin_unlock_irqrestore(&self->lock, flags);
  765. dev_kfree_skb(skb);
  766. return NETDEV_TX_OK;
  767. }
  768. static netdev_tx_t via_ircc_hard_xmit_fir(struct sk_buff *skb,
  769. struct net_device *dev)
  770. {
  771. struct via_ircc_cb *self;
  772. u16 iobase;
  773. __u32 speed;
  774. unsigned long flags;
  775. self = netdev_priv(dev);
  776. iobase = self->io.fir_base;
  777. if (self->st_fifo.len)
  778. return NETDEV_TX_OK;
  779. if (self->chip_id == 0x3076)
  780. iodelay(1500);
  781. else
  782. udelay(1500);
  783. netif_stop_queue(dev);
  784. speed = irda_get_next_speed(skb);
  785. if ((speed != self->io.speed) && (speed != -1)) {
  786. if (!skb->len) {
  787. via_ircc_change_speed(self, speed);
  788. dev->trans_start = jiffies;
  789. dev_kfree_skb(skb);
  790. return NETDEV_TX_OK;
  791. } else
  792. self->new_speed = speed;
  793. }
  794. spin_lock_irqsave(&self->lock, flags);
  795. self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
  796. self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
  797. self->tx_fifo.tail += skb->len;
  798. dev->stats.tx_bytes += skb->len;
  799. skb_copy_from_linear_data(skb,
  800. self->tx_fifo.queue[self->tx_fifo.free].start, skb->len);
  801. self->tx_fifo.len++;
  802. self->tx_fifo.free++;
  803. //F01 if (self->tx_fifo.len == 1) {
  804. via_ircc_dma_xmit(self, iobase);
  805. //F01 }
  806. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
  807. dev->trans_start = jiffies;
  808. dev_kfree_skb(skb);
  809. spin_unlock_irqrestore(&self->lock, flags);
  810. return NETDEV_TX_OK;
  811. }
  812. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
  813. {
  814. EnTXDMA(iobase, OFF);
  815. self->io.direction = IO_XMIT;
  816. EnPhys(iobase, ON);
  817. EnableTX(iobase, ON);
  818. EnableRX(iobase, OFF);
  819. ResetChip(iobase, 0);
  820. ResetChip(iobase, 1);
  821. ResetChip(iobase, 2);
  822. ResetChip(iobase, 3);
  823. ResetChip(iobase, 4);
  824. EnAllInt(iobase, ON);
  825. EnTXDMA(iobase, ON);
  826. EnRXDMA(iobase, OFF);
  827. irda_setup_dma(self->io.dma,
  828. ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
  829. self->tx_buff.head) + self->tx_buff_dma,
  830. self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
  831. IRDA_DEBUG(1, "%s: tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
  832. __func__, self->tx_fifo.ptr,
  833. self->tx_fifo.queue[self->tx_fifo.ptr].len,
  834. self->tx_fifo.len);
  835. SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
  836. RXStart(iobase, OFF);
  837. TXStart(iobase, ON);
  838. return 0;
  839. }
  840. /*
  841. * Function via_ircc_dma_xmit_complete (self)
  842. *
  843. * The transfer of a frame in finished. This function will only be called
  844. * by the interrupt handler
  845. *
  846. */
  847. static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
  848. {
  849. int iobase;
  850. int ret = TRUE;
  851. u8 Tx_status;
  852. IRDA_DEBUG(3, "%s()\n", __func__);
  853. iobase = self->io.fir_base;
  854. /* Disable DMA */
  855. // DisableDmaChannel(self->io.dma);
  856. /* Check for underrrun! */
  857. /* Clear bit, by writing 1 into it */
  858. Tx_status = GetTXStatus(iobase);
  859. if (Tx_status & 0x08) {
  860. self->netdev->stats.tx_errors++;
  861. self->netdev->stats.tx_fifo_errors++;
  862. hwreset(self);
  863. // how to clear underrrun ?
  864. } else {
  865. self->netdev->stats.tx_packets++;
  866. ResetChip(iobase, 3);
  867. ResetChip(iobase, 4);
  868. }
  869. /* Check if we need to change the speed */
  870. if (self->new_speed) {
  871. via_ircc_change_speed(self, self->new_speed);
  872. self->new_speed = 0;
  873. }
  874. /* Finished with this frame, so prepare for next */
  875. if (IsFIROn(iobase)) {
  876. if (self->tx_fifo.len) {
  877. self->tx_fifo.len--;
  878. self->tx_fifo.ptr++;
  879. }
  880. }
  881. IRDA_DEBUG(1,
  882. "%s: tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
  883. __func__,
  884. self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free);
  885. /* F01_S
  886. // Any frames to be sent back-to-back?
  887. if (self->tx_fifo.len) {
  888. // Not finished yet!
  889. via_ircc_dma_xmit(self, iobase);
  890. ret = FALSE;
  891. } else {
  892. F01_E*/
  893. // Reset Tx FIFO info
  894. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  895. self->tx_fifo.tail = self->tx_buff.head;
  896. //F01 }
  897. // Make sure we have room for more frames
  898. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
  899. // Not busy transmitting anymore
  900. // Tell the network layer, that we can accept more frames
  901. netif_wake_queue(self->netdev);
  902. //F01 }
  903. return ret;
  904. }
  905. /*
  906. * Function via_ircc_dma_receive (self)
  907. *
  908. * Set configuration for receive a frame.
  909. *
  910. */
  911. static int via_ircc_dma_receive(struct via_ircc_cb *self)
  912. {
  913. int iobase;
  914. iobase = self->io.fir_base;
  915. IRDA_DEBUG(3, "%s()\n", __func__);
  916. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  917. self->tx_fifo.tail = self->tx_buff.head;
  918. self->RxDataReady = 0;
  919. self->io.direction = IO_RECV;
  920. self->rx_buff.data = self->rx_buff.head;
  921. self->st_fifo.len = self->st_fifo.pending_bytes = 0;
  922. self->st_fifo.tail = self->st_fifo.head = 0;
  923. EnPhys(iobase, ON);
  924. EnableTX(iobase, OFF);
  925. EnableRX(iobase, ON);
  926. ResetChip(iobase, 0);
  927. ResetChip(iobase, 1);
  928. ResetChip(iobase, 2);
  929. ResetChip(iobase, 3);
  930. ResetChip(iobase, 4);
  931. EnAllInt(iobase, ON);
  932. EnTXDMA(iobase, OFF);
  933. EnRXDMA(iobase, ON);
  934. irda_setup_dma(self->io.dma2, self->rx_buff_dma,
  935. self->rx_buff.truesize, DMA_RX_MODE);
  936. TXStart(iobase, OFF);
  937. RXStart(iobase, ON);
  938. return 0;
  939. }
  940. /*
  941. * Function via_ircc_dma_receive_complete (self)
  942. *
  943. * Controller Finished with receiving frames,
  944. * and this routine is call by ISR
  945. *
  946. */
  947. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  948. int iobase)
  949. {
  950. struct st_fifo *st_fifo;
  951. struct sk_buff *skb;
  952. int len, i;
  953. u8 status = 0;
  954. iobase = self->io.fir_base;
  955. st_fifo = &self->st_fifo;
  956. if (self->io.speed < 4000000) { //Speed below FIR
  957. len = GetRecvByte(iobase, self);
  958. skb = dev_alloc_skb(len + 1);
  959. if (skb == NULL)
  960. return FALSE;
  961. // Make sure IP header gets aligned
  962. skb_reserve(skb, 1);
  963. skb_put(skb, len - 2);
  964. if (self->chip_id == 0x3076) {
  965. for (i = 0; i < len - 2; i++)
  966. skb->data[i] = self->rx_buff.data[i * 2];
  967. } else {
  968. if (self->chip_id == 0x3096) {
  969. for (i = 0; i < len - 2; i++)
  970. skb->data[i] =
  971. self->rx_buff.data[i];
  972. }
  973. }
  974. // Move to next frame
  975. self->rx_buff.data += len;
  976. self->netdev->stats.rx_bytes += len;
  977. self->netdev->stats.rx_packets++;
  978. skb->dev = self->netdev;
  979. skb_reset_mac_header(skb);
  980. skb->protocol = htons(ETH_P_IRDA);
  981. netif_rx(skb);
  982. return TRUE;
  983. }
  984. else { //FIR mode
  985. len = GetRecvByte(iobase, self);
  986. if (len == 0)
  987. return TRUE; //interrupt only, data maybe move by RxT
  988. if (((len - 4) < 2) || ((len - 4) > 2048)) {
  989. IRDA_DEBUG(1, "%s(): Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
  990. __func__, len, RxCurCount(iobase, self),
  991. self->RxLastCount);
  992. hwreset(self);
  993. return FALSE;
  994. }
  995. IRDA_DEBUG(2, "%s(): fifo.len=%x,len=%x,CurCount=%x..\n",
  996. __func__,
  997. st_fifo->len, len - 4, RxCurCount(iobase, self));
  998. st_fifo->entries[st_fifo->tail].status = status;
  999. st_fifo->entries[st_fifo->tail].len = len;
  1000. st_fifo->pending_bytes += len;
  1001. st_fifo->tail++;
  1002. st_fifo->len++;
  1003. if (st_fifo->tail > MAX_RX_WINDOW)
  1004. st_fifo->tail = 0;
  1005. self->RxDataReady = 0;
  1006. // It maybe have MAX_RX_WINDOW package receive by
  1007. // receive_complete before Timer IRQ
  1008. /* F01_S
  1009. if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
  1010. RXStart(iobase,ON);
  1011. SetTimer(iobase,4);
  1012. }
  1013. else {
  1014. F01_E */
  1015. EnableRX(iobase, OFF);
  1016. EnRXDMA(iobase, OFF);
  1017. RXStart(iobase, OFF);
  1018. //F01_S
  1019. // Put this entry back in fifo
  1020. if (st_fifo->head > MAX_RX_WINDOW)
  1021. st_fifo->head = 0;
  1022. status = st_fifo->entries[st_fifo->head].status;
  1023. len = st_fifo->entries[st_fifo->head].len;
  1024. st_fifo->head++;
  1025. st_fifo->len--;
  1026. skb = dev_alloc_skb(len + 1 - 4);
  1027. /*
  1028. * if frame size,data ptr,or skb ptr are wrong ,the get next
  1029. * entry.
  1030. */
  1031. if ((skb == NULL) || (skb->data == NULL)
  1032. || (self->rx_buff.data == NULL) || (len < 6)) {
  1033. self->netdev->stats.rx_dropped++;
  1034. return TRUE;
  1035. }
  1036. skb_reserve(skb, 1);
  1037. skb_put(skb, len - 4);
  1038. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4);
  1039. IRDA_DEBUG(2, "%s(): len=%x.rx_buff=%p\n", __func__,
  1040. len - 4, self->rx_buff.data);
  1041. // Move to next frame
  1042. self->rx_buff.data += len;
  1043. self->netdev->stats.rx_bytes += len;
  1044. self->netdev->stats.rx_packets++;
  1045. skb->dev = self->netdev;
  1046. skb_reset_mac_header(skb);
  1047. skb->protocol = htons(ETH_P_IRDA);
  1048. netif_rx(skb);
  1049. //F01_E
  1050. } //FIR
  1051. return TRUE;
  1052. }
  1053. /*
  1054. * if frame is received , but no INT ,then use this routine to upload frame.
  1055. */
  1056. static int upload_rxdata(struct via_ircc_cb *self, int iobase)
  1057. {
  1058. struct sk_buff *skb;
  1059. int len;
  1060. struct st_fifo *st_fifo;
  1061. st_fifo = &self->st_fifo;
  1062. len = GetRecvByte(iobase, self);
  1063. IRDA_DEBUG(2, "%s(): len=%x\n", __func__, len);
  1064. if ((len - 4) < 2) {
  1065. self->netdev->stats.rx_dropped++;
  1066. return FALSE;
  1067. }
  1068. skb = dev_alloc_skb(len + 1);
  1069. if (skb == NULL) {
  1070. self->netdev->stats.rx_dropped++;
  1071. return FALSE;
  1072. }
  1073. skb_reserve(skb, 1);
  1074. skb_put(skb, len - 4 + 1);
  1075. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4 + 1);
  1076. st_fifo->tail++;
  1077. st_fifo->len++;
  1078. if (st_fifo->tail > MAX_RX_WINDOW)
  1079. st_fifo->tail = 0;
  1080. // Move to next frame
  1081. self->rx_buff.data += len;
  1082. self->netdev->stats.rx_bytes += len;
  1083. self->netdev->stats.rx_packets++;
  1084. skb->dev = self->netdev;
  1085. skb_reset_mac_header(skb);
  1086. skb->protocol = htons(ETH_P_IRDA);
  1087. netif_rx(skb);
  1088. if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
  1089. RXStart(iobase, ON);
  1090. } else {
  1091. EnableRX(iobase, OFF);
  1092. EnRXDMA(iobase, OFF);
  1093. RXStart(iobase, OFF);
  1094. }
  1095. return TRUE;
  1096. }
  1097. /*
  1098. * Implement back to back receive , use this routine to upload data.
  1099. */
  1100. static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
  1101. {
  1102. struct st_fifo *st_fifo;
  1103. struct sk_buff *skb;
  1104. int len;
  1105. u8 status;
  1106. st_fifo = &self->st_fifo;
  1107. if (CkRxRecv(iobase, self)) {
  1108. // if still receiving ,then return ,don't upload frame
  1109. self->RetryCount = 0;
  1110. SetTimer(iobase, 20);
  1111. self->RxDataReady++;
  1112. return FALSE;
  1113. } else
  1114. self->RetryCount++;
  1115. if ((self->RetryCount >= 1) ||
  1116. ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
  1117. || (st_fifo->len >= (MAX_RX_WINDOW))) {
  1118. while (st_fifo->len > 0) { //upload frame
  1119. // Put this entry back in fifo
  1120. if (st_fifo->head > MAX_RX_WINDOW)
  1121. st_fifo->head = 0;
  1122. status = st_fifo->entries[st_fifo->head].status;
  1123. len = st_fifo->entries[st_fifo->head].len;
  1124. st_fifo->head++;
  1125. st_fifo->len--;
  1126. skb = dev_alloc_skb(len + 1 - 4);
  1127. /*
  1128. * if frame size, data ptr, or skb ptr are wrong,
  1129. * then get next entry.
  1130. */
  1131. if ((skb == NULL) || (skb->data == NULL)
  1132. || (self->rx_buff.data == NULL) || (len < 6)) {
  1133. self->netdev->stats.rx_dropped++;
  1134. continue;
  1135. }
  1136. skb_reserve(skb, 1);
  1137. skb_put(skb, len - 4);
  1138. skb_copy_to_linear_data(skb, self->rx_buff.data, len - 4);
  1139. IRDA_DEBUG(2, "%s(): len=%x.head=%x\n", __func__,
  1140. len - 4, st_fifo->head);
  1141. // Move to next frame
  1142. self->rx_buff.data += len;
  1143. self->netdev->stats.rx_bytes += len;
  1144. self->netdev->stats.rx_packets++;
  1145. skb->dev = self->netdev;
  1146. skb_reset_mac_header(skb);
  1147. skb->protocol = htons(ETH_P_IRDA);
  1148. netif_rx(skb);
  1149. } //while
  1150. self->RetryCount = 0;
  1151. IRDA_DEBUG(2,
  1152. "%s(): End of upload HostStatus=%x,RxStatus=%x\n",
  1153. __func__,
  1154. GetHostStatus(iobase), GetRXStatus(iobase));
  1155. /*
  1156. * if frame is receive complete at this routine ,then upload
  1157. * frame.
  1158. */
  1159. if ((GetRXStatus(iobase) & 0x10)
  1160. && (RxCurCount(iobase, self) != self->RxLastCount)) {
  1161. upload_rxdata(self, iobase);
  1162. if (irda_device_txqueue_empty(self->netdev))
  1163. via_ircc_dma_receive(self);
  1164. }
  1165. } // timer detect complete
  1166. else
  1167. SetTimer(iobase, 4);
  1168. return TRUE;
  1169. }
  1170. /*
  1171. * Function via_ircc_interrupt (irq, dev_id)
  1172. *
  1173. * An interrupt from the chip has arrived. Time to do some work
  1174. *
  1175. */
  1176. static irqreturn_t via_ircc_interrupt(int dummy, void *dev_id)
  1177. {
  1178. struct net_device *dev = dev_id;
  1179. struct via_ircc_cb *self = netdev_priv(dev);
  1180. int iobase;
  1181. u8 iHostIntType, iRxIntType, iTxIntType;
  1182. iobase = self->io.fir_base;
  1183. spin_lock(&self->lock);
  1184. iHostIntType = GetHostStatus(iobase);
  1185. IRDA_DEBUG(4, "%s(): iHostIntType %02x: %s %s %s %02x\n",
  1186. __func__, iHostIntType,
  1187. (iHostIntType & 0x40) ? "Timer" : "",
  1188. (iHostIntType & 0x20) ? "Tx" : "",
  1189. (iHostIntType & 0x10) ? "Rx" : "",
  1190. (iHostIntType & 0x0e) >> 1);
  1191. if ((iHostIntType & 0x40) != 0) { //Timer Event
  1192. self->EventFlag.TimeOut++;
  1193. ClearTimerInt(iobase, 1);
  1194. if (self->io.direction == IO_XMIT) {
  1195. via_ircc_dma_xmit(self, iobase);
  1196. }
  1197. if (self->io.direction == IO_RECV) {
  1198. /*
  1199. * frame ready hold too long, must reset.
  1200. */
  1201. if (self->RxDataReady > 30) {
  1202. hwreset(self);
  1203. if (irda_device_txqueue_empty(self->netdev)) {
  1204. via_ircc_dma_receive(self);
  1205. }
  1206. } else { // call this to upload frame.
  1207. RxTimerHandler(self, iobase);
  1208. }
  1209. } //RECV
  1210. } //Timer Event
  1211. if ((iHostIntType & 0x20) != 0) { //Tx Event
  1212. iTxIntType = GetTXStatus(iobase);
  1213. IRDA_DEBUG(4, "%s(): iTxIntType %02x: %s %s %s %s\n",
  1214. __func__, iTxIntType,
  1215. (iTxIntType & 0x08) ? "FIFO underr." : "",
  1216. (iTxIntType & 0x04) ? "EOM" : "",
  1217. (iTxIntType & 0x02) ? "FIFO ready" : "",
  1218. (iTxIntType & 0x01) ? "Early EOM" : "");
  1219. if (iTxIntType & 0x4) {
  1220. self->EventFlag.EOMessage++; // read and will auto clean
  1221. if (via_ircc_dma_xmit_complete(self)) {
  1222. if (irda_device_txqueue_empty
  1223. (self->netdev)) {
  1224. via_ircc_dma_receive(self);
  1225. }
  1226. } else {
  1227. self->EventFlag.Unknown++;
  1228. }
  1229. } //EOP
  1230. } //Tx Event
  1231. //----------------------------------------
  1232. if ((iHostIntType & 0x10) != 0) { //Rx Event
  1233. /* Check if DMA has finished */
  1234. iRxIntType = GetRXStatus(iobase);
  1235. IRDA_DEBUG(4, "%s(): iRxIntType %02x: %s %s %s %s %s %s %s\n",
  1236. __func__, iRxIntType,
  1237. (iRxIntType & 0x80) ? "PHY err." : "",
  1238. (iRxIntType & 0x40) ? "CRC err" : "",
  1239. (iRxIntType & 0x20) ? "FIFO overr." : "",
  1240. (iRxIntType & 0x10) ? "EOF" : "",
  1241. (iRxIntType & 0x08) ? "RxData" : "",
  1242. (iRxIntType & 0x02) ? "RxMaxLen" : "",
  1243. (iRxIntType & 0x01) ? "SIR bad" : "");
  1244. if (!iRxIntType)
  1245. IRDA_DEBUG(3, "%s(): RxIRQ =0\n", __func__);
  1246. if (iRxIntType & 0x10) {
  1247. if (via_ircc_dma_receive_complete(self, iobase)) {
  1248. //F01 if(!(IsFIROn(iobase))) via_ircc_dma_receive(self);
  1249. via_ircc_dma_receive(self);
  1250. }
  1251. } // No ERR
  1252. else { //ERR
  1253. IRDA_DEBUG(4, "%s(): RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
  1254. __func__, iRxIntType, iHostIntType,
  1255. RxCurCount(iobase, self),
  1256. self->RxLastCount);
  1257. if (iRxIntType & 0x20) { //FIFO OverRun ERR
  1258. ResetChip(iobase, 0);
  1259. ResetChip(iobase, 1);
  1260. } else { //PHY,CRC ERR
  1261. if (iRxIntType != 0x08)
  1262. hwreset(self); //F01
  1263. }
  1264. via_ircc_dma_receive(self);
  1265. } //ERR
  1266. } //Rx Event
  1267. spin_unlock(&self->lock);
  1268. return IRQ_RETVAL(iHostIntType);
  1269. }
  1270. static void hwreset(struct via_ircc_cb *self)
  1271. {
  1272. int iobase;
  1273. iobase = self->io.fir_base;
  1274. IRDA_DEBUG(3, "%s()\n", __func__);
  1275. ResetChip(iobase, 5);
  1276. EnableDMA(iobase, OFF);
  1277. EnableTX(iobase, OFF);
  1278. EnableRX(iobase, OFF);
  1279. EnRXDMA(iobase, OFF);
  1280. EnTXDMA(iobase, OFF);
  1281. RXStart(iobase, OFF);
  1282. TXStart(iobase, OFF);
  1283. InitCard(iobase);
  1284. CommonInit(iobase);
  1285. SIRFilter(iobase, ON);
  1286. SetSIR(iobase, ON);
  1287. CRC16(iobase, ON);
  1288. EnTXCRC(iobase, 0);
  1289. WriteReg(iobase, I_ST_CT_0, 0x00);
  1290. SetBaudRate(iobase, 9600);
  1291. SetPulseWidth(iobase, 12);
  1292. SetSendPreambleCount(iobase, 0);
  1293. WriteReg(iobase, I_ST_CT_0, 0x80);
  1294. /* Restore speed. */
  1295. via_ircc_change_speed(self, self->io.speed);
  1296. self->st_fifo.len = 0;
  1297. }
  1298. /*
  1299. * Function via_ircc_is_receiving (self)
  1300. *
  1301. * Return TRUE is we are currently receiving a frame
  1302. *
  1303. */
  1304. static int via_ircc_is_receiving(struct via_ircc_cb *self)
  1305. {
  1306. int status = FALSE;
  1307. int iobase;
  1308. IRDA_ASSERT(self != NULL, return FALSE;);
  1309. iobase = self->io.fir_base;
  1310. if (CkRxRecv(iobase, self))
  1311. status = TRUE;
  1312. IRDA_DEBUG(2, "%s(): status=%x....\n", __func__, status);
  1313. return status;
  1314. }
  1315. /*
  1316. * Function via_ircc_net_open (dev)
  1317. *
  1318. * Start the device
  1319. *
  1320. */
  1321. static int via_ircc_net_open(struct net_device *dev)
  1322. {
  1323. struct via_ircc_cb *self;
  1324. int iobase;
  1325. char hwname[32];
  1326. IRDA_DEBUG(3, "%s()\n", __func__);
  1327. IRDA_ASSERT(dev != NULL, return -1;);
  1328. self = netdev_priv(dev);
  1329. dev->stats.rx_packets = 0;
  1330. IRDA_ASSERT(self != NULL, return 0;);
  1331. iobase = self->io.fir_base;
  1332. if (request_irq(self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
  1333. IRDA_WARNING("%s, unable to allocate irq=%d\n", driver_name,
  1334. self->io.irq);
  1335. return -EAGAIN;
  1336. }
  1337. /*
  1338. * Always allocate the DMA channel after the IRQ, and clean up on
  1339. * failure.
  1340. */
  1341. if (request_dma(self->io.dma, dev->name)) {
  1342. IRDA_WARNING("%s, unable to allocate dma=%d\n", driver_name,
  1343. self->io.dma);
  1344. free_irq(self->io.irq, self);
  1345. return -EAGAIN;
  1346. }
  1347. if (self->io.dma2 != self->io.dma) {
  1348. if (request_dma(self->io.dma2, dev->name)) {
  1349. IRDA_WARNING("%s, unable to allocate dma2=%d\n",
  1350. driver_name, self->io.dma2);
  1351. free_irq(self->io.irq, self);
  1352. free_dma(self->io.dma);
  1353. return -EAGAIN;
  1354. }
  1355. }
  1356. /* turn on interrupts */
  1357. EnAllInt(iobase, ON);
  1358. EnInternalLoop(iobase, OFF);
  1359. EnExternalLoop(iobase, OFF);
  1360. /* */
  1361. via_ircc_dma_receive(self);
  1362. /* Ready to play! */
  1363. netif_start_queue(dev);
  1364. /*
  1365. * Open new IrLAP layer instance, now that everything should be
  1366. * initialized properly
  1367. */
  1368. sprintf(hwname, "VIA @ 0x%x", iobase);
  1369. self->irlap = irlap_open(dev, &self->qos, hwname);
  1370. self->RxLastCount = 0;
  1371. return 0;
  1372. }
  1373. /*
  1374. * Function via_ircc_net_close (dev)
  1375. *
  1376. * Stop the device
  1377. *
  1378. */
  1379. static int via_ircc_net_close(struct net_device *dev)
  1380. {
  1381. struct via_ircc_cb *self;
  1382. int iobase;
  1383. IRDA_DEBUG(3, "%s()\n", __func__);
  1384. IRDA_ASSERT(dev != NULL, return -1;);
  1385. self = netdev_priv(dev);
  1386. IRDA_ASSERT(self != NULL, return 0;);
  1387. /* Stop device */
  1388. netif_stop_queue(dev);
  1389. /* Stop and remove instance of IrLAP */
  1390. if (self->irlap)
  1391. irlap_close(self->irlap);
  1392. self->irlap = NULL;
  1393. iobase = self->io.fir_base;
  1394. EnTXDMA(iobase, OFF);
  1395. EnRXDMA(iobase, OFF);
  1396. DisableDmaChannel(self->io.dma);
  1397. /* Disable interrupts */
  1398. EnAllInt(iobase, OFF);
  1399. free_irq(self->io.irq, dev);
  1400. free_dma(self->io.dma);
  1401. if (self->io.dma2 != self->io.dma)
  1402. free_dma(self->io.dma2);
  1403. return 0;
  1404. }
  1405. /*
  1406. * Function via_ircc_net_ioctl (dev, rq, cmd)
  1407. *
  1408. * Process IOCTL commands for this device
  1409. *
  1410. */
  1411. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  1412. int cmd)
  1413. {
  1414. struct if_irda_req *irq = (struct if_irda_req *) rq;
  1415. struct via_ircc_cb *self;
  1416. unsigned long flags;
  1417. int ret = 0;
  1418. IRDA_ASSERT(dev != NULL, return -1;);
  1419. self = netdev_priv(dev);
  1420. IRDA_ASSERT(self != NULL, return -1;);
  1421. IRDA_DEBUG(1, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name,
  1422. cmd);
  1423. /* Disable interrupts & save flags */
  1424. spin_lock_irqsave(&self->lock, flags);
  1425. switch (cmd) {
  1426. case SIOCSBANDWIDTH: /* Set bandwidth */
  1427. if (!capable(CAP_NET_ADMIN)) {
  1428. ret = -EPERM;
  1429. goto out;
  1430. }
  1431. via_ircc_change_speed(self, irq->ifr_baudrate);
  1432. break;
  1433. case SIOCSMEDIABUSY: /* Set media busy */
  1434. if (!capable(CAP_NET_ADMIN)) {
  1435. ret = -EPERM;
  1436. goto out;
  1437. }
  1438. irda_device_set_media_busy(self->netdev, TRUE);
  1439. break;
  1440. case SIOCGRECEIVING: /* Check if we are receiving right now */
  1441. irq->ifr_receiving = via_ircc_is_receiving(self);
  1442. break;
  1443. default:
  1444. ret = -EOPNOTSUPP;
  1445. }
  1446. out:
  1447. spin_unlock_irqrestore(&self->lock, flags);
  1448. return ret;
  1449. }
  1450. MODULE_AUTHOR("VIA Technologies,inc");
  1451. MODULE_DESCRIPTION("VIA IrDA Device Driver");
  1452. MODULE_LICENSE("GPL");
  1453. module_init(via_ircc_init);
  1454. module_exit(via_ircc_cleanup);