yam.c 32 KB

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  1. /*****************************************************************************/
  2. /*
  3. * yam.c -- YAM radio modem driver.
  4. *
  5. * Copyright (C) 1998 Frederic Rible F1OAT (frible@teaser.fr)
  6. * Adapted from baycom.c driver written by Thomas Sailer (sailer@ife.ee.ethz.ch)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * Please note that the GPL allows you to use the driver, NOT the radio.
  23. * In order to use the radio, you need a license from the communications
  24. * authority of your country.
  25. *
  26. *
  27. * History:
  28. * 0.0 F1OAT 06.06.98 Begin of work with baycom.c source code V 0.3
  29. * 0.1 F1OAT 07.06.98 Add timer polling routine for channel arbitration
  30. * 0.2 F6FBB 08.06.98 Added delay after FPGA programming
  31. * 0.3 F6FBB 29.07.98 Delayed PTT implementation for dupmode=2
  32. * 0.4 F6FBB 30.07.98 Added TxTail, Slottime and Persistance
  33. * 0.5 F6FBB 01.08.98 Shared IRQs, /proc/net and network statistics
  34. * 0.6 F6FBB 25.08.98 Added 1200Bds format
  35. * 0.7 F6FBB 12.09.98 Added to the kernel configuration
  36. * 0.8 F6FBB 14.10.98 Fixed slottime/persistence timing bug
  37. * OK1ZIA 2.09.01 Fixed "kfree_skb on hard IRQ"
  38. * using dev_kfree_skb_any(). (important in 2.4 kernel)
  39. *
  40. */
  41. /*****************************************************************************/
  42. #include <linux/module.h>
  43. #include <linux/types.h>
  44. #include <linux/net.h>
  45. #include <linux/in.h>
  46. #include <linux/if.h>
  47. #include <linux/slab.h>
  48. #include <linux/errno.h>
  49. #include <linux/bitops.h>
  50. #include <linux/random.h>
  51. #include <asm/io.h>
  52. #include <asm/system.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/ioport.h>
  55. #include <linux/firmware.h>
  56. #include <linux/platform_device.h>
  57. #include <linux/netdevice.h>
  58. #include <linux/if_arp.h>
  59. #include <linux/etherdevice.h>
  60. #include <linux/skbuff.h>
  61. #include <net/ax25.h>
  62. #include <linux/kernel.h>
  63. #include <linux/proc_fs.h>
  64. #include <linux/seq_file.h>
  65. #include <net/net_namespace.h>
  66. #include <asm/uaccess.h>
  67. #include <linux/init.h>
  68. #include <linux/yam.h>
  69. /* --------------------------------------------------------------------- */
  70. static const char yam_drvname[] = "yam";
  71. static const char yam_drvinfo[] __initdata = KERN_INFO \
  72. "YAM driver version 0.8 by F1OAT/F6FBB\n";
  73. /* --------------------------------------------------------------------- */
  74. #define FIRMWARE_9600 "yam/9600.bin"
  75. #define FIRMWARE_1200 "yam/1200.bin"
  76. #define YAM_9600 1
  77. #define YAM_1200 2
  78. #define NR_PORTS 4
  79. #define YAM_MAGIC 0xF10A7654
  80. /* Transmitter states */
  81. #define TX_OFF 0
  82. #define TX_HEAD 1
  83. #define TX_DATA 2
  84. #define TX_CRC1 3
  85. #define TX_CRC2 4
  86. #define TX_TAIL 5
  87. #define YAM_MAX_FRAME 1024
  88. #define DEFAULT_BITRATE 9600 /* bps */
  89. #define DEFAULT_HOLDD 10 /* sec */
  90. #define DEFAULT_TXD 300 /* ms */
  91. #define DEFAULT_TXTAIL 10 /* ms */
  92. #define DEFAULT_SLOT 100 /* ms */
  93. #define DEFAULT_PERS 64 /* 0->255 */
  94. struct yam_port {
  95. int magic;
  96. int bitrate;
  97. int baudrate;
  98. int iobase;
  99. int irq;
  100. int dupmode;
  101. struct net_device *dev;
  102. int nb_rxint;
  103. int nb_mdint;
  104. /* Parameters section */
  105. int txd; /* tx delay */
  106. int holdd; /* duplex ptt delay */
  107. int txtail; /* txtail delay */
  108. int slot; /* slottime */
  109. int pers; /* persistence */
  110. /* Tx section */
  111. int tx_state;
  112. int tx_count;
  113. int slotcnt;
  114. unsigned char tx_buf[YAM_MAX_FRAME];
  115. int tx_len;
  116. int tx_crcl, tx_crch;
  117. struct sk_buff_head send_queue; /* Packets awaiting transmission */
  118. /* Rx section */
  119. int dcd;
  120. unsigned char rx_buf[YAM_MAX_FRAME];
  121. int rx_len;
  122. int rx_crcl, rx_crch;
  123. };
  124. struct yam_mcs {
  125. unsigned char bits[YAM_FPGA_SIZE];
  126. int bitrate;
  127. struct yam_mcs *next;
  128. };
  129. static struct net_device *yam_devs[NR_PORTS];
  130. static struct yam_mcs *yam_data;
  131. static DEFINE_TIMER(yam_timer, NULL, 0, 0);
  132. /* --------------------------------------------------------------------- */
  133. #define RBR(iobase) (iobase+0)
  134. #define THR(iobase) (iobase+0)
  135. #define IER(iobase) (iobase+1)
  136. #define IIR(iobase) (iobase+2)
  137. #define FCR(iobase) (iobase+2)
  138. #define LCR(iobase) (iobase+3)
  139. #define MCR(iobase) (iobase+4)
  140. #define LSR(iobase) (iobase+5)
  141. #define MSR(iobase) (iobase+6)
  142. #define SCR(iobase) (iobase+7)
  143. #define DLL(iobase) (iobase+0)
  144. #define DLM(iobase) (iobase+1)
  145. #define YAM_EXTENT 8
  146. /* Interrupt Identification Register Bit Masks */
  147. #define IIR_NOPEND 1
  148. #define IIR_MSR 0
  149. #define IIR_TX 2
  150. #define IIR_RX 4
  151. #define IIR_LSR 6
  152. #define IIR_TIMEOUT 12 /* Fifo mode only */
  153. #define IIR_MASK 0x0F
  154. /* Interrupt Enable Register Bit Masks */
  155. #define IER_RX 1 /* enable rx interrupt */
  156. #define IER_TX 2 /* enable tx interrupt */
  157. #define IER_LSR 4 /* enable line status interrupts */
  158. #define IER_MSR 8 /* enable modem status interrupts */
  159. /* Modem Control Register Bit Masks */
  160. #define MCR_DTR 0x01 /* DTR output */
  161. #define MCR_RTS 0x02 /* RTS output */
  162. #define MCR_OUT1 0x04 /* OUT1 output (not accessible in RS232) */
  163. #define MCR_OUT2 0x08 /* Master Interrupt enable (must be set on PCs) */
  164. #define MCR_LOOP 0x10 /* Loopback enable */
  165. /* Modem Status Register Bit Masks */
  166. #define MSR_DCTS 0x01 /* Delta CTS input */
  167. #define MSR_DDSR 0x02 /* Delta DSR */
  168. #define MSR_DRIN 0x04 /* Delta RI */
  169. #define MSR_DDCD 0x08 /* Delta DCD */
  170. #define MSR_CTS 0x10 /* CTS input */
  171. #define MSR_DSR 0x20 /* DSR input */
  172. #define MSR_RING 0x40 /* RI input */
  173. #define MSR_DCD 0x80 /* DCD input */
  174. /* line status register bit mask */
  175. #define LSR_RXC 0x01
  176. #define LSR_OE 0x02
  177. #define LSR_PE 0x04
  178. #define LSR_FE 0x08
  179. #define LSR_BREAK 0x10
  180. #define LSR_THRE 0x20
  181. #define LSR_TSRE 0x40
  182. /* Line Control Register Bit Masks */
  183. #define LCR_DLAB 0x80
  184. #define LCR_BREAK 0x40
  185. #define LCR_PZERO 0x28
  186. #define LCR_PEVEN 0x18
  187. #define LCR_PODD 0x08
  188. #define LCR_STOP1 0x00
  189. #define LCR_STOP2 0x04
  190. #define LCR_BIT5 0x00
  191. #define LCR_BIT6 0x02
  192. #define LCR_BIT7 0x01
  193. #define LCR_BIT8 0x03
  194. /* YAM Modem <-> UART Port mapping */
  195. #define TX_RDY MSR_DCTS /* transmitter ready to send */
  196. #define RX_DCD MSR_DCD /* carrier detect */
  197. #define RX_FLAG MSR_RING /* hdlc flag received */
  198. #define FPGA_DONE MSR_DSR /* FPGA is configured */
  199. #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */
  200. #define PTT_OFF (MCR_DTR|MCR_OUT2) /* release PTT */
  201. #define ENABLE_RXINT IER_RX /* enable uart rx interrupt during rx */
  202. #define ENABLE_TXINT IER_MSR /* enable uart ms interrupt during tx */
  203. #define ENABLE_RTXINT (IER_RX|IER_MSR) /* full duplex operations */
  204. /*************************************************************************
  205. * CRC Tables
  206. ************************************************************************/
  207. static const unsigned char chktabl[256] =
  208. {0x00, 0x89, 0x12, 0x9b, 0x24, 0xad, 0x36, 0xbf, 0x48, 0xc1, 0x5a, 0xd3, 0x6c, 0xe5, 0x7e,
  209. 0xf7, 0x81, 0x08, 0x93, 0x1a, 0xa5, 0x2c, 0xb7, 0x3e, 0xc9, 0x40, 0xdb, 0x52, 0xed, 0x64,
  210. 0xff, 0x76, 0x02, 0x8b, 0x10, 0x99, 0x26, 0xaf, 0x34, 0xbd, 0x4a, 0xc3, 0x58, 0xd1, 0x6e,
  211. 0xe7, 0x7c, 0xf5, 0x83, 0x0a, 0x91, 0x18, 0xa7, 0x2e, 0xb5, 0x3c, 0xcb, 0x42, 0xd9, 0x50,
  212. 0xef, 0x66, 0xfd, 0x74, 0x04, 0x8d, 0x16, 0x9f, 0x20, 0xa9, 0x32, 0xbb, 0x4c, 0xc5, 0x5e,
  213. 0xd7, 0x68, 0xe1, 0x7a, 0xf3, 0x85, 0x0c, 0x97, 0x1e, 0xa1, 0x28, 0xb3, 0x3a, 0xcd, 0x44,
  214. 0xdf, 0x56, 0xe9, 0x60, 0xfb, 0x72, 0x06, 0x8f, 0x14, 0x9d, 0x22, 0xab, 0x30, 0xb9, 0x4e,
  215. 0xc7, 0x5c, 0xd5, 0x6a, 0xe3, 0x78, 0xf1, 0x87, 0x0e, 0x95, 0x1c, 0xa3, 0x2a, 0xb1, 0x38,
  216. 0xcf, 0x46, 0xdd, 0x54, 0xeb, 0x62, 0xf9, 0x70, 0x08, 0x81, 0x1a, 0x93, 0x2c, 0xa5, 0x3e,
  217. 0xb7, 0x40, 0xc9, 0x52, 0xdb, 0x64, 0xed, 0x76, 0xff, 0x89, 0x00, 0x9b, 0x12, 0xad, 0x24,
  218. 0xbf, 0x36, 0xc1, 0x48, 0xd3, 0x5a, 0xe5, 0x6c, 0xf7, 0x7e, 0x0a, 0x83, 0x18, 0x91, 0x2e,
  219. 0xa7, 0x3c, 0xb5, 0x42, 0xcb, 0x50, 0xd9, 0x66, 0xef, 0x74, 0xfd, 0x8b, 0x02, 0x99, 0x10,
  220. 0xaf, 0x26, 0xbd, 0x34, 0xc3, 0x4a, 0xd1, 0x58, 0xe7, 0x6e, 0xf5, 0x7c, 0x0c, 0x85, 0x1e,
  221. 0x97, 0x28, 0xa1, 0x3a, 0xb3, 0x44, 0xcd, 0x56, 0xdf, 0x60, 0xe9, 0x72, 0xfb, 0x8d, 0x04,
  222. 0x9f, 0x16, 0xa9, 0x20, 0xbb, 0x32, 0xc5, 0x4c, 0xd7, 0x5e, 0xe1, 0x68, 0xf3, 0x7a, 0x0e,
  223. 0x87, 0x1c, 0x95, 0x2a, 0xa3, 0x38, 0xb1, 0x46, 0xcf, 0x54, 0xdd, 0x62, 0xeb, 0x70, 0xf9,
  224. 0x8f, 0x06, 0x9d, 0x14, 0xab, 0x22, 0xb9, 0x30, 0xc7, 0x4e, 0xd5, 0x5c, 0xe3, 0x6a, 0xf1,
  225. 0x78};
  226. static const unsigned char chktabh[256] =
  227. {0x00, 0x11, 0x23, 0x32, 0x46, 0x57, 0x65, 0x74, 0x8c, 0x9d, 0xaf, 0xbe, 0xca, 0xdb, 0xe9,
  228. 0xf8, 0x10, 0x01, 0x33, 0x22, 0x56, 0x47, 0x75, 0x64, 0x9c, 0x8d, 0xbf, 0xae, 0xda, 0xcb,
  229. 0xf9, 0xe8, 0x21, 0x30, 0x02, 0x13, 0x67, 0x76, 0x44, 0x55, 0xad, 0xbc, 0x8e, 0x9f, 0xeb,
  230. 0xfa, 0xc8, 0xd9, 0x31, 0x20, 0x12, 0x03, 0x77, 0x66, 0x54, 0x45, 0xbd, 0xac, 0x9e, 0x8f,
  231. 0xfb, 0xea, 0xd8, 0xc9, 0x42, 0x53, 0x61, 0x70, 0x04, 0x15, 0x27, 0x36, 0xce, 0xdf, 0xed,
  232. 0xfc, 0x88, 0x99, 0xab, 0xba, 0x52, 0x43, 0x71, 0x60, 0x14, 0x05, 0x37, 0x26, 0xde, 0xcf,
  233. 0xfd, 0xec, 0x98, 0x89, 0xbb, 0xaa, 0x63, 0x72, 0x40, 0x51, 0x25, 0x34, 0x06, 0x17, 0xef,
  234. 0xfe, 0xcc, 0xdd, 0xa9, 0xb8, 0x8a, 0x9b, 0x73, 0x62, 0x50, 0x41, 0x35, 0x24, 0x16, 0x07,
  235. 0xff, 0xee, 0xdc, 0xcd, 0xb9, 0xa8, 0x9a, 0x8b, 0x84, 0x95, 0xa7, 0xb6, 0xc2, 0xd3, 0xe1,
  236. 0xf0, 0x08, 0x19, 0x2b, 0x3a, 0x4e, 0x5f, 0x6d, 0x7c, 0x94, 0x85, 0xb7, 0xa6, 0xd2, 0xc3,
  237. 0xf1, 0xe0, 0x18, 0x09, 0x3b, 0x2a, 0x5e, 0x4f, 0x7d, 0x6c, 0xa5, 0xb4, 0x86, 0x97, 0xe3,
  238. 0xf2, 0xc0, 0xd1, 0x29, 0x38, 0x0a, 0x1b, 0x6f, 0x7e, 0x4c, 0x5d, 0xb5, 0xa4, 0x96, 0x87,
  239. 0xf3, 0xe2, 0xd0, 0xc1, 0x39, 0x28, 0x1a, 0x0b, 0x7f, 0x6e, 0x5c, 0x4d, 0xc6, 0xd7, 0xe5,
  240. 0xf4, 0x80, 0x91, 0xa3, 0xb2, 0x4a, 0x5b, 0x69, 0x78, 0x0c, 0x1d, 0x2f, 0x3e, 0xd6, 0xc7,
  241. 0xf5, 0xe4, 0x90, 0x81, 0xb3, 0xa2, 0x5a, 0x4b, 0x79, 0x68, 0x1c, 0x0d, 0x3f, 0x2e, 0xe7,
  242. 0xf6, 0xc4, 0xd5, 0xa1, 0xb0, 0x82, 0x93, 0x6b, 0x7a, 0x48, 0x59, 0x2d, 0x3c, 0x0e, 0x1f,
  243. 0xf7, 0xe6, 0xd4, 0xc5, 0xb1, 0xa0, 0x92, 0x83, 0x7b, 0x6a, 0x58, 0x49, 0x3d, 0x2c, 0x1e,
  244. 0x0f};
  245. /*************************************************************************
  246. * FPGA functions
  247. ************************************************************************/
  248. static void delay(int ms)
  249. {
  250. unsigned long timeout = jiffies + ((ms * HZ) / 1000);
  251. while (time_before(jiffies, timeout))
  252. cpu_relax();
  253. }
  254. /*
  255. * reset FPGA
  256. */
  257. static void fpga_reset(int iobase)
  258. {
  259. outb(0, IER(iobase));
  260. outb(LCR_DLAB | LCR_BIT5, LCR(iobase));
  261. outb(1, DLL(iobase));
  262. outb(0, DLM(iobase));
  263. outb(LCR_BIT5, LCR(iobase));
  264. inb(LSR(iobase));
  265. inb(MSR(iobase));
  266. /* turn off FPGA supply voltage */
  267. outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
  268. delay(100);
  269. /* turn on FPGA supply voltage again */
  270. outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  271. delay(100);
  272. }
  273. /*
  274. * send one byte to FPGA
  275. */
  276. static int fpga_write(int iobase, unsigned char wrd)
  277. {
  278. unsigned char bit;
  279. int k;
  280. unsigned long timeout = jiffies + HZ / 10;
  281. for (k = 0; k < 8; k++) {
  282. bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR;
  283. outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));
  284. wrd <<= 1;
  285. outb(0xfc, THR(iobase));
  286. while ((inb(LSR(iobase)) & LSR_TSRE) == 0)
  287. if (time_after(jiffies, timeout))
  288. return -1;
  289. }
  290. return 0;
  291. }
  292. /*
  293. * predef should be 0 for loading user defined mcs
  294. * predef should be YAM_1200 for loading predef 1200 mcs
  295. * predef should be YAM_9600 for loading predef 9600 mcs
  296. */
  297. static unsigned char *add_mcs(unsigned char *bits, int bitrate,
  298. unsigned int predef)
  299. {
  300. const char *fw_name[2] = {FIRMWARE_9600, FIRMWARE_1200};
  301. const struct firmware *fw;
  302. struct platform_device *pdev;
  303. struct yam_mcs *p;
  304. int err;
  305. switch (predef) {
  306. case 0:
  307. fw = NULL;
  308. break;
  309. case YAM_1200:
  310. case YAM_9600:
  311. predef--;
  312. pdev = platform_device_register_simple("yam", 0, NULL, 0);
  313. if (IS_ERR(pdev)) {
  314. printk(KERN_ERR "yam: Failed to register firmware\n");
  315. return NULL;
  316. }
  317. err = request_firmware(&fw, fw_name[predef], &pdev->dev);
  318. platform_device_unregister(pdev);
  319. if (err) {
  320. printk(KERN_ERR "Failed to load firmware \"%s\"\n",
  321. fw_name[predef]);
  322. return NULL;
  323. }
  324. if (fw->size != YAM_FPGA_SIZE) {
  325. printk(KERN_ERR "Bogus length %zu in firmware \"%s\"\n",
  326. fw->size, fw_name[predef]);
  327. release_firmware(fw);
  328. return NULL;
  329. }
  330. bits = (unsigned char *)fw->data;
  331. break;
  332. default:
  333. printk(KERN_ERR "yam: Invalid predef number %u\n", predef);
  334. return NULL;
  335. }
  336. /* If it already exists, replace the bit data */
  337. p = yam_data;
  338. while (p) {
  339. if (p->bitrate == bitrate) {
  340. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  341. return p->bits;
  342. }
  343. p = p->next;
  344. }
  345. /* Allocate a new mcs */
  346. if ((p = kmalloc(sizeof(struct yam_mcs), GFP_KERNEL)) == NULL) {
  347. printk(KERN_WARNING "YAM: no memory to allocate mcs\n");
  348. release_firmware(fw);
  349. return NULL;
  350. }
  351. memcpy(p->bits, bits, YAM_FPGA_SIZE);
  352. p->bitrate = bitrate;
  353. p->next = yam_data;
  354. yam_data = p;
  355. release_firmware(fw);
  356. return p->bits;
  357. }
  358. static unsigned char *get_mcs(int bitrate)
  359. {
  360. struct yam_mcs *p;
  361. p = yam_data;
  362. while (p) {
  363. if (p->bitrate == bitrate)
  364. return p->bits;
  365. p = p->next;
  366. }
  367. /* Load predefined mcs data */
  368. switch (bitrate) {
  369. case 1200:
  370. /* setting predef as YAM_1200 for loading predef 1200 mcs */
  371. return add_mcs(NULL, bitrate, YAM_1200);
  372. default:
  373. /* setting predef as YAM_9600 for loading predef 9600 mcs */
  374. return add_mcs(NULL, bitrate, YAM_9600);
  375. }
  376. }
  377. /*
  378. * download bitstream to FPGA
  379. * data is contained in bits[] array in yam1200.h resp. yam9600.h
  380. */
  381. static int fpga_download(int iobase, int bitrate)
  382. {
  383. int i, rc;
  384. unsigned char *pbits;
  385. pbits = get_mcs(bitrate);
  386. if (pbits == NULL)
  387. return -1;
  388. fpga_reset(iobase);
  389. for (i = 0; i < YAM_FPGA_SIZE; i++) {
  390. if (fpga_write(iobase, pbits[i])) {
  391. printk(KERN_ERR "yam: error in write cycle\n");
  392. return -1; /* write... */
  393. }
  394. }
  395. fpga_write(iobase, 0xFF);
  396. rc = inb(MSR(iobase)); /* check DONE signal */
  397. /* Needed for some hardwares */
  398. delay(50);
  399. return (rc & MSR_DSR) ? 0 : -1;
  400. }
  401. /************************************************************************
  402. * Serial port init
  403. ************************************************************************/
  404. static void yam_set_uart(struct net_device *dev)
  405. {
  406. struct yam_port *yp = netdev_priv(dev);
  407. int divisor = 115200 / yp->baudrate;
  408. outb(0, IER(dev->base_addr));
  409. outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr));
  410. outb(divisor, DLL(dev->base_addr));
  411. outb(0, DLM(dev->base_addr));
  412. outb(LCR_BIT8, LCR(dev->base_addr));
  413. outb(PTT_OFF, MCR(dev->base_addr));
  414. outb(0x00, FCR(dev->base_addr));
  415. /* Flush pending irq */
  416. inb(RBR(dev->base_addr));
  417. inb(MSR(dev->base_addr));
  418. /* Enable rx irq */
  419. outb(ENABLE_RTXINT, IER(dev->base_addr));
  420. }
  421. /* --------------------------------------------------------------------- */
  422. enum uart {
  423. c_uart_unknown, c_uart_8250,
  424. c_uart_16450, c_uart_16550, c_uart_16550A
  425. };
  426. static const char *uart_str[] =
  427. {"unknown", "8250", "16450", "16550", "16550A"};
  428. static enum uart yam_check_uart(unsigned int iobase)
  429. {
  430. unsigned char b1, b2, b3;
  431. enum uart u;
  432. enum uart uart_tab[] =
  433. {c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A};
  434. b1 = inb(MCR(iobase));
  435. outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
  436. b2 = inb(MSR(iobase));
  437. outb(0x1a, MCR(iobase));
  438. b3 = inb(MSR(iobase)) & 0xf0;
  439. outb(b1, MCR(iobase)); /* restore old values */
  440. outb(b2, MSR(iobase));
  441. if (b3 != 0x90)
  442. return c_uart_unknown;
  443. inb(RBR(iobase));
  444. inb(RBR(iobase));
  445. outb(0x01, FCR(iobase)); /* enable FIFOs */
  446. u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
  447. if (u == c_uart_16450) {
  448. outb(0x5a, SCR(iobase));
  449. b1 = inb(SCR(iobase));
  450. outb(0xa5, SCR(iobase));
  451. b2 = inb(SCR(iobase));
  452. if ((b1 != 0x5a) || (b2 != 0xa5))
  453. u = c_uart_8250;
  454. }
  455. return u;
  456. }
  457. /******************************************************************************
  458. * Rx Section
  459. ******************************************************************************/
  460. static inline void yam_rx_flag(struct net_device *dev, struct yam_port *yp)
  461. {
  462. if (yp->dcd && yp->rx_len >= 3 && yp->rx_len < YAM_MAX_FRAME) {
  463. int pkt_len = yp->rx_len - 2 + 1; /* -CRC + kiss */
  464. struct sk_buff *skb;
  465. if ((yp->rx_crch & yp->rx_crcl) != 0xFF) {
  466. /* Bad crc */
  467. } else {
  468. if (!(skb = dev_alloc_skb(pkt_len))) {
  469. printk(KERN_WARNING "%s: memory squeeze, dropping packet\n", dev->name);
  470. ++dev->stats.rx_dropped;
  471. } else {
  472. unsigned char *cp;
  473. cp = skb_put(skb, pkt_len);
  474. *cp++ = 0; /* KISS kludge */
  475. memcpy(cp, yp->rx_buf, pkt_len - 1);
  476. skb->protocol = ax25_type_trans(skb, dev);
  477. netif_rx(skb);
  478. ++dev->stats.rx_packets;
  479. }
  480. }
  481. }
  482. yp->rx_len = 0;
  483. yp->rx_crcl = 0x21;
  484. yp->rx_crch = 0xf3;
  485. }
  486. static inline void yam_rx_byte(struct net_device *dev, struct yam_port *yp, unsigned char rxb)
  487. {
  488. if (yp->rx_len < YAM_MAX_FRAME) {
  489. unsigned char c = yp->rx_crcl;
  490. yp->rx_crcl = (chktabl[c] ^ yp->rx_crch);
  491. yp->rx_crch = (chktabh[c] ^ rxb);
  492. yp->rx_buf[yp->rx_len++] = rxb;
  493. }
  494. }
  495. /********************************************************************************
  496. * TX Section
  497. ********************************************************************************/
  498. static void ptt_on(struct net_device *dev)
  499. {
  500. outb(PTT_ON, MCR(dev->base_addr));
  501. }
  502. static void ptt_off(struct net_device *dev)
  503. {
  504. outb(PTT_OFF, MCR(dev->base_addr));
  505. }
  506. static netdev_tx_t yam_send_packet(struct sk_buff *skb,
  507. struct net_device *dev)
  508. {
  509. struct yam_port *yp = netdev_priv(dev);
  510. skb_queue_tail(&yp->send_queue, skb);
  511. dev->trans_start = jiffies;
  512. return NETDEV_TX_OK;
  513. }
  514. static void yam_start_tx(struct net_device *dev, struct yam_port *yp)
  515. {
  516. if ((yp->tx_state == TX_TAIL) || (yp->txd == 0))
  517. yp->tx_count = 1;
  518. else
  519. yp->tx_count = (yp->bitrate * yp->txd) / 8000;
  520. yp->tx_state = TX_HEAD;
  521. ptt_on(dev);
  522. }
  523. static void yam_arbitrate(struct net_device *dev)
  524. {
  525. struct yam_port *yp = netdev_priv(dev);
  526. if (yp->magic != YAM_MAGIC || yp->tx_state != TX_OFF ||
  527. skb_queue_empty(&yp->send_queue))
  528. return;
  529. /* tx_state is TX_OFF and there is data to send */
  530. if (yp->dupmode) {
  531. /* Full duplex mode, don't wait */
  532. yam_start_tx(dev, yp);
  533. return;
  534. }
  535. if (yp->dcd) {
  536. /* DCD on, wait slotime ... */
  537. yp->slotcnt = yp->slot / 10;
  538. return;
  539. }
  540. /* Is slottime passed ? */
  541. if ((--yp->slotcnt) > 0)
  542. return;
  543. yp->slotcnt = yp->slot / 10;
  544. /* is random > persist ? */
  545. if ((random32() % 256) > yp->pers)
  546. return;
  547. yam_start_tx(dev, yp);
  548. }
  549. static void yam_dotimer(unsigned long dummy)
  550. {
  551. int i;
  552. for (i = 0; i < NR_PORTS; i++) {
  553. struct net_device *dev = yam_devs[i];
  554. if (dev && netif_running(dev))
  555. yam_arbitrate(dev);
  556. }
  557. yam_timer.expires = jiffies + HZ / 100;
  558. add_timer(&yam_timer);
  559. }
  560. static void yam_tx_byte(struct net_device *dev, struct yam_port *yp)
  561. {
  562. struct sk_buff *skb;
  563. unsigned char b, temp;
  564. switch (yp->tx_state) {
  565. case TX_OFF:
  566. break;
  567. case TX_HEAD:
  568. if (--yp->tx_count <= 0) {
  569. if (!(skb = skb_dequeue(&yp->send_queue))) {
  570. ptt_off(dev);
  571. yp->tx_state = TX_OFF;
  572. break;
  573. }
  574. yp->tx_state = TX_DATA;
  575. if (skb->data[0] != 0) {
  576. /* do_kiss_params(s, skb->data, skb->len); */
  577. dev_kfree_skb_any(skb);
  578. break;
  579. }
  580. yp->tx_len = skb->len - 1; /* strip KISS byte */
  581. if (yp->tx_len >= YAM_MAX_FRAME || yp->tx_len < 2) {
  582. dev_kfree_skb_any(skb);
  583. break;
  584. }
  585. skb_copy_from_linear_data_offset(skb, 1,
  586. yp->tx_buf,
  587. yp->tx_len);
  588. dev_kfree_skb_any(skb);
  589. yp->tx_count = 0;
  590. yp->tx_crcl = 0x21;
  591. yp->tx_crch = 0xf3;
  592. yp->tx_state = TX_DATA;
  593. }
  594. break;
  595. case TX_DATA:
  596. b = yp->tx_buf[yp->tx_count++];
  597. outb(b, THR(dev->base_addr));
  598. temp = yp->tx_crcl;
  599. yp->tx_crcl = chktabl[temp] ^ yp->tx_crch;
  600. yp->tx_crch = chktabh[temp] ^ b;
  601. if (yp->tx_count >= yp->tx_len) {
  602. yp->tx_state = TX_CRC1;
  603. }
  604. break;
  605. case TX_CRC1:
  606. yp->tx_crch = chktabl[yp->tx_crcl] ^ yp->tx_crch;
  607. yp->tx_crcl = chktabh[yp->tx_crcl] ^ chktabl[yp->tx_crch] ^ 0xff;
  608. outb(yp->tx_crcl, THR(dev->base_addr));
  609. yp->tx_state = TX_CRC2;
  610. break;
  611. case TX_CRC2:
  612. outb(chktabh[yp->tx_crch] ^ 0xFF, THR(dev->base_addr));
  613. if (skb_queue_empty(&yp->send_queue)) {
  614. yp->tx_count = (yp->bitrate * yp->txtail) / 8000;
  615. if (yp->dupmode == 2)
  616. yp->tx_count += (yp->bitrate * yp->holdd) / 8;
  617. if (yp->tx_count == 0)
  618. yp->tx_count = 1;
  619. yp->tx_state = TX_TAIL;
  620. } else {
  621. yp->tx_count = 1;
  622. yp->tx_state = TX_HEAD;
  623. }
  624. ++dev->stats.tx_packets;
  625. break;
  626. case TX_TAIL:
  627. if (--yp->tx_count <= 0) {
  628. yp->tx_state = TX_OFF;
  629. ptt_off(dev);
  630. }
  631. break;
  632. }
  633. }
  634. /***********************************************************************************
  635. * ISR routine
  636. ************************************************************************************/
  637. static irqreturn_t yam_interrupt(int irq, void *dev_id)
  638. {
  639. struct net_device *dev;
  640. struct yam_port *yp;
  641. unsigned char iir;
  642. int counter = 100;
  643. int i;
  644. int handled = 0;
  645. for (i = 0; i < NR_PORTS; i++) {
  646. dev = yam_devs[i];
  647. yp = netdev_priv(dev);
  648. if (!netif_running(dev))
  649. continue;
  650. while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) {
  651. unsigned char msr = inb(MSR(dev->base_addr));
  652. unsigned char lsr = inb(LSR(dev->base_addr));
  653. unsigned char rxb;
  654. handled = 1;
  655. if (lsr & LSR_OE)
  656. ++dev->stats.rx_fifo_errors;
  657. yp->dcd = (msr & RX_DCD) ? 1 : 0;
  658. if (--counter <= 0) {
  659. printk(KERN_ERR "%s: too many irq iir=%d\n",
  660. dev->name, iir);
  661. goto out;
  662. }
  663. if (msr & TX_RDY) {
  664. ++yp->nb_mdint;
  665. yam_tx_byte(dev, yp);
  666. }
  667. if (lsr & LSR_RXC) {
  668. ++yp->nb_rxint;
  669. rxb = inb(RBR(dev->base_addr));
  670. if (msr & RX_FLAG)
  671. yam_rx_flag(dev, yp);
  672. else
  673. yam_rx_byte(dev, yp, rxb);
  674. }
  675. }
  676. }
  677. out:
  678. return IRQ_RETVAL(handled);
  679. }
  680. #ifdef CONFIG_PROC_FS
  681. static void *yam_seq_start(struct seq_file *seq, loff_t *pos)
  682. {
  683. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  684. }
  685. static void *yam_seq_next(struct seq_file *seq, void *v, loff_t *pos)
  686. {
  687. ++*pos;
  688. return (*pos < NR_PORTS) ? yam_devs[*pos] : NULL;
  689. }
  690. static void yam_seq_stop(struct seq_file *seq, void *v)
  691. {
  692. }
  693. static int yam_seq_show(struct seq_file *seq, void *v)
  694. {
  695. struct net_device *dev = v;
  696. const struct yam_port *yp = netdev_priv(dev);
  697. seq_printf(seq, "Device %s\n", dev->name);
  698. seq_printf(seq, " Up %d\n", netif_running(dev));
  699. seq_printf(seq, " Speed %u\n", yp->bitrate);
  700. seq_printf(seq, " IoBase 0x%x\n", yp->iobase);
  701. seq_printf(seq, " BaudRate %u\n", yp->baudrate);
  702. seq_printf(seq, " IRQ %u\n", yp->irq);
  703. seq_printf(seq, " TxState %u\n", yp->tx_state);
  704. seq_printf(seq, " Duplex %u\n", yp->dupmode);
  705. seq_printf(seq, " HoldDly %u\n", yp->holdd);
  706. seq_printf(seq, " TxDelay %u\n", yp->txd);
  707. seq_printf(seq, " TxTail %u\n", yp->txtail);
  708. seq_printf(seq, " SlotTime %u\n", yp->slot);
  709. seq_printf(seq, " Persist %u\n", yp->pers);
  710. seq_printf(seq, " TxFrames %lu\n", dev->stats.tx_packets);
  711. seq_printf(seq, " RxFrames %lu\n", dev->stats.rx_packets);
  712. seq_printf(seq, " TxInt %u\n", yp->nb_mdint);
  713. seq_printf(seq, " RxInt %u\n", yp->nb_rxint);
  714. seq_printf(seq, " RxOver %lu\n", dev->stats.rx_fifo_errors);
  715. seq_printf(seq, "\n");
  716. return 0;
  717. }
  718. static const struct seq_operations yam_seqops = {
  719. .start = yam_seq_start,
  720. .next = yam_seq_next,
  721. .stop = yam_seq_stop,
  722. .show = yam_seq_show,
  723. };
  724. static int yam_info_open(struct inode *inode, struct file *file)
  725. {
  726. return seq_open(file, &yam_seqops);
  727. }
  728. static const struct file_operations yam_info_fops = {
  729. .owner = THIS_MODULE,
  730. .open = yam_info_open,
  731. .read = seq_read,
  732. .llseek = seq_lseek,
  733. .release = seq_release,
  734. };
  735. #endif
  736. /* --------------------------------------------------------------------- */
  737. static int yam_open(struct net_device *dev)
  738. {
  739. struct yam_port *yp = netdev_priv(dev);
  740. enum uart u;
  741. int i;
  742. int ret=0;
  743. printk(KERN_INFO "Trying %s at iobase 0x%lx irq %u\n", dev->name, dev->base_addr, dev->irq);
  744. if (!dev || !yp->bitrate)
  745. return -ENXIO;
  746. if (!dev->base_addr || dev->base_addr > 0x1000 - YAM_EXTENT ||
  747. dev->irq < 2 || dev->irq > 15) {
  748. return -ENXIO;
  749. }
  750. if (!request_region(dev->base_addr, YAM_EXTENT, dev->name))
  751. {
  752. printk(KERN_ERR "%s: cannot 0x%lx busy\n", dev->name, dev->base_addr);
  753. return -EACCES;
  754. }
  755. if ((u = yam_check_uart(dev->base_addr)) == c_uart_unknown) {
  756. printk(KERN_ERR "%s: cannot find uart type\n", dev->name);
  757. ret = -EIO;
  758. goto out_release_base;
  759. }
  760. if (fpga_download(dev->base_addr, yp->bitrate)) {
  761. printk(KERN_ERR "%s: cannot init FPGA\n", dev->name);
  762. ret = -EIO;
  763. goto out_release_base;
  764. }
  765. outb(0, IER(dev->base_addr));
  766. if (request_irq(dev->irq, yam_interrupt, IRQF_DISABLED | IRQF_SHARED, dev->name, dev)) {
  767. printk(KERN_ERR "%s: irq %d busy\n", dev->name, dev->irq);
  768. ret = -EBUSY;
  769. goto out_release_base;
  770. }
  771. yam_set_uart(dev);
  772. netif_start_queue(dev);
  773. yp->slotcnt = yp->slot / 10;
  774. /* Reset overruns for all ports - FPGA programming makes overruns */
  775. for (i = 0; i < NR_PORTS; i++) {
  776. struct net_device *yam_dev = yam_devs[i];
  777. inb(LSR(yam_dev->base_addr));
  778. yam_dev->stats.rx_fifo_errors = 0;
  779. }
  780. printk(KERN_INFO "%s at iobase 0x%lx irq %u uart %s\n", dev->name, dev->base_addr, dev->irq,
  781. uart_str[u]);
  782. return 0;
  783. out_release_base:
  784. release_region(dev->base_addr, YAM_EXTENT);
  785. return ret;
  786. }
  787. /* --------------------------------------------------------------------- */
  788. static int yam_close(struct net_device *dev)
  789. {
  790. struct sk_buff *skb;
  791. struct yam_port *yp = netdev_priv(dev);
  792. if (!dev)
  793. return -EINVAL;
  794. /*
  795. * disable interrupts
  796. */
  797. outb(0, IER(dev->base_addr));
  798. outb(1, MCR(dev->base_addr));
  799. /* Remove IRQ handler if last */
  800. free_irq(dev->irq,dev);
  801. release_region(dev->base_addr, YAM_EXTENT);
  802. netif_stop_queue(dev);
  803. while ((skb = skb_dequeue(&yp->send_queue)))
  804. dev_kfree_skb(skb);
  805. printk(KERN_INFO "%s: close yam at iobase 0x%lx irq %u\n",
  806. yam_drvname, dev->base_addr, dev->irq);
  807. return 0;
  808. }
  809. /* --------------------------------------------------------------------- */
  810. static int yam_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  811. {
  812. struct yam_port *yp = netdev_priv(dev);
  813. struct yamdrv_ioctl_cfg yi;
  814. struct yamdrv_ioctl_mcs *ym;
  815. int ioctl_cmd;
  816. if (copy_from_user(&ioctl_cmd, ifr->ifr_data, sizeof(int)))
  817. return -EFAULT;
  818. if (yp->magic != YAM_MAGIC)
  819. return -EINVAL;
  820. if (!capable(CAP_NET_ADMIN))
  821. return -EPERM;
  822. if (cmd != SIOCDEVPRIVATE)
  823. return -EINVAL;
  824. switch (ioctl_cmd) {
  825. case SIOCYAMRESERVED:
  826. return -EINVAL; /* unused */
  827. case SIOCYAMSMCS:
  828. if (netif_running(dev))
  829. return -EINVAL; /* Cannot change this parameter when up */
  830. if ((ym = kmalloc(sizeof(struct yamdrv_ioctl_mcs), GFP_KERNEL)) == NULL)
  831. return -ENOBUFS;
  832. ym->bitrate = 9600;
  833. if (copy_from_user(ym, ifr->ifr_data, sizeof(struct yamdrv_ioctl_mcs))) {
  834. kfree(ym);
  835. return -EFAULT;
  836. }
  837. if (ym->bitrate > YAM_MAXBITRATE) {
  838. kfree(ym);
  839. return -EINVAL;
  840. }
  841. /* setting predef as 0 for loading userdefined mcs data */
  842. add_mcs(ym->bits, ym->bitrate, 0);
  843. kfree(ym);
  844. break;
  845. case SIOCYAMSCFG:
  846. if (!capable(CAP_SYS_RAWIO))
  847. return -EPERM;
  848. if (copy_from_user(&yi, ifr->ifr_data, sizeof(struct yamdrv_ioctl_cfg)))
  849. return -EFAULT;
  850. if ((yi.cfg.mask & YAM_IOBASE) && netif_running(dev))
  851. return -EINVAL; /* Cannot change this parameter when up */
  852. if ((yi.cfg.mask & YAM_IRQ) && netif_running(dev))
  853. return -EINVAL; /* Cannot change this parameter when up */
  854. if ((yi.cfg.mask & YAM_BITRATE) && netif_running(dev))
  855. return -EINVAL; /* Cannot change this parameter when up */
  856. if ((yi.cfg.mask & YAM_BAUDRATE) && netif_running(dev))
  857. return -EINVAL; /* Cannot change this parameter when up */
  858. if (yi.cfg.mask & YAM_IOBASE) {
  859. yp->iobase = yi.cfg.iobase;
  860. dev->base_addr = yi.cfg.iobase;
  861. }
  862. if (yi.cfg.mask & YAM_IRQ) {
  863. if (yi.cfg.irq > 15)
  864. return -EINVAL;
  865. yp->irq = yi.cfg.irq;
  866. dev->irq = yi.cfg.irq;
  867. }
  868. if (yi.cfg.mask & YAM_BITRATE) {
  869. if (yi.cfg.bitrate > YAM_MAXBITRATE)
  870. return -EINVAL;
  871. yp->bitrate = yi.cfg.bitrate;
  872. }
  873. if (yi.cfg.mask & YAM_BAUDRATE) {
  874. if (yi.cfg.baudrate > YAM_MAXBAUDRATE)
  875. return -EINVAL;
  876. yp->baudrate = yi.cfg.baudrate;
  877. }
  878. if (yi.cfg.mask & YAM_MODE) {
  879. if (yi.cfg.mode > YAM_MAXMODE)
  880. return -EINVAL;
  881. yp->dupmode = yi.cfg.mode;
  882. }
  883. if (yi.cfg.mask & YAM_HOLDDLY) {
  884. if (yi.cfg.holddly > YAM_MAXHOLDDLY)
  885. return -EINVAL;
  886. yp->holdd = yi.cfg.holddly;
  887. }
  888. if (yi.cfg.mask & YAM_TXDELAY) {
  889. if (yi.cfg.txdelay > YAM_MAXTXDELAY)
  890. return -EINVAL;
  891. yp->txd = yi.cfg.txdelay;
  892. }
  893. if (yi.cfg.mask & YAM_TXTAIL) {
  894. if (yi.cfg.txtail > YAM_MAXTXTAIL)
  895. return -EINVAL;
  896. yp->txtail = yi.cfg.txtail;
  897. }
  898. if (yi.cfg.mask & YAM_PERSIST) {
  899. if (yi.cfg.persist > YAM_MAXPERSIST)
  900. return -EINVAL;
  901. yp->pers = yi.cfg.persist;
  902. }
  903. if (yi.cfg.mask & YAM_SLOTTIME) {
  904. if (yi.cfg.slottime > YAM_MAXSLOTTIME)
  905. return -EINVAL;
  906. yp->slot = yi.cfg.slottime;
  907. yp->slotcnt = yp->slot / 10;
  908. }
  909. break;
  910. case SIOCYAMGCFG:
  911. yi.cfg.mask = 0xffffffff;
  912. yi.cfg.iobase = yp->iobase;
  913. yi.cfg.irq = yp->irq;
  914. yi.cfg.bitrate = yp->bitrate;
  915. yi.cfg.baudrate = yp->baudrate;
  916. yi.cfg.mode = yp->dupmode;
  917. yi.cfg.txdelay = yp->txd;
  918. yi.cfg.holddly = yp->holdd;
  919. yi.cfg.txtail = yp->txtail;
  920. yi.cfg.persist = yp->pers;
  921. yi.cfg.slottime = yp->slot;
  922. if (copy_to_user(ifr->ifr_data, &yi, sizeof(struct yamdrv_ioctl_cfg)))
  923. return -EFAULT;
  924. break;
  925. default:
  926. return -EINVAL;
  927. }
  928. return 0;
  929. }
  930. /* --------------------------------------------------------------------- */
  931. static int yam_set_mac_address(struct net_device *dev, void *addr)
  932. {
  933. struct sockaddr *sa = (struct sockaddr *) addr;
  934. /* addr is an AX.25 shifted ASCII mac address */
  935. memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
  936. return 0;
  937. }
  938. /* --------------------------------------------------------------------- */
  939. static const struct net_device_ops yam_netdev_ops = {
  940. .ndo_open = yam_open,
  941. .ndo_stop = yam_close,
  942. .ndo_start_xmit = yam_send_packet,
  943. .ndo_do_ioctl = yam_ioctl,
  944. .ndo_set_mac_address = yam_set_mac_address,
  945. };
  946. static void yam_setup(struct net_device *dev)
  947. {
  948. struct yam_port *yp = netdev_priv(dev);
  949. yp->magic = YAM_MAGIC;
  950. yp->bitrate = DEFAULT_BITRATE;
  951. yp->baudrate = DEFAULT_BITRATE * 2;
  952. yp->iobase = 0;
  953. yp->irq = 0;
  954. yp->dupmode = 0;
  955. yp->holdd = DEFAULT_HOLDD;
  956. yp->txd = DEFAULT_TXD;
  957. yp->txtail = DEFAULT_TXTAIL;
  958. yp->slot = DEFAULT_SLOT;
  959. yp->pers = DEFAULT_PERS;
  960. yp->dev = dev;
  961. dev->base_addr = yp->iobase;
  962. dev->irq = yp->irq;
  963. skb_queue_head_init(&yp->send_queue);
  964. dev->netdev_ops = &yam_netdev_ops;
  965. dev->header_ops = &ax25_header_ops;
  966. dev->type = ARPHRD_AX25;
  967. dev->hard_header_len = AX25_MAX_HEADER_LEN;
  968. dev->mtu = AX25_MTU;
  969. dev->addr_len = AX25_ADDR_LEN;
  970. memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
  971. memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
  972. }
  973. static int __init yam_init_driver(void)
  974. {
  975. struct net_device *dev;
  976. int i, err;
  977. char name[IFNAMSIZ];
  978. printk(yam_drvinfo);
  979. for (i = 0; i < NR_PORTS; i++) {
  980. sprintf(name, "yam%d", i);
  981. dev = alloc_netdev(sizeof(struct yam_port), name,
  982. yam_setup);
  983. if (!dev) {
  984. printk(KERN_ERR "yam: cannot allocate net device %s\n",
  985. dev->name);
  986. err = -ENOMEM;
  987. goto error;
  988. }
  989. err = register_netdev(dev);
  990. if (err) {
  991. printk(KERN_WARNING "yam: cannot register net device %s\n", dev->name);
  992. goto error;
  993. }
  994. yam_devs[i] = dev;
  995. }
  996. yam_timer.function = yam_dotimer;
  997. yam_timer.expires = jiffies + HZ / 100;
  998. add_timer(&yam_timer);
  999. proc_net_fops_create(&init_net, "yam", S_IRUGO, &yam_info_fops);
  1000. return 0;
  1001. error:
  1002. while (--i >= 0) {
  1003. unregister_netdev(yam_devs[i]);
  1004. free_netdev(yam_devs[i]);
  1005. }
  1006. return err;
  1007. }
  1008. /* --------------------------------------------------------------------- */
  1009. static void __exit yam_cleanup_driver(void)
  1010. {
  1011. struct yam_mcs *p;
  1012. int i;
  1013. del_timer(&yam_timer);
  1014. for (i = 0; i < NR_PORTS; i++) {
  1015. struct net_device *dev = yam_devs[i];
  1016. if (dev) {
  1017. unregister_netdev(dev);
  1018. free_netdev(dev);
  1019. }
  1020. }
  1021. while (yam_data) {
  1022. p = yam_data;
  1023. yam_data = yam_data->next;
  1024. kfree(p);
  1025. }
  1026. proc_net_remove(&init_net, "yam");
  1027. }
  1028. /* --------------------------------------------------------------------- */
  1029. MODULE_AUTHOR("Frederic Rible F1OAT frible@teaser.fr");
  1030. MODULE_DESCRIPTION("Yam amateur radio modem driver");
  1031. MODULE_LICENSE("GPL");
  1032. MODULE_FIRMWARE(FIRMWARE_1200);
  1033. MODULE_FIRMWARE(FIRMWARE_9600);
  1034. module_init(yam_init_driver);
  1035. module_exit(yam_cleanup_driver);
  1036. /* --------------------------------------------------------------------- */