w90p910_ether.c 26 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Nuvoton technology corporation.
  3. *
  4. * Wan ZongShun <mcuos.com@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation;version 2 of the License.
  9. *
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/mii.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/skbuff.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/clk.h>
  20. #define DRV_MODULE_NAME "w90p910-emc"
  21. #define DRV_MODULE_VERSION "0.1"
  22. /* Ethernet MAC Registers */
  23. #define REG_CAMCMR 0x00
  24. #define REG_CAMEN 0x04
  25. #define REG_CAMM_BASE 0x08
  26. #define REG_CAML_BASE 0x0c
  27. #define REG_TXDLSA 0x88
  28. #define REG_RXDLSA 0x8C
  29. #define REG_MCMDR 0x90
  30. #define REG_MIID 0x94
  31. #define REG_MIIDA 0x98
  32. #define REG_FFTCR 0x9C
  33. #define REG_TSDR 0xa0
  34. #define REG_RSDR 0xa4
  35. #define REG_DMARFC 0xa8
  36. #define REG_MIEN 0xac
  37. #define REG_MISTA 0xb0
  38. #define REG_CTXDSA 0xcc
  39. #define REG_CTXBSA 0xd0
  40. #define REG_CRXDSA 0xd4
  41. #define REG_CRXBSA 0xd8
  42. /* mac controller bit */
  43. #define MCMDR_RXON 0x01
  44. #define MCMDR_ACP (0x01 << 3)
  45. #define MCMDR_SPCRC (0x01 << 5)
  46. #define MCMDR_TXON (0x01 << 8)
  47. #define MCMDR_FDUP (0x01 << 18)
  48. #define MCMDR_ENMDC (0x01 << 19)
  49. #define MCMDR_OPMOD (0x01 << 20)
  50. #define SWR (0x01 << 24)
  51. /* cam command regiser */
  52. #define CAMCMR_AUP 0x01
  53. #define CAMCMR_AMP (0x01 << 1)
  54. #define CAMCMR_ABP (0x01 << 2)
  55. #define CAMCMR_CCAM (0x01 << 3)
  56. #define CAMCMR_ECMP (0x01 << 4)
  57. #define CAM0EN 0x01
  58. /* mac mii controller bit */
  59. #define MDCCR (0x0a << 20)
  60. #define PHYAD (0x01 << 8)
  61. #define PHYWR (0x01 << 16)
  62. #define PHYBUSY (0x01 << 17)
  63. #define PHYPRESP (0x01 << 18)
  64. #define CAM_ENTRY_SIZE 0x08
  65. /* rx and tx status */
  66. #define TXDS_TXCP (0x01 << 19)
  67. #define RXDS_CRCE (0x01 << 17)
  68. #define RXDS_PTLE (0x01 << 19)
  69. #define RXDS_RXGD (0x01 << 20)
  70. #define RXDS_ALIE (0x01 << 21)
  71. #define RXDS_RP (0x01 << 22)
  72. /* mac interrupt status*/
  73. #define MISTA_EXDEF (0x01 << 19)
  74. #define MISTA_TXBERR (0x01 << 24)
  75. #define MISTA_TDU (0x01 << 23)
  76. #define MISTA_RDU (0x01 << 10)
  77. #define MISTA_RXBERR (0x01 << 11)
  78. #define ENSTART 0x01
  79. #define ENRXINTR 0x01
  80. #define ENRXGD (0x01 << 4)
  81. #define ENRXBERR (0x01 << 11)
  82. #define ENTXINTR (0x01 << 16)
  83. #define ENTXCP (0x01 << 18)
  84. #define ENTXABT (0x01 << 21)
  85. #define ENTXBERR (0x01 << 24)
  86. #define ENMDC (0x01 << 19)
  87. #define PHYBUSY (0x01 << 17)
  88. #define MDCCR_VAL 0xa00000
  89. /* rx and tx owner bit */
  90. #define RX_OWEN_DMA (0x01 << 31)
  91. #define RX_OWEN_CPU (~(0x03 << 30))
  92. #define TX_OWEN_DMA (0x01 << 31)
  93. #define TX_OWEN_CPU (~(0x01 << 31))
  94. /* tx frame desc controller bit */
  95. #define MACTXINTEN 0x04
  96. #define CRCMODE 0x02
  97. #define PADDINGMODE 0x01
  98. /* fftcr controller bit */
  99. #define TXTHD (0x03 << 8)
  100. #define BLENGTH (0x01 << 20)
  101. /* global setting for driver */
  102. #define RX_DESC_SIZE 50
  103. #define TX_DESC_SIZE 10
  104. #define MAX_RBUFF_SZ 0x600
  105. #define MAX_TBUFF_SZ 0x600
  106. #define TX_TIMEOUT 50
  107. #define DELAY 1000
  108. #define CAM0 0x0
  109. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
  110. struct w90p910_rxbd {
  111. unsigned int sl;
  112. unsigned int buffer;
  113. unsigned int reserved;
  114. unsigned int next;
  115. };
  116. struct w90p910_txbd {
  117. unsigned int mode;
  118. unsigned int buffer;
  119. unsigned int sl;
  120. unsigned int next;
  121. };
  122. struct recv_pdesc {
  123. struct w90p910_rxbd desclist[RX_DESC_SIZE];
  124. char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
  125. };
  126. struct tran_pdesc {
  127. struct w90p910_txbd desclist[TX_DESC_SIZE];
  128. char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
  129. };
  130. struct w90p910_ether {
  131. struct recv_pdesc *rdesc;
  132. struct tran_pdesc *tdesc;
  133. dma_addr_t rdesc_phys;
  134. dma_addr_t tdesc_phys;
  135. struct net_device_stats stats;
  136. struct platform_device *pdev;
  137. struct resource *res;
  138. struct sk_buff *skb;
  139. struct clk *clk;
  140. struct clk *rmiiclk;
  141. struct mii_if_info mii;
  142. struct timer_list check_timer;
  143. void __iomem *reg;
  144. unsigned int rxirq;
  145. unsigned int txirq;
  146. unsigned int cur_tx;
  147. unsigned int cur_rx;
  148. unsigned int finish_tx;
  149. unsigned int rx_packets;
  150. unsigned int rx_bytes;
  151. unsigned int start_tx_ptr;
  152. unsigned int start_rx_ptr;
  153. unsigned int linkflag;
  154. };
  155. static void update_linkspeed_register(struct net_device *dev,
  156. unsigned int speed, unsigned int duplex)
  157. {
  158. struct w90p910_ether *ether = netdev_priv(dev);
  159. unsigned int val;
  160. val = __raw_readl(ether->reg + REG_MCMDR);
  161. if (speed == SPEED_100) {
  162. /* 100 full/half duplex */
  163. if (duplex == DUPLEX_FULL) {
  164. val |= (MCMDR_OPMOD | MCMDR_FDUP);
  165. } else {
  166. val |= MCMDR_OPMOD;
  167. val &= ~MCMDR_FDUP;
  168. }
  169. } else {
  170. /* 10 full/half duplex */
  171. if (duplex == DUPLEX_FULL) {
  172. val |= MCMDR_FDUP;
  173. val &= ~MCMDR_OPMOD;
  174. } else {
  175. val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
  176. }
  177. }
  178. __raw_writel(val, ether->reg + REG_MCMDR);
  179. }
  180. static void update_linkspeed(struct net_device *dev)
  181. {
  182. struct w90p910_ether *ether = netdev_priv(dev);
  183. struct platform_device *pdev;
  184. unsigned int bmsr, bmcr, lpa, speed, duplex;
  185. pdev = ether->pdev;
  186. if (!mii_link_ok(&ether->mii)) {
  187. ether->linkflag = 0x0;
  188. netif_carrier_off(dev);
  189. dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
  190. return;
  191. }
  192. if (ether->linkflag == 1)
  193. return;
  194. bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
  195. bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
  196. if (bmcr & BMCR_ANENABLE) {
  197. if (!(bmsr & BMSR_ANEGCOMPLETE))
  198. return;
  199. lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
  200. if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
  201. speed = SPEED_100;
  202. else
  203. speed = SPEED_10;
  204. if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
  205. duplex = DUPLEX_FULL;
  206. else
  207. duplex = DUPLEX_HALF;
  208. } else {
  209. speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
  210. duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  211. }
  212. update_linkspeed_register(dev, speed, duplex);
  213. dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
  214. (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
  215. ether->linkflag = 0x01;
  216. netif_carrier_on(dev);
  217. }
  218. static void w90p910_check_link(unsigned long dev_id)
  219. {
  220. struct net_device *dev = (struct net_device *) dev_id;
  221. struct w90p910_ether *ether = netdev_priv(dev);
  222. update_linkspeed(dev);
  223. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  224. }
  225. static void w90p910_write_cam(struct net_device *dev,
  226. unsigned int x, unsigned char *pval)
  227. {
  228. struct w90p910_ether *ether = netdev_priv(dev);
  229. unsigned int msw, lsw;
  230. msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
  231. lsw = (pval[4] << 24) | (pval[5] << 16);
  232. __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
  233. __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
  234. }
  235. static int w90p910_init_desc(struct net_device *dev)
  236. {
  237. struct w90p910_ether *ether;
  238. struct w90p910_txbd *tdesc;
  239. struct w90p910_rxbd *rdesc;
  240. struct platform_device *pdev;
  241. unsigned int i;
  242. ether = netdev_priv(dev);
  243. pdev = ether->pdev;
  244. ether->tdesc = (struct tran_pdesc *)
  245. dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  246. &ether->tdesc_phys, GFP_KERNEL);
  247. if (!ether->tdesc) {
  248. dev_err(&pdev->dev, "Failed to allocate memory for tx desc\n");
  249. return -ENOMEM;
  250. }
  251. ether->rdesc = (struct recv_pdesc *)
  252. dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  253. &ether->rdesc_phys, GFP_KERNEL);
  254. if (!ether->rdesc) {
  255. dev_err(&pdev->dev, "Failed to allocate memory for rx desc\n");
  256. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  257. ether->tdesc, ether->tdesc_phys);
  258. return -ENOMEM;
  259. }
  260. for (i = 0; i < TX_DESC_SIZE; i++) {
  261. unsigned int offset;
  262. tdesc = &(ether->tdesc->desclist[i]);
  263. if (i == TX_DESC_SIZE - 1)
  264. offset = offsetof(struct tran_pdesc, desclist[0]);
  265. else
  266. offset = offsetof(struct tran_pdesc, desclist[i + 1]);
  267. tdesc->next = ether->tdesc_phys + offset;
  268. tdesc->buffer = ether->tdesc_phys +
  269. offsetof(struct tran_pdesc, tran_buf[i]);
  270. tdesc->sl = 0;
  271. tdesc->mode = 0;
  272. }
  273. ether->start_tx_ptr = ether->tdesc_phys;
  274. for (i = 0; i < RX_DESC_SIZE; i++) {
  275. unsigned int offset;
  276. rdesc = &(ether->rdesc->desclist[i]);
  277. if (i == RX_DESC_SIZE - 1)
  278. offset = offsetof(struct recv_pdesc, desclist[0]);
  279. else
  280. offset = offsetof(struct recv_pdesc, desclist[i + 1]);
  281. rdesc->next = ether->rdesc_phys + offset;
  282. rdesc->sl = RX_OWEN_DMA;
  283. rdesc->buffer = ether->rdesc_phys +
  284. offsetof(struct recv_pdesc, recv_buf[i]);
  285. }
  286. ether->start_rx_ptr = ether->rdesc_phys;
  287. return 0;
  288. }
  289. static void w90p910_set_fifo_threshold(struct net_device *dev)
  290. {
  291. struct w90p910_ether *ether = netdev_priv(dev);
  292. unsigned int val;
  293. val = TXTHD | BLENGTH;
  294. __raw_writel(val, ether->reg + REG_FFTCR);
  295. }
  296. static void w90p910_return_default_idle(struct net_device *dev)
  297. {
  298. struct w90p910_ether *ether = netdev_priv(dev);
  299. unsigned int val;
  300. val = __raw_readl(ether->reg + REG_MCMDR);
  301. val |= SWR;
  302. __raw_writel(val, ether->reg + REG_MCMDR);
  303. }
  304. static void w90p910_trigger_rx(struct net_device *dev)
  305. {
  306. struct w90p910_ether *ether = netdev_priv(dev);
  307. __raw_writel(ENSTART, ether->reg + REG_RSDR);
  308. }
  309. static void w90p910_trigger_tx(struct net_device *dev)
  310. {
  311. struct w90p910_ether *ether = netdev_priv(dev);
  312. __raw_writel(ENSTART, ether->reg + REG_TSDR);
  313. }
  314. static void w90p910_enable_mac_interrupt(struct net_device *dev)
  315. {
  316. struct w90p910_ether *ether = netdev_priv(dev);
  317. unsigned int val;
  318. val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
  319. val |= ENTXBERR | ENRXBERR | ENTXABT;
  320. __raw_writel(val, ether->reg + REG_MIEN);
  321. }
  322. static void w90p910_get_and_clear_int(struct net_device *dev,
  323. unsigned int *val)
  324. {
  325. struct w90p910_ether *ether = netdev_priv(dev);
  326. *val = __raw_readl(ether->reg + REG_MISTA);
  327. __raw_writel(*val, ether->reg + REG_MISTA);
  328. }
  329. static void w90p910_set_global_maccmd(struct net_device *dev)
  330. {
  331. struct w90p910_ether *ether = netdev_priv(dev);
  332. unsigned int val;
  333. val = __raw_readl(ether->reg + REG_MCMDR);
  334. val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
  335. __raw_writel(val, ether->reg + REG_MCMDR);
  336. }
  337. static void w90p910_enable_cam(struct net_device *dev)
  338. {
  339. struct w90p910_ether *ether = netdev_priv(dev);
  340. unsigned int val;
  341. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  342. val = __raw_readl(ether->reg + REG_CAMEN);
  343. val |= CAM0EN;
  344. __raw_writel(val, ether->reg + REG_CAMEN);
  345. }
  346. static void w90p910_enable_cam_command(struct net_device *dev)
  347. {
  348. struct w90p910_ether *ether = netdev_priv(dev);
  349. unsigned int val;
  350. val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
  351. __raw_writel(val, ether->reg + REG_CAMCMR);
  352. }
  353. static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
  354. {
  355. struct w90p910_ether *ether = netdev_priv(dev);
  356. unsigned int val;
  357. val = __raw_readl(ether->reg + REG_MCMDR);
  358. if (enable)
  359. val |= MCMDR_TXON;
  360. else
  361. val &= ~MCMDR_TXON;
  362. __raw_writel(val, ether->reg + REG_MCMDR);
  363. }
  364. static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
  365. {
  366. struct w90p910_ether *ether = netdev_priv(dev);
  367. unsigned int val;
  368. val = __raw_readl(ether->reg + REG_MCMDR);
  369. if (enable)
  370. val |= MCMDR_RXON;
  371. else
  372. val &= ~MCMDR_RXON;
  373. __raw_writel(val, ether->reg + REG_MCMDR);
  374. }
  375. static void w90p910_set_curdest(struct net_device *dev)
  376. {
  377. struct w90p910_ether *ether = netdev_priv(dev);
  378. __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
  379. __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
  380. }
  381. static void w90p910_reset_mac(struct net_device *dev)
  382. {
  383. struct w90p910_ether *ether = netdev_priv(dev);
  384. w90p910_enable_tx(dev, 0);
  385. w90p910_enable_rx(dev, 0);
  386. w90p910_set_fifo_threshold(dev);
  387. w90p910_return_default_idle(dev);
  388. if (!netif_queue_stopped(dev))
  389. netif_stop_queue(dev);
  390. w90p910_init_desc(dev);
  391. dev->trans_start = jiffies;
  392. ether->cur_tx = 0x0;
  393. ether->finish_tx = 0x0;
  394. ether->cur_rx = 0x0;
  395. w90p910_set_curdest(dev);
  396. w90p910_enable_cam(dev);
  397. w90p910_enable_cam_command(dev);
  398. w90p910_enable_mac_interrupt(dev);
  399. w90p910_enable_tx(dev, 1);
  400. w90p910_enable_rx(dev, 1);
  401. w90p910_trigger_tx(dev);
  402. w90p910_trigger_rx(dev);
  403. dev->trans_start = jiffies;
  404. if (netif_queue_stopped(dev))
  405. netif_wake_queue(dev);
  406. }
  407. static void w90p910_mdio_write(struct net_device *dev,
  408. int phy_id, int reg, int data)
  409. {
  410. struct w90p910_ether *ether = netdev_priv(dev);
  411. struct platform_device *pdev;
  412. unsigned int val, i;
  413. pdev = ether->pdev;
  414. __raw_writel(data, ether->reg + REG_MIID);
  415. val = (phy_id << 0x08) | reg;
  416. val |= PHYBUSY | PHYWR | MDCCR_VAL;
  417. __raw_writel(val, ether->reg + REG_MIIDA);
  418. for (i = 0; i < DELAY; i++) {
  419. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  420. break;
  421. }
  422. if (i == DELAY)
  423. dev_warn(&pdev->dev, "mdio write timed out\n");
  424. }
  425. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
  426. {
  427. struct w90p910_ether *ether = netdev_priv(dev);
  428. struct platform_device *pdev;
  429. unsigned int val, i, data;
  430. pdev = ether->pdev;
  431. val = (phy_id << 0x08) | reg;
  432. val |= PHYBUSY | MDCCR_VAL;
  433. __raw_writel(val, ether->reg + REG_MIIDA);
  434. for (i = 0; i < DELAY; i++) {
  435. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  436. break;
  437. }
  438. if (i == DELAY) {
  439. dev_warn(&pdev->dev, "mdio read timed out\n");
  440. data = 0xffff;
  441. } else {
  442. data = __raw_readl(ether->reg + REG_MIID);
  443. }
  444. return data;
  445. }
  446. static int w90p910_set_mac_address(struct net_device *dev, void *addr)
  447. {
  448. struct sockaddr *address = addr;
  449. if (!is_valid_ether_addr(address->sa_data))
  450. return -EADDRNOTAVAIL;
  451. memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
  452. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  453. return 0;
  454. }
  455. static int w90p910_ether_close(struct net_device *dev)
  456. {
  457. struct w90p910_ether *ether = netdev_priv(dev);
  458. struct platform_device *pdev;
  459. pdev = ether->pdev;
  460. dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  461. ether->rdesc, ether->rdesc_phys);
  462. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  463. ether->tdesc, ether->tdesc_phys);
  464. netif_stop_queue(dev);
  465. del_timer_sync(&ether->check_timer);
  466. clk_disable(ether->rmiiclk);
  467. clk_disable(ether->clk);
  468. free_irq(ether->txirq, dev);
  469. free_irq(ether->rxirq, dev);
  470. return 0;
  471. }
  472. static struct net_device_stats *w90p910_ether_stats(struct net_device *dev)
  473. {
  474. struct w90p910_ether *ether;
  475. ether = netdev_priv(dev);
  476. return &ether->stats;
  477. }
  478. static int w90p910_send_frame(struct net_device *dev,
  479. unsigned char *data, int length)
  480. {
  481. struct w90p910_ether *ether;
  482. struct w90p910_txbd *txbd;
  483. struct platform_device *pdev;
  484. unsigned char *buffer;
  485. ether = netdev_priv(dev);
  486. pdev = ether->pdev;
  487. txbd = &ether->tdesc->desclist[ether->cur_tx];
  488. buffer = ether->tdesc->tran_buf[ether->cur_tx];
  489. if (length > 1514) {
  490. dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
  491. length = 1514;
  492. }
  493. txbd->sl = length & 0xFFFF;
  494. memcpy(buffer, data, length);
  495. txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
  496. w90p910_enable_tx(dev, 1);
  497. w90p910_trigger_tx(dev);
  498. if (++ether->cur_tx >= TX_DESC_SIZE)
  499. ether->cur_tx = 0;
  500. txbd = &ether->tdesc->desclist[ether->cur_tx];
  501. dev->trans_start = jiffies;
  502. if (txbd->mode & TX_OWEN_DMA)
  503. netif_stop_queue(dev);
  504. return 0;
  505. }
  506. static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
  507. {
  508. struct w90p910_ether *ether = netdev_priv(dev);
  509. if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
  510. ether->skb = skb;
  511. dev_kfree_skb_irq(skb);
  512. return 0;
  513. }
  514. return -EAGAIN;
  515. }
  516. static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
  517. {
  518. struct w90p910_ether *ether;
  519. struct w90p910_txbd *txbd;
  520. struct platform_device *pdev;
  521. struct net_device *dev;
  522. unsigned int cur_entry, entry, status;
  523. dev = dev_id;
  524. ether = netdev_priv(dev);
  525. pdev = ether->pdev;
  526. w90p910_get_and_clear_int(dev, &status);
  527. cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
  528. entry = ether->tdesc_phys +
  529. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  530. while (entry != cur_entry) {
  531. txbd = &ether->tdesc->desclist[ether->finish_tx];
  532. if (++ether->finish_tx >= TX_DESC_SIZE)
  533. ether->finish_tx = 0;
  534. if (txbd->sl & TXDS_TXCP) {
  535. ether->stats.tx_packets++;
  536. ether->stats.tx_bytes += txbd->sl & 0xFFFF;
  537. } else {
  538. ether->stats.tx_errors++;
  539. }
  540. txbd->sl = 0x0;
  541. txbd->mode = 0x0;
  542. if (netif_queue_stopped(dev))
  543. netif_wake_queue(dev);
  544. entry = ether->tdesc_phys +
  545. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  546. }
  547. if (status & MISTA_EXDEF) {
  548. dev_err(&pdev->dev, "emc defer exceed interrupt\n");
  549. } else if (status & MISTA_TXBERR) {
  550. dev_err(&pdev->dev, "emc bus error interrupt\n");
  551. w90p910_reset_mac(dev);
  552. } else if (status & MISTA_TDU) {
  553. if (netif_queue_stopped(dev))
  554. netif_wake_queue(dev);
  555. }
  556. return IRQ_HANDLED;
  557. }
  558. static void netdev_rx(struct net_device *dev)
  559. {
  560. struct w90p910_ether *ether;
  561. struct w90p910_rxbd *rxbd;
  562. struct platform_device *pdev;
  563. struct sk_buff *skb;
  564. unsigned char *data;
  565. unsigned int length, status, val, entry;
  566. ether = netdev_priv(dev);
  567. pdev = ether->pdev;
  568. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  569. do {
  570. val = __raw_readl(ether->reg + REG_CRXDSA);
  571. entry = ether->rdesc_phys +
  572. offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
  573. if (val == entry)
  574. break;
  575. status = rxbd->sl;
  576. length = status & 0xFFFF;
  577. if (status & RXDS_RXGD) {
  578. data = ether->rdesc->recv_buf[ether->cur_rx];
  579. skb = dev_alloc_skb(length+2);
  580. if (!skb) {
  581. dev_err(&pdev->dev, "get skb buffer error\n");
  582. ether->stats.rx_dropped++;
  583. return;
  584. }
  585. skb->dev = dev;
  586. skb_reserve(skb, 2);
  587. skb_put(skb, length);
  588. skb_copy_to_linear_data(skb, data, length);
  589. skb->protocol = eth_type_trans(skb, dev);
  590. ether->stats.rx_packets++;
  591. ether->stats.rx_bytes += length;
  592. netif_rx(skb);
  593. } else {
  594. ether->stats.rx_errors++;
  595. if (status & RXDS_RP) {
  596. dev_err(&pdev->dev, "rx runt err\n");
  597. ether->stats.rx_length_errors++;
  598. } else if (status & RXDS_CRCE) {
  599. dev_err(&pdev->dev, "rx crc err\n");
  600. ether->stats.rx_crc_errors++;
  601. } else if (status & RXDS_ALIE) {
  602. dev_err(&pdev->dev, "rx aligment err\n");
  603. ether->stats.rx_frame_errors++;
  604. } else if (status & RXDS_PTLE) {
  605. dev_err(&pdev->dev, "rx longer err\n");
  606. ether->stats.rx_over_errors++;
  607. }
  608. }
  609. rxbd->sl = RX_OWEN_DMA;
  610. rxbd->reserved = 0x0;
  611. if (++ether->cur_rx >= RX_DESC_SIZE)
  612. ether->cur_rx = 0;
  613. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  614. } while (1);
  615. }
  616. static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
  617. {
  618. struct net_device *dev;
  619. struct w90p910_ether *ether;
  620. struct platform_device *pdev;
  621. unsigned int status;
  622. dev = dev_id;
  623. ether = netdev_priv(dev);
  624. pdev = ether->pdev;
  625. w90p910_get_and_clear_int(dev, &status);
  626. if (status & MISTA_RDU) {
  627. netdev_rx(dev);
  628. w90p910_trigger_rx(dev);
  629. return IRQ_HANDLED;
  630. } else if (status & MISTA_RXBERR) {
  631. dev_err(&pdev->dev, "emc rx bus error\n");
  632. w90p910_reset_mac(dev);
  633. }
  634. netdev_rx(dev);
  635. return IRQ_HANDLED;
  636. }
  637. static int w90p910_ether_open(struct net_device *dev)
  638. {
  639. struct w90p910_ether *ether;
  640. struct platform_device *pdev;
  641. ether = netdev_priv(dev);
  642. pdev = ether->pdev;
  643. w90p910_reset_mac(dev);
  644. w90p910_set_fifo_threshold(dev);
  645. w90p910_set_curdest(dev);
  646. w90p910_enable_cam(dev);
  647. w90p910_enable_cam_command(dev);
  648. w90p910_enable_mac_interrupt(dev);
  649. w90p910_set_global_maccmd(dev);
  650. w90p910_enable_rx(dev, 1);
  651. ether->rx_packets = 0x0;
  652. ether->rx_bytes = 0x0;
  653. if (request_irq(ether->txirq, w90p910_tx_interrupt,
  654. 0x0, pdev->name, dev)) {
  655. dev_err(&pdev->dev, "register irq tx failed\n");
  656. return -EAGAIN;
  657. }
  658. if (request_irq(ether->rxirq, w90p910_rx_interrupt,
  659. 0x0, pdev->name, dev)) {
  660. dev_err(&pdev->dev, "register irq rx failed\n");
  661. free_irq(ether->txirq, dev);
  662. return -EAGAIN;
  663. }
  664. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  665. netif_start_queue(dev);
  666. w90p910_trigger_rx(dev);
  667. dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
  668. return 0;
  669. }
  670. static void w90p910_ether_set_multicast_list(struct net_device *dev)
  671. {
  672. struct w90p910_ether *ether;
  673. unsigned int rx_mode;
  674. ether = netdev_priv(dev);
  675. if (dev->flags & IFF_PROMISC)
  676. rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  677. else if ((dev->flags & IFF_ALLMULTI) || dev->mc_list)
  678. rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  679. else
  680. rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
  681. __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
  682. }
  683. static int w90p910_ether_ioctl(struct net_device *dev,
  684. struct ifreq *ifr, int cmd)
  685. {
  686. struct w90p910_ether *ether = netdev_priv(dev);
  687. struct mii_ioctl_data *data = if_mii(ifr);
  688. return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
  689. }
  690. static void w90p910_get_drvinfo(struct net_device *dev,
  691. struct ethtool_drvinfo *info)
  692. {
  693. strcpy(info->driver, DRV_MODULE_NAME);
  694. strcpy(info->version, DRV_MODULE_VERSION);
  695. }
  696. static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  697. {
  698. struct w90p910_ether *ether = netdev_priv(dev);
  699. return mii_ethtool_gset(&ether->mii, cmd);
  700. }
  701. static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  702. {
  703. struct w90p910_ether *ether = netdev_priv(dev);
  704. return mii_ethtool_sset(&ether->mii, cmd);
  705. }
  706. static int w90p910_nway_reset(struct net_device *dev)
  707. {
  708. struct w90p910_ether *ether = netdev_priv(dev);
  709. return mii_nway_restart(&ether->mii);
  710. }
  711. static u32 w90p910_get_link(struct net_device *dev)
  712. {
  713. struct w90p910_ether *ether = netdev_priv(dev);
  714. return mii_link_ok(&ether->mii);
  715. }
  716. static const struct ethtool_ops w90p910_ether_ethtool_ops = {
  717. .get_settings = w90p910_get_settings,
  718. .set_settings = w90p910_set_settings,
  719. .get_drvinfo = w90p910_get_drvinfo,
  720. .nway_reset = w90p910_nway_reset,
  721. .get_link = w90p910_get_link,
  722. };
  723. static const struct net_device_ops w90p910_ether_netdev_ops = {
  724. .ndo_open = w90p910_ether_open,
  725. .ndo_stop = w90p910_ether_close,
  726. .ndo_start_xmit = w90p910_ether_start_xmit,
  727. .ndo_get_stats = w90p910_ether_stats,
  728. .ndo_set_multicast_list = w90p910_ether_set_multicast_list,
  729. .ndo_set_mac_address = w90p910_set_mac_address,
  730. .ndo_do_ioctl = w90p910_ether_ioctl,
  731. .ndo_validate_addr = eth_validate_addr,
  732. .ndo_change_mtu = eth_change_mtu,
  733. };
  734. static void __init get_mac_address(struct net_device *dev)
  735. {
  736. struct w90p910_ether *ether = netdev_priv(dev);
  737. struct platform_device *pdev;
  738. char addr[6];
  739. pdev = ether->pdev;
  740. addr[0] = 0x00;
  741. addr[1] = 0x02;
  742. addr[2] = 0xac;
  743. addr[3] = 0x55;
  744. addr[4] = 0x88;
  745. addr[5] = 0xa8;
  746. if (is_valid_ether_addr(addr))
  747. memcpy(dev->dev_addr, &addr, 0x06);
  748. else
  749. dev_err(&pdev->dev, "invalid mac address\n");
  750. }
  751. static int w90p910_ether_setup(struct net_device *dev)
  752. {
  753. struct w90p910_ether *ether = netdev_priv(dev);
  754. ether_setup(dev);
  755. dev->netdev_ops = &w90p910_ether_netdev_ops;
  756. dev->ethtool_ops = &w90p910_ether_ethtool_ops;
  757. dev->tx_queue_len = 16;
  758. dev->dma = 0x0;
  759. dev->watchdog_timeo = TX_TIMEOUT;
  760. get_mac_address(dev);
  761. ether->cur_tx = 0x0;
  762. ether->cur_rx = 0x0;
  763. ether->finish_tx = 0x0;
  764. ether->linkflag = 0x0;
  765. ether->mii.phy_id = 0x01;
  766. ether->mii.phy_id_mask = 0x1f;
  767. ether->mii.reg_num_mask = 0x1f;
  768. ether->mii.dev = dev;
  769. ether->mii.mdio_read = w90p910_mdio_read;
  770. ether->mii.mdio_write = w90p910_mdio_write;
  771. setup_timer(&ether->check_timer, w90p910_check_link,
  772. (unsigned long)dev);
  773. return 0;
  774. }
  775. static int __devinit w90p910_ether_probe(struct platform_device *pdev)
  776. {
  777. struct w90p910_ether *ether;
  778. struct net_device *dev;
  779. int error;
  780. dev = alloc_etherdev(sizeof(struct w90p910_ether));
  781. if (!dev)
  782. return -ENOMEM;
  783. ether = netdev_priv(dev);
  784. ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  785. if (ether->res == NULL) {
  786. dev_err(&pdev->dev, "failed to get I/O memory\n");
  787. error = -ENXIO;
  788. goto failed_free;
  789. }
  790. if (!request_mem_region(ether->res->start,
  791. resource_size(ether->res), pdev->name)) {
  792. dev_err(&pdev->dev, "failed to request I/O memory\n");
  793. error = -EBUSY;
  794. goto failed_free;
  795. }
  796. ether->reg = ioremap(ether->res->start, resource_size(ether->res));
  797. if (ether->reg == NULL) {
  798. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  799. error = -ENXIO;
  800. goto failed_free_mem;
  801. }
  802. ether->txirq = platform_get_irq(pdev, 0);
  803. if (ether->txirq < 0) {
  804. dev_err(&pdev->dev, "failed to get ether tx irq\n");
  805. error = -ENXIO;
  806. goto failed_free_io;
  807. }
  808. ether->rxirq = platform_get_irq(pdev, 1);
  809. if (ether->rxirq < 0) {
  810. dev_err(&pdev->dev, "failed to get ether rx irq\n");
  811. error = -ENXIO;
  812. goto failed_free_txirq;
  813. }
  814. platform_set_drvdata(pdev, dev);
  815. ether->clk = clk_get(&pdev->dev, NULL);
  816. if (IS_ERR(ether->clk)) {
  817. dev_err(&pdev->dev, "failed to get ether clock\n");
  818. error = PTR_ERR(ether->clk);
  819. goto failed_free_rxirq;
  820. }
  821. ether->rmiiclk = clk_get(&pdev->dev, "RMII");
  822. if (IS_ERR(ether->rmiiclk)) {
  823. dev_err(&pdev->dev, "failed to get ether clock\n");
  824. error = PTR_ERR(ether->rmiiclk);
  825. goto failed_put_clk;
  826. }
  827. ether->pdev = pdev;
  828. w90p910_ether_setup(dev);
  829. error = register_netdev(dev);
  830. if (error != 0) {
  831. dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n");
  832. error = -ENODEV;
  833. goto failed_put_rmiiclk;
  834. }
  835. return 0;
  836. failed_put_rmiiclk:
  837. clk_put(ether->rmiiclk);
  838. failed_put_clk:
  839. clk_put(ether->clk);
  840. failed_free_rxirq:
  841. free_irq(ether->rxirq, pdev);
  842. platform_set_drvdata(pdev, NULL);
  843. failed_free_txirq:
  844. free_irq(ether->txirq, pdev);
  845. failed_free_io:
  846. iounmap(ether->reg);
  847. failed_free_mem:
  848. release_mem_region(ether->res->start, resource_size(ether->res));
  849. failed_free:
  850. free_netdev(dev);
  851. return error;
  852. }
  853. static int __devexit w90p910_ether_remove(struct platform_device *pdev)
  854. {
  855. struct net_device *dev = platform_get_drvdata(pdev);
  856. struct w90p910_ether *ether = netdev_priv(dev);
  857. unregister_netdev(dev);
  858. clk_put(ether->rmiiclk);
  859. clk_put(ether->clk);
  860. iounmap(ether->reg);
  861. release_mem_region(ether->res->start, resource_size(ether->res));
  862. free_irq(ether->txirq, dev);
  863. free_irq(ether->rxirq, dev);
  864. del_timer_sync(&ether->check_timer);
  865. platform_set_drvdata(pdev, NULL);
  866. free_netdev(dev);
  867. return 0;
  868. }
  869. static struct platform_driver w90p910_ether_driver = {
  870. .probe = w90p910_ether_probe,
  871. .remove = __devexit_p(w90p910_ether_remove),
  872. .driver = {
  873. .name = "nuc900-emc",
  874. .owner = THIS_MODULE,
  875. },
  876. };
  877. static int __init w90p910_ether_init(void)
  878. {
  879. return platform_driver_register(&w90p910_ether_driver);
  880. }
  881. static void __exit w90p910_ether_exit(void)
  882. {
  883. platform_driver_unregister(&w90p910_ether_driver);
  884. }
  885. module_init(w90p910_ether_init);
  886. module_exit(w90p910_ether_exit);
  887. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  888. MODULE_DESCRIPTION("w90p910 MAC driver!");
  889. MODULE_LICENSE("GPL");
  890. MODULE_ALIAS("platform:nuc900-emc");