sdhci-of.c 8.0 KB

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  1. /*
  2. * OpenFirmware bindings for Secure Digital Host Controller Interface.
  3. *
  4. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  5. * Copyright (c) 2009 MontaVista Software, Inc.
  6. *
  7. * Authors: Xiaobo Xie <X.Xie@freescale.com>
  8. * Anton Vorontsov <avorontsov@ru.mvista.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or (at
  13. * your option) any later version.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/io.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/delay.h>
  20. #include <linux/of.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/mmc/host.h>
  23. #include <asm/machdep.h>
  24. #include "sdhci.h"
  25. struct sdhci_of_data {
  26. unsigned int quirks;
  27. struct sdhci_ops ops;
  28. };
  29. struct sdhci_of_host {
  30. unsigned int clock;
  31. u16 xfer_mode_shadow;
  32. };
  33. /*
  34. * Ops and quirks for the Freescale eSDHC controller.
  35. */
  36. #define ESDHC_DMA_SYSCTL 0x40c
  37. #define ESDHC_DMA_SNOOP 0x00000040
  38. #define ESDHC_SYSTEM_CONTROL 0x2c
  39. #define ESDHC_CLOCK_MASK 0x0000fff0
  40. #define ESDHC_PREDIV_SHIFT 8
  41. #define ESDHC_DIVIDER_SHIFT 4
  42. #define ESDHC_CLOCK_PEREN 0x00000004
  43. #define ESDHC_CLOCK_HCKEN 0x00000002
  44. #define ESDHC_CLOCK_IPGEN 0x00000001
  45. #define ESDHC_HOST_CONTROL_RES 0x05
  46. static u32 esdhc_readl(struct sdhci_host *host, int reg)
  47. {
  48. return in_be32(host->ioaddr + reg);
  49. }
  50. static u16 esdhc_readw(struct sdhci_host *host, int reg)
  51. {
  52. u16 ret;
  53. if (unlikely(reg == SDHCI_HOST_VERSION))
  54. ret = in_be16(host->ioaddr + reg);
  55. else
  56. ret = in_be16(host->ioaddr + (reg ^ 0x2));
  57. return ret;
  58. }
  59. static u8 esdhc_readb(struct sdhci_host *host, int reg)
  60. {
  61. return in_8(host->ioaddr + (reg ^ 0x3));
  62. }
  63. static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
  64. {
  65. out_be32(host->ioaddr + reg, val);
  66. }
  67. static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
  68. {
  69. struct sdhci_of_host *of_host = sdhci_priv(host);
  70. int base = reg & ~0x3;
  71. int shift = (reg & 0x2) * 8;
  72. switch (reg) {
  73. case SDHCI_TRANSFER_MODE:
  74. /*
  75. * Postpone this write, we must do it together with a
  76. * command write that is down below.
  77. */
  78. of_host->xfer_mode_shadow = val;
  79. return;
  80. case SDHCI_COMMAND:
  81. esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow,
  82. SDHCI_TRANSFER_MODE);
  83. return;
  84. case SDHCI_BLOCK_SIZE:
  85. /*
  86. * Two last DMA bits are reserved, and first one is used for
  87. * non-standard blksz of 4096 bytes that we don't support
  88. * yet. So clear the DMA boundary bits.
  89. */
  90. val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  91. /* fall through */
  92. }
  93. clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
  94. }
  95. static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
  96. {
  97. int base = reg & ~0x3;
  98. int shift = (reg & 0x3) * 8;
  99. /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
  100. if (reg == SDHCI_HOST_CONTROL)
  101. val &= ~ESDHC_HOST_CONTROL_RES;
  102. clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
  103. }
  104. static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
  105. {
  106. int pre_div = 2;
  107. int div = 1;
  108. clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
  109. ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
  110. if (clock == 0)
  111. goto out;
  112. while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
  113. pre_div *= 2;
  114. while (host->max_clk / pre_div / div > clock && div < 16)
  115. div++;
  116. dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
  117. clock, host->max_clk / pre_div / div);
  118. pre_div >>= 1;
  119. div--;
  120. setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
  121. ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
  122. div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
  123. mdelay(100);
  124. out:
  125. host->clock = clock;
  126. }
  127. static int esdhc_enable_dma(struct sdhci_host *host)
  128. {
  129. setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
  130. return 0;
  131. }
  132. static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
  133. {
  134. struct sdhci_of_host *of_host = sdhci_priv(host);
  135. return of_host->clock;
  136. }
  137. static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
  138. {
  139. struct sdhci_of_host *of_host = sdhci_priv(host);
  140. return of_host->clock / 256 / 16;
  141. }
  142. static struct sdhci_of_data sdhci_esdhc = {
  143. .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
  144. SDHCI_QUIRK_BROKEN_CARD_DETECTION |
  145. SDHCI_QUIRK_NO_BUSY_IRQ |
  146. SDHCI_QUIRK_NONSTANDARD_CLOCK |
  147. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  148. SDHCI_QUIRK_PIO_NEEDS_DELAY |
  149. SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
  150. SDHCI_QUIRK_NO_CARD_NO_RESET,
  151. .ops = {
  152. .readl = esdhc_readl,
  153. .readw = esdhc_readw,
  154. .readb = esdhc_readb,
  155. .writel = esdhc_writel,
  156. .writew = esdhc_writew,
  157. .writeb = esdhc_writeb,
  158. .set_clock = esdhc_set_clock,
  159. .enable_dma = esdhc_enable_dma,
  160. .get_max_clock = esdhc_get_max_clock,
  161. .get_min_clock = esdhc_get_min_clock,
  162. },
  163. };
  164. #ifdef CONFIG_PM
  165. static int sdhci_of_suspend(struct of_device *ofdev, pm_message_t state)
  166. {
  167. struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
  168. return mmc_suspend_host(host->mmc, state);
  169. }
  170. static int sdhci_of_resume(struct of_device *ofdev)
  171. {
  172. struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
  173. return mmc_resume_host(host->mmc);
  174. }
  175. #else
  176. #define sdhci_of_suspend NULL
  177. #define sdhci_of_resume NULL
  178. #endif
  179. static bool __devinit sdhci_of_wp_inverted(struct device_node *np)
  180. {
  181. if (of_get_property(np, "sdhci,wp-inverted", NULL))
  182. return true;
  183. /* Old device trees don't have the wp-inverted property. */
  184. return machine_is(mpc837x_rdb) || machine_is(mpc837x_mds);
  185. }
  186. static int __devinit sdhci_of_probe(struct of_device *ofdev,
  187. const struct of_device_id *match)
  188. {
  189. struct device_node *np = ofdev->node;
  190. struct sdhci_of_data *sdhci_of_data = match->data;
  191. struct sdhci_host *host;
  192. struct sdhci_of_host *of_host;
  193. const u32 *clk;
  194. int size;
  195. int ret;
  196. if (!of_device_is_available(np))
  197. return -ENODEV;
  198. host = sdhci_alloc_host(&ofdev->dev, sizeof(*of_host));
  199. if (IS_ERR(host))
  200. return -ENOMEM;
  201. of_host = sdhci_priv(host);
  202. dev_set_drvdata(&ofdev->dev, host);
  203. host->ioaddr = of_iomap(np, 0);
  204. if (!host->ioaddr) {
  205. ret = -ENOMEM;
  206. goto err_addr_map;
  207. }
  208. host->irq = irq_of_parse_and_map(np, 0);
  209. if (!host->irq) {
  210. ret = -EINVAL;
  211. goto err_no_irq;
  212. }
  213. host->hw_name = dev_name(&ofdev->dev);
  214. if (sdhci_of_data) {
  215. host->quirks = sdhci_of_data->quirks;
  216. host->ops = &sdhci_of_data->ops;
  217. }
  218. if (of_get_property(np, "sdhci,1-bit-only", NULL))
  219. host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
  220. if (sdhci_of_wp_inverted(np))
  221. host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
  222. clk = of_get_property(np, "clock-frequency", &size);
  223. if (clk && size == sizeof(*clk) && *clk)
  224. of_host->clock = *clk;
  225. ret = sdhci_add_host(host);
  226. if (ret)
  227. goto err_add_host;
  228. return 0;
  229. err_add_host:
  230. irq_dispose_mapping(host->irq);
  231. err_no_irq:
  232. iounmap(host->ioaddr);
  233. err_addr_map:
  234. sdhci_free_host(host);
  235. return ret;
  236. }
  237. static int __devexit sdhci_of_remove(struct of_device *ofdev)
  238. {
  239. struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
  240. sdhci_remove_host(host, 0);
  241. sdhci_free_host(host);
  242. irq_dispose_mapping(host->irq);
  243. iounmap(host->ioaddr);
  244. return 0;
  245. }
  246. static const struct of_device_id sdhci_of_match[] = {
  247. { .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, },
  248. { .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, },
  249. { .compatible = "fsl,esdhc", .data = &sdhci_esdhc, },
  250. { .compatible = "generic-sdhci", },
  251. {},
  252. };
  253. MODULE_DEVICE_TABLE(of, sdhci_of_match);
  254. static struct of_platform_driver sdhci_of_driver = {
  255. .driver.name = "sdhci-of",
  256. .match_table = sdhci_of_match,
  257. .probe = sdhci_of_probe,
  258. .remove = __devexit_p(sdhci_of_remove),
  259. .suspend = sdhci_of_suspend,
  260. .resume = sdhci_of_resume,
  261. };
  262. static int __init sdhci_of_init(void)
  263. {
  264. return of_register_platform_driver(&sdhci_of_driver);
  265. }
  266. module_init(sdhci_of_init);
  267. static void __exit sdhci_of_exit(void)
  268. {
  269. of_unregister_platform_driver(&sdhci_of_driver);
  270. }
  271. module_exit(sdhci_of_exit);
  272. MODULE_DESCRIPTION("Secure Digital Host Controller Interface OF driver");
  273. MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
  274. "Anton Vorontsov <avorontsov@ru.mvista.com>");
  275. MODULE_LICENSE("GPL");