cputable.c 58 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. struct cpu_spec* cur_cpu_spec = NULL;
  22. EXPORT_SYMBOL(cur_cpu_spec);
  23. /* The platform string corresponding to the real PVR */
  24. const char *powerpc_base_platform;
  25. /* NOTE:
  26. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  27. * the responsibility of the appropriate CPU save/restore functions to
  28. * eventually copy these settings over. Those save/restore aren't yet
  29. * part of the cputable though. That has to be fixed for both ppc32
  30. * and ppc64
  31. */
  32. #ifdef CONFIG_PPC32
  33. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  46. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  47. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  48. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  54. #endif /* CONFIG_PPC32 */
  55. #ifdef CONFIG_PPC64
  56. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  57. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  58. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  59. extern void __restore_cpu_pa6t(void);
  60. extern void __restore_cpu_ppc970(void);
  61. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  62. extern void __restore_cpu_power7(void);
  63. #endif /* CONFIG_PPC64 */
  64. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  65. * ones as well...
  66. */
  67. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  68. PPC_FEATURE_HAS_MMU)
  69. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  70. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  71. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  72. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  73. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  74. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  75. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  76. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  77. PPC_FEATURE_TRUE_LE | \
  78. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  79. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  80. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  81. PPC_FEATURE_TRUE_LE | \
  82. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  83. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  84. PPC_FEATURE_TRUE_LE | \
  85. PPC_FEATURE_HAS_ALTIVEC_COMP)
  86. #ifdef CONFIG_PPC_BOOK3E_64
  87. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  88. #else
  89. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  90. PPC_FEATURE_BOOKE)
  91. #endif
  92. static struct cpu_spec __initdata cpu_specs[] = {
  93. #ifdef CONFIG_PPC_BOOK3S_64
  94. { /* Power3 */
  95. .pvr_mask = 0xffff0000,
  96. .pvr_value = 0x00400000,
  97. .cpu_name = "POWER3 (630)",
  98. .cpu_features = CPU_FTRS_POWER3,
  99. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  100. .mmu_features = MMU_FTR_HPTE_TABLE,
  101. .icache_bsize = 128,
  102. .dcache_bsize = 128,
  103. .num_pmcs = 8,
  104. .pmc_type = PPC_PMC_IBM,
  105. .oprofile_cpu_type = "ppc64/power3",
  106. .oprofile_type = PPC_OPROFILE_RS64,
  107. .machine_check = machine_check_generic,
  108. .platform = "power3",
  109. },
  110. { /* Power3+ */
  111. .pvr_mask = 0xffff0000,
  112. .pvr_value = 0x00410000,
  113. .cpu_name = "POWER3 (630+)",
  114. .cpu_features = CPU_FTRS_POWER3,
  115. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  116. .mmu_features = MMU_FTR_HPTE_TABLE,
  117. .icache_bsize = 128,
  118. .dcache_bsize = 128,
  119. .num_pmcs = 8,
  120. .pmc_type = PPC_PMC_IBM,
  121. .oprofile_cpu_type = "ppc64/power3",
  122. .oprofile_type = PPC_OPROFILE_RS64,
  123. .machine_check = machine_check_generic,
  124. .platform = "power3",
  125. },
  126. { /* Northstar */
  127. .pvr_mask = 0xffff0000,
  128. .pvr_value = 0x00330000,
  129. .cpu_name = "RS64-II (northstar)",
  130. .cpu_features = CPU_FTRS_RS64,
  131. .cpu_user_features = COMMON_USER_PPC64,
  132. .mmu_features = MMU_FTR_HPTE_TABLE,
  133. .icache_bsize = 128,
  134. .dcache_bsize = 128,
  135. .num_pmcs = 8,
  136. .pmc_type = PPC_PMC_IBM,
  137. .oprofile_cpu_type = "ppc64/rs64",
  138. .oprofile_type = PPC_OPROFILE_RS64,
  139. .machine_check = machine_check_generic,
  140. .platform = "rs64",
  141. },
  142. { /* Pulsar */
  143. .pvr_mask = 0xffff0000,
  144. .pvr_value = 0x00340000,
  145. .cpu_name = "RS64-III (pulsar)",
  146. .cpu_features = CPU_FTRS_RS64,
  147. .cpu_user_features = COMMON_USER_PPC64,
  148. .mmu_features = MMU_FTR_HPTE_TABLE,
  149. .icache_bsize = 128,
  150. .dcache_bsize = 128,
  151. .num_pmcs = 8,
  152. .pmc_type = PPC_PMC_IBM,
  153. .oprofile_cpu_type = "ppc64/rs64",
  154. .oprofile_type = PPC_OPROFILE_RS64,
  155. .machine_check = machine_check_generic,
  156. .platform = "rs64",
  157. },
  158. { /* I-star */
  159. .pvr_mask = 0xffff0000,
  160. .pvr_value = 0x00360000,
  161. .cpu_name = "RS64-III (icestar)",
  162. .cpu_features = CPU_FTRS_RS64,
  163. .cpu_user_features = COMMON_USER_PPC64,
  164. .mmu_features = MMU_FTR_HPTE_TABLE,
  165. .icache_bsize = 128,
  166. .dcache_bsize = 128,
  167. .num_pmcs = 8,
  168. .pmc_type = PPC_PMC_IBM,
  169. .oprofile_cpu_type = "ppc64/rs64",
  170. .oprofile_type = PPC_OPROFILE_RS64,
  171. .machine_check = machine_check_generic,
  172. .platform = "rs64",
  173. },
  174. { /* S-star */
  175. .pvr_mask = 0xffff0000,
  176. .pvr_value = 0x00370000,
  177. .cpu_name = "RS64-IV (sstar)",
  178. .cpu_features = CPU_FTRS_RS64,
  179. .cpu_user_features = COMMON_USER_PPC64,
  180. .mmu_features = MMU_FTR_HPTE_TABLE,
  181. .icache_bsize = 128,
  182. .dcache_bsize = 128,
  183. .num_pmcs = 8,
  184. .pmc_type = PPC_PMC_IBM,
  185. .oprofile_cpu_type = "ppc64/rs64",
  186. .oprofile_type = PPC_OPROFILE_RS64,
  187. .machine_check = machine_check_generic,
  188. .platform = "rs64",
  189. },
  190. { /* Power4 */
  191. .pvr_mask = 0xffff0000,
  192. .pvr_value = 0x00350000,
  193. .cpu_name = "POWER4 (gp)",
  194. .cpu_features = CPU_FTRS_POWER4,
  195. .cpu_user_features = COMMON_USER_POWER4,
  196. .mmu_features = MMU_FTR_HPTE_TABLE,
  197. .icache_bsize = 128,
  198. .dcache_bsize = 128,
  199. .num_pmcs = 8,
  200. .pmc_type = PPC_PMC_IBM,
  201. .oprofile_cpu_type = "ppc64/power4",
  202. .oprofile_type = PPC_OPROFILE_POWER4,
  203. .machine_check = machine_check_generic,
  204. .platform = "power4",
  205. },
  206. { /* Power4+ */
  207. .pvr_mask = 0xffff0000,
  208. .pvr_value = 0x00380000,
  209. .cpu_name = "POWER4+ (gq)",
  210. .cpu_features = CPU_FTRS_POWER4,
  211. .cpu_user_features = COMMON_USER_POWER4,
  212. .mmu_features = MMU_FTR_HPTE_TABLE,
  213. .icache_bsize = 128,
  214. .dcache_bsize = 128,
  215. .num_pmcs = 8,
  216. .pmc_type = PPC_PMC_IBM,
  217. .oprofile_cpu_type = "ppc64/power4",
  218. .oprofile_type = PPC_OPROFILE_POWER4,
  219. .machine_check = machine_check_generic,
  220. .platform = "power4",
  221. },
  222. { /* PPC970 */
  223. .pvr_mask = 0xffff0000,
  224. .pvr_value = 0x00390000,
  225. .cpu_name = "PPC970",
  226. .cpu_features = CPU_FTRS_PPC970,
  227. .cpu_user_features = COMMON_USER_POWER4 |
  228. PPC_FEATURE_HAS_ALTIVEC_COMP,
  229. .mmu_features = MMU_FTR_HPTE_TABLE,
  230. .icache_bsize = 128,
  231. .dcache_bsize = 128,
  232. .num_pmcs = 8,
  233. .pmc_type = PPC_PMC_IBM,
  234. .cpu_setup = __setup_cpu_ppc970,
  235. .cpu_restore = __restore_cpu_ppc970,
  236. .oprofile_cpu_type = "ppc64/970",
  237. .oprofile_type = PPC_OPROFILE_POWER4,
  238. .machine_check = machine_check_generic,
  239. .platform = "ppc970",
  240. },
  241. { /* PPC970FX */
  242. .pvr_mask = 0xffff0000,
  243. .pvr_value = 0x003c0000,
  244. .cpu_name = "PPC970FX",
  245. .cpu_features = CPU_FTRS_PPC970,
  246. .cpu_user_features = COMMON_USER_POWER4 |
  247. PPC_FEATURE_HAS_ALTIVEC_COMP,
  248. .mmu_features = MMU_FTR_HPTE_TABLE,
  249. .icache_bsize = 128,
  250. .dcache_bsize = 128,
  251. .num_pmcs = 8,
  252. .pmc_type = PPC_PMC_IBM,
  253. .cpu_setup = __setup_cpu_ppc970,
  254. .cpu_restore = __restore_cpu_ppc970,
  255. .oprofile_cpu_type = "ppc64/970",
  256. .oprofile_type = PPC_OPROFILE_POWER4,
  257. .machine_check = machine_check_generic,
  258. .platform = "ppc970",
  259. },
  260. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  261. .pvr_mask = 0xffffffff,
  262. .pvr_value = 0x00440100,
  263. .cpu_name = "PPC970MP",
  264. .cpu_features = CPU_FTRS_PPC970,
  265. .cpu_user_features = COMMON_USER_POWER4 |
  266. PPC_FEATURE_HAS_ALTIVEC_COMP,
  267. .mmu_features = MMU_FTR_HPTE_TABLE,
  268. .icache_bsize = 128,
  269. .dcache_bsize = 128,
  270. .num_pmcs = 8,
  271. .pmc_type = PPC_PMC_IBM,
  272. .cpu_setup = __setup_cpu_ppc970,
  273. .cpu_restore = __restore_cpu_ppc970,
  274. .oprofile_cpu_type = "ppc64/970MP",
  275. .oprofile_type = PPC_OPROFILE_POWER4,
  276. .machine_check = machine_check_generic,
  277. .platform = "ppc970",
  278. },
  279. { /* PPC970MP */
  280. .pvr_mask = 0xffff0000,
  281. .pvr_value = 0x00440000,
  282. .cpu_name = "PPC970MP",
  283. .cpu_features = CPU_FTRS_PPC970,
  284. .cpu_user_features = COMMON_USER_POWER4 |
  285. PPC_FEATURE_HAS_ALTIVEC_COMP,
  286. .mmu_features = MMU_FTR_HPTE_TABLE,
  287. .icache_bsize = 128,
  288. .dcache_bsize = 128,
  289. .num_pmcs = 8,
  290. .pmc_type = PPC_PMC_IBM,
  291. .cpu_setup = __setup_cpu_ppc970MP,
  292. .cpu_restore = __restore_cpu_ppc970,
  293. .oprofile_cpu_type = "ppc64/970MP",
  294. .oprofile_type = PPC_OPROFILE_POWER4,
  295. .machine_check = machine_check_generic,
  296. .platform = "ppc970",
  297. },
  298. { /* PPC970GX */
  299. .pvr_mask = 0xffff0000,
  300. .pvr_value = 0x00450000,
  301. .cpu_name = "PPC970GX",
  302. .cpu_features = CPU_FTRS_PPC970,
  303. .cpu_user_features = COMMON_USER_POWER4 |
  304. PPC_FEATURE_HAS_ALTIVEC_COMP,
  305. .mmu_features = MMU_FTR_HPTE_TABLE,
  306. .icache_bsize = 128,
  307. .dcache_bsize = 128,
  308. .num_pmcs = 8,
  309. .pmc_type = PPC_PMC_IBM,
  310. .cpu_setup = __setup_cpu_ppc970,
  311. .oprofile_cpu_type = "ppc64/970",
  312. .oprofile_type = PPC_OPROFILE_POWER4,
  313. .machine_check = machine_check_generic,
  314. .platform = "ppc970",
  315. },
  316. { /* Power5 GR */
  317. .pvr_mask = 0xffff0000,
  318. .pvr_value = 0x003a0000,
  319. .cpu_name = "POWER5 (gr)",
  320. .cpu_features = CPU_FTRS_POWER5,
  321. .cpu_user_features = COMMON_USER_POWER5,
  322. .mmu_features = MMU_FTR_HPTE_TABLE,
  323. .icache_bsize = 128,
  324. .dcache_bsize = 128,
  325. .num_pmcs = 6,
  326. .pmc_type = PPC_PMC_IBM,
  327. .oprofile_cpu_type = "ppc64/power5",
  328. .oprofile_type = PPC_OPROFILE_POWER4,
  329. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  330. * and above but only works on POWER5 and above
  331. */
  332. .oprofile_mmcra_sihv = MMCRA_SIHV,
  333. .oprofile_mmcra_sipr = MMCRA_SIPR,
  334. .machine_check = machine_check_generic,
  335. .platform = "power5",
  336. },
  337. { /* Power5++ */
  338. .pvr_mask = 0xffffff00,
  339. .pvr_value = 0x003b0300,
  340. .cpu_name = "POWER5+ (gs)",
  341. .cpu_features = CPU_FTRS_POWER5,
  342. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  343. .mmu_features = MMU_FTR_HPTE_TABLE,
  344. .icache_bsize = 128,
  345. .dcache_bsize = 128,
  346. .num_pmcs = 6,
  347. .oprofile_cpu_type = "ppc64/power5++",
  348. .oprofile_type = PPC_OPROFILE_POWER4,
  349. .oprofile_mmcra_sihv = MMCRA_SIHV,
  350. .oprofile_mmcra_sipr = MMCRA_SIPR,
  351. .machine_check = machine_check_generic,
  352. .platform = "power5+",
  353. },
  354. { /* Power5 GS */
  355. .pvr_mask = 0xffff0000,
  356. .pvr_value = 0x003b0000,
  357. .cpu_name = "POWER5+ (gs)",
  358. .cpu_features = CPU_FTRS_POWER5,
  359. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  360. .mmu_features = MMU_FTR_HPTE_TABLE,
  361. .icache_bsize = 128,
  362. .dcache_bsize = 128,
  363. .num_pmcs = 6,
  364. .pmc_type = PPC_PMC_IBM,
  365. .oprofile_cpu_type = "ppc64/power5+",
  366. .oprofile_type = PPC_OPROFILE_POWER4,
  367. .oprofile_mmcra_sihv = MMCRA_SIHV,
  368. .oprofile_mmcra_sipr = MMCRA_SIPR,
  369. .machine_check = machine_check_generic,
  370. .platform = "power5+",
  371. },
  372. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  373. .pvr_mask = 0xffffffff,
  374. .pvr_value = 0x0f000001,
  375. .cpu_name = "POWER5+",
  376. .cpu_features = CPU_FTRS_POWER5,
  377. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  378. .mmu_features = MMU_FTR_HPTE_TABLE,
  379. .icache_bsize = 128,
  380. .dcache_bsize = 128,
  381. .machine_check = machine_check_generic,
  382. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  383. .oprofile_type = PPC_OPROFILE_POWER4,
  384. .platform = "power5+",
  385. },
  386. { /* Power6 */
  387. .pvr_mask = 0xffff0000,
  388. .pvr_value = 0x003e0000,
  389. .cpu_name = "POWER6 (raw)",
  390. .cpu_features = CPU_FTRS_POWER6,
  391. .cpu_user_features = COMMON_USER_POWER6 |
  392. PPC_FEATURE_POWER6_EXT,
  393. .mmu_features = MMU_FTR_HPTE_TABLE,
  394. .icache_bsize = 128,
  395. .dcache_bsize = 128,
  396. .num_pmcs = 6,
  397. .pmc_type = PPC_PMC_IBM,
  398. .oprofile_cpu_type = "ppc64/power6",
  399. .oprofile_type = PPC_OPROFILE_POWER4,
  400. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  401. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  402. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  403. POWER6_MMCRA_OTHER,
  404. .machine_check = machine_check_generic,
  405. .platform = "power6x",
  406. },
  407. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  408. .pvr_mask = 0xffffffff,
  409. .pvr_value = 0x0f000002,
  410. .cpu_name = "POWER6 (architected)",
  411. .cpu_features = CPU_FTRS_POWER6,
  412. .cpu_user_features = COMMON_USER_POWER6,
  413. .mmu_features = MMU_FTR_HPTE_TABLE,
  414. .icache_bsize = 128,
  415. .dcache_bsize = 128,
  416. .machine_check = machine_check_generic,
  417. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  418. .oprofile_type = PPC_OPROFILE_POWER4,
  419. .platform = "power6",
  420. },
  421. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  422. .pvr_mask = 0xffffffff,
  423. .pvr_value = 0x0f000003,
  424. .cpu_name = "POWER7 (architected)",
  425. .cpu_features = CPU_FTRS_POWER7,
  426. .cpu_user_features = COMMON_USER_POWER7,
  427. .mmu_features = MMU_FTR_HPTE_TABLE |
  428. MMU_FTR_TLBIE_206,
  429. .icache_bsize = 128,
  430. .dcache_bsize = 128,
  431. .machine_check = machine_check_generic,
  432. .oprofile_type = PPC_OPROFILE_POWER4,
  433. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  434. .platform = "power7",
  435. },
  436. { /* Power7 */
  437. .pvr_mask = 0xffff0000,
  438. .pvr_value = 0x003f0000,
  439. .cpu_name = "POWER7 (raw)",
  440. .cpu_features = CPU_FTRS_POWER7,
  441. .cpu_user_features = COMMON_USER_POWER7,
  442. .mmu_features = MMU_FTR_HPTE_TABLE |
  443. MMU_FTR_TLBIE_206,
  444. .icache_bsize = 128,
  445. .dcache_bsize = 128,
  446. .num_pmcs = 6,
  447. .pmc_type = PPC_PMC_IBM,
  448. .cpu_setup = __setup_cpu_power7,
  449. .cpu_restore = __restore_cpu_power7,
  450. .oprofile_cpu_type = "ppc64/power7",
  451. .oprofile_type = PPC_OPROFILE_POWER4,
  452. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  453. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  454. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  455. POWER6_MMCRA_OTHER,
  456. .platform = "power7",
  457. },
  458. { /* Cell Broadband Engine */
  459. .pvr_mask = 0xffff0000,
  460. .pvr_value = 0x00700000,
  461. .cpu_name = "Cell Broadband Engine",
  462. .cpu_features = CPU_FTRS_CELL,
  463. .cpu_user_features = COMMON_USER_PPC64 |
  464. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  465. PPC_FEATURE_SMT,
  466. .mmu_features = MMU_FTR_HPTE_TABLE,
  467. .icache_bsize = 128,
  468. .dcache_bsize = 128,
  469. .num_pmcs = 4,
  470. .pmc_type = PPC_PMC_IBM,
  471. .oprofile_cpu_type = "ppc64/cell-be",
  472. .oprofile_type = PPC_OPROFILE_CELL,
  473. .machine_check = machine_check_generic,
  474. .platform = "ppc-cell-be",
  475. },
  476. { /* PA Semi PA6T */
  477. .pvr_mask = 0x7fff0000,
  478. .pvr_value = 0x00900000,
  479. .cpu_name = "PA6T",
  480. .cpu_features = CPU_FTRS_PA6T,
  481. .cpu_user_features = COMMON_USER_PA6T,
  482. .mmu_features = MMU_FTR_HPTE_TABLE,
  483. .icache_bsize = 64,
  484. .dcache_bsize = 64,
  485. .num_pmcs = 6,
  486. .pmc_type = PPC_PMC_PA6T,
  487. .cpu_setup = __setup_cpu_pa6t,
  488. .cpu_restore = __restore_cpu_pa6t,
  489. .oprofile_cpu_type = "ppc64/pa6t",
  490. .oprofile_type = PPC_OPROFILE_PA6T,
  491. .machine_check = machine_check_generic,
  492. .platform = "pa6t",
  493. },
  494. { /* default match */
  495. .pvr_mask = 0x00000000,
  496. .pvr_value = 0x00000000,
  497. .cpu_name = "POWER4 (compatible)",
  498. .cpu_features = CPU_FTRS_COMPATIBLE,
  499. .cpu_user_features = COMMON_USER_PPC64,
  500. .mmu_features = MMU_FTR_HPTE_TABLE,
  501. .icache_bsize = 128,
  502. .dcache_bsize = 128,
  503. .num_pmcs = 6,
  504. .pmc_type = PPC_PMC_IBM,
  505. .machine_check = machine_check_generic,
  506. .platform = "power4",
  507. }
  508. #endif /* CONFIG_PPC_BOOK3S_64 */
  509. #ifdef CONFIG_PPC32
  510. #if CLASSIC_PPC
  511. { /* 601 */
  512. .pvr_mask = 0xffff0000,
  513. .pvr_value = 0x00010000,
  514. .cpu_name = "601",
  515. .cpu_features = CPU_FTRS_PPC601,
  516. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  517. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  518. .mmu_features = MMU_FTR_HPTE_TABLE,
  519. .icache_bsize = 32,
  520. .dcache_bsize = 32,
  521. .machine_check = machine_check_generic,
  522. .platform = "ppc601",
  523. },
  524. { /* 603 */
  525. .pvr_mask = 0xffff0000,
  526. .pvr_value = 0x00030000,
  527. .cpu_name = "603",
  528. .cpu_features = CPU_FTRS_603,
  529. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  530. .mmu_features = 0,
  531. .icache_bsize = 32,
  532. .dcache_bsize = 32,
  533. .cpu_setup = __setup_cpu_603,
  534. .machine_check = machine_check_generic,
  535. .platform = "ppc603",
  536. },
  537. { /* 603e */
  538. .pvr_mask = 0xffff0000,
  539. .pvr_value = 0x00060000,
  540. .cpu_name = "603e",
  541. .cpu_features = CPU_FTRS_603,
  542. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  543. .mmu_features = 0,
  544. .icache_bsize = 32,
  545. .dcache_bsize = 32,
  546. .cpu_setup = __setup_cpu_603,
  547. .machine_check = machine_check_generic,
  548. .platform = "ppc603",
  549. },
  550. { /* 603ev */
  551. .pvr_mask = 0xffff0000,
  552. .pvr_value = 0x00070000,
  553. .cpu_name = "603ev",
  554. .cpu_features = CPU_FTRS_603,
  555. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  556. .mmu_features = 0,
  557. .icache_bsize = 32,
  558. .dcache_bsize = 32,
  559. .cpu_setup = __setup_cpu_603,
  560. .machine_check = machine_check_generic,
  561. .platform = "ppc603",
  562. },
  563. { /* 604 */
  564. .pvr_mask = 0xffff0000,
  565. .pvr_value = 0x00040000,
  566. .cpu_name = "604",
  567. .cpu_features = CPU_FTRS_604,
  568. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  569. .mmu_features = MMU_FTR_HPTE_TABLE,
  570. .icache_bsize = 32,
  571. .dcache_bsize = 32,
  572. .num_pmcs = 2,
  573. .cpu_setup = __setup_cpu_604,
  574. .machine_check = machine_check_generic,
  575. .platform = "ppc604",
  576. },
  577. { /* 604e */
  578. .pvr_mask = 0xfffff000,
  579. .pvr_value = 0x00090000,
  580. .cpu_name = "604e",
  581. .cpu_features = CPU_FTRS_604,
  582. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  583. .mmu_features = MMU_FTR_HPTE_TABLE,
  584. .icache_bsize = 32,
  585. .dcache_bsize = 32,
  586. .num_pmcs = 4,
  587. .cpu_setup = __setup_cpu_604,
  588. .machine_check = machine_check_generic,
  589. .platform = "ppc604",
  590. },
  591. { /* 604r */
  592. .pvr_mask = 0xffff0000,
  593. .pvr_value = 0x00090000,
  594. .cpu_name = "604r",
  595. .cpu_features = CPU_FTRS_604,
  596. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  597. .mmu_features = MMU_FTR_HPTE_TABLE,
  598. .icache_bsize = 32,
  599. .dcache_bsize = 32,
  600. .num_pmcs = 4,
  601. .cpu_setup = __setup_cpu_604,
  602. .machine_check = machine_check_generic,
  603. .platform = "ppc604",
  604. },
  605. { /* 604ev */
  606. .pvr_mask = 0xffff0000,
  607. .pvr_value = 0x000a0000,
  608. .cpu_name = "604ev",
  609. .cpu_features = CPU_FTRS_604,
  610. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  611. .mmu_features = MMU_FTR_HPTE_TABLE,
  612. .icache_bsize = 32,
  613. .dcache_bsize = 32,
  614. .num_pmcs = 4,
  615. .cpu_setup = __setup_cpu_604,
  616. .machine_check = machine_check_generic,
  617. .platform = "ppc604",
  618. },
  619. { /* 740/750 (0x4202, don't support TAU ?) */
  620. .pvr_mask = 0xffffffff,
  621. .pvr_value = 0x00084202,
  622. .cpu_name = "740/750",
  623. .cpu_features = CPU_FTRS_740_NOTAU,
  624. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  625. .mmu_features = MMU_FTR_HPTE_TABLE,
  626. .icache_bsize = 32,
  627. .dcache_bsize = 32,
  628. .num_pmcs = 4,
  629. .cpu_setup = __setup_cpu_750,
  630. .machine_check = machine_check_generic,
  631. .platform = "ppc750",
  632. },
  633. { /* 750CX (80100 and 8010x?) */
  634. .pvr_mask = 0xfffffff0,
  635. .pvr_value = 0x00080100,
  636. .cpu_name = "750CX",
  637. .cpu_features = CPU_FTRS_750,
  638. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  639. .mmu_features = MMU_FTR_HPTE_TABLE,
  640. .icache_bsize = 32,
  641. .dcache_bsize = 32,
  642. .num_pmcs = 4,
  643. .cpu_setup = __setup_cpu_750cx,
  644. .machine_check = machine_check_generic,
  645. .platform = "ppc750",
  646. },
  647. { /* 750CX (82201 and 82202) */
  648. .pvr_mask = 0xfffffff0,
  649. .pvr_value = 0x00082200,
  650. .cpu_name = "750CX",
  651. .cpu_features = CPU_FTRS_750,
  652. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  653. .mmu_features = MMU_FTR_HPTE_TABLE,
  654. .icache_bsize = 32,
  655. .dcache_bsize = 32,
  656. .num_pmcs = 4,
  657. .pmc_type = PPC_PMC_IBM,
  658. .cpu_setup = __setup_cpu_750cx,
  659. .machine_check = machine_check_generic,
  660. .platform = "ppc750",
  661. },
  662. { /* 750CXe (82214) */
  663. .pvr_mask = 0xfffffff0,
  664. .pvr_value = 0x00082210,
  665. .cpu_name = "750CXe",
  666. .cpu_features = CPU_FTRS_750,
  667. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  668. .mmu_features = MMU_FTR_HPTE_TABLE,
  669. .icache_bsize = 32,
  670. .dcache_bsize = 32,
  671. .num_pmcs = 4,
  672. .pmc_type = PPC_PMC_IBM,
  673. .cpu_setup = __setup_cpu_750cx,
  674. .machine_check = machine_check_generic,
  675. .platform = "ppc750",
  676. },
  677. { /* 750CXe "Gekko" (83214) */
  678. .pvr_mask = 0xffffffff,
  679. .pvr_value = 0x00083214,
  680. .cpu_name = "750CXe",
  681. .cpu_features = CPU_FTRS_750,
  682. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  683. .mmu_features = MMU_FTR_HPTE_TABLE,
  684. .icache_bsize = 32,
  685. .dcache_bsize = 32,
  686. .num_pmcs = 4,
  687. .pmc_type = PPC_PMC_IBM,
  688. .cpu_setup = __setup_cpu_750cx,
  689. .machine_check = machine_check_generic,
  690. .platform = "ppc750",
  691. },
  692. { /* 750CL */
  693. .pvr_mask = 0xfffff0f0,
  694. .pvr_value = 0x00087010,
  695. .cpu_name = "750CL",
  696. .cpu_features = CPU_FTRS_750CL,
  697. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  698. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  699. .icache_bsize = 32,
  700. .dcache_bsize = 32,
  701. .num_pmcs = 4,
  702. .pmc_type = PPC_PMC_IBM,
  703. .cpu_setup = __setup_cpu_750,
  704. .machine_check = machine_check_generic,
  705. .platform = "ppc750",
  706. .oprofile_cpu_type = "ppc/750",
  707. .oprofile_type = PPC_OPROFILE_G4,
  708. },
  709. { /* 745/755 */
  710. .pvr_mask = 0xfffff000,
  711. .pvr_value = 0x00083000,
  712. .cpu_name = "745/755",
  713. .cpu_features = CPU_FTRS_750,
  714. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  715. .mmu_features = MMU_FTR_HPTE_TABLE,
  716. .icache_bsize = 32,
  717. .dcache_bsize = 32,
  718. .num_pmcs = 4,
  719. .pmc_type = PPC_PMC_IBM,
  720. .cpu_setup = __setup_cpu_750,
  721. .machine_check = machine_check_generic,
  722. .platform = "ppc750",
  723. },
  724. { /* 750FX rev 1.x */
  725. .pvr_mask = 0xffffff00,
  726. .pvr_value = 0x70000100,
  727. .cpu_name = "750FX",
  728. .cpu_features = CPU_FTRS_750FX1,
  729. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  730. .mmu_features = MMU_FTR_HPTE_TABLE,
  731. .icache_bsize = 32,
  732. .dcache_bsize = 32,
  733. .num_pmcs = 4,
  734. .pmc_type = PPC_PMC_IBM,
  735. .cpu_setup = __setup_cpu_750,
  736. .machine_check = machine_check_generic,
  737. .platform = "ppc750",
  738. .oprofile_cpu_type = "ppc/750",
  739. .oprofile_type = PPC_OPROFILE_G4,
  740. },
  741. { /* 750FX rev 2.0 must disable HID0[DPM] */
  742. .pvr_mask = 0xffffffff,
  743. .pvr_value = 0x70000200,
  744. .cpu_name = "750FX",
  745. .cpu_features = CPU_FTRS_750FX2,
  746. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  747. .mmu_features = MMU_FTR_HPTE_TABLE,
  748. .icache_bsize = 32,
  749. .dcache_bsize = 32,
  750. .num_pmcs = 4,
  751. .pmc_type = PPC_PMC_IBM,
  752. .cpu_setup = __setup_cpu_750,
  753. .machine_check = machine_check_generic,
  754. .platform = "ppc750",
  755. .oprofile_cpu_type = "ppc/750",
  756. .oprofile_type = PPC_OPROFILE_G4,
  757. },
  758. { /* 750FX (All revs except 2.0) */
  759. .pvr_mask = 0xffff0000,
  760. .pvr_value = 0x70000000,
  761. .cpu_name = "750FX",
  762. .cpu_features = CPU_FTRS_750FX,
  763. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  764. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  765. .icache_bsize = 32,
  766. .dcache_bsize = 32,
  767. .num_pmcs = 4,
  768. .pmc_type = PPC_PMC_IBM,
  769. .cpu_setup = __setup_cpu_750fx,
  770. .machine_check = machine_check_generic,
  771. .platform = "ppc750",
  772. .oprofile_cpu_type = "ppc/750",
  773. .oprofile_type = PPC_OPROFILE_G4,
  774. },
  775. { /* 750GX */
  776. .pvr_mask = 0xffff0000,
  777. .pvr_value = 0x70020000,
  778. .cpu_name = "750GX",
  779. .cpu_features = CPU_FTRS_750GX,
  780. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  781. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  782. .icache_bsize = 32,
  783. .dcache_bsize = 32,
  784. .num_pmcs = 4,
  785. .pmc_type = PPC_PMC_IBM,
  786. .cpu_setup = __setup_cpu_750fx,
  787. .machine_check = machine_check_generic,
  788. .platform = "ppc750",
  789. .oprofile_cpu_type = "ppc/750",
  790. .oprofile_type = PPC_OPROFILE_G4,
  791. },
  792. { /* 740/750 (L2CR bit need fixup for 740) */
  793. .pvr_mask = 0xffff0000,
  794. .pvr_value = 0x00080000,
  795. .cpu_name = "740/750",
  796. .cpu_features = CPU_FTRS_740,
  797. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  798. .mmu_features = MMU_FTR_HPTE_TABLE,
  799. .icache_bsize = 32,
  800. .dcache_bsize = 32,
  801. .num_pmcs = 4,
  802. .pmc_type = PPC_PMC_IBM,
  803. .cpu_setup = __setup_cpu_750,
  804. .machine_check = machine_check_generic,
  805. .platform = "ppc750",
  806. },
  807. { /* 7400 rev 1.1 ? (no TAU) */
  808. .pvr_mask = 0xffffffff,
  809. .pvr_value = 0x000c1101,
  810. .cpu_name = "7400 (1.1)",
  811. .cpu_features = CPU_FTRS_7400_NOTAU,
  812. .cpu_user_features = COMMON_USER |
  813. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  814. .mmu_features = MMU_FTR_HPTE_TABLE,
  815. .icache_bsize = 32,
  816. .dcache_bsize = 32,
  817. .num_pmcs = 4,
  818. .pmc_type = PPC_PMC_G4,
  819. .cpu_setup = __setup_cpu_7400,
  820. .machine_check = machine_check_generic,
  821. .platform = "ppc7400",
  822. },
  823. { /* 7400 */
  824. .pvr_mask = 0xffff0000,
  825. .pvr_value = 0x000c0000,
  826. .cpu_name = "7400",
  827. .cpu_features = CPU_FTRS_7400,
  828. .cpu_user_features = COMMON_USER |
  829. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  830. .mmu_features = MMU_FTR_HPTE_TABLE,
  831. .icache_bsize = 32,
  832. .dcache_bsize = 32,
  833. .num_pmcs = 4,
  834. .pmc_type = PPC_PMC_G4,
  835. .cpu_setup = __setup_cpu_7400,
  836. .machine_check = machine_check_generic,
  837. .platform = "ppc7400",
  838. },
  839. { /* 7410 */
  840. .pvr_mask = 0xffff0000,
  841. .pvr_value = 0x800c0000,
  842. .cpu_name = "7410",
  843. .cpu_features = CPU_FTRS_7400,
  844. .cpu_user_features = COMMON_USER |
  845. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  846. .mmu_features = MMU_FTR_HPTE_TABLE,
  847. .icache_bsize = 32,
  848. .dcache_bsize = 32,
  849. .num_pmcs = 4,
  850. .pmc_type = PPC_PMC_G4,
  851. .cpu_setup = __setup_cpu_7410,
  852. .machine_check = machine_check_generic,
  853. .platform = "ppc7400",
  854. },
  855. { /* 7450 2.0 - no doze/nap */
  856. .pvr_mask = 0xffffffff,
  857. .pvr_value = 0x80000200,
  858. .cpu_name = "7450",
  859. .cpu_features = CPU_FTRS_7450_20,
  860. .cpu_user_features = COMMON_USER |
  861. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  862. .mmu_features = MMU_FTR_HPTE_TABLE,
  863. .icache_bsize = 32,
  864. .dcache_bsize = 32,
  865. .num_pmcs = 6,
  866. .pmc_type = PPC_PMC_G4,
  867. .cpu_setup = __setup_cpu_745x,
  868. .oprofile_cpu_type = "ppc/7450",
  869. .oprofile_type = PPC_OPROFILE_G4,
  870. .machine_check = machine_check_generic,
  871. .platform = "ppc7450",
  872. },
  873. { /* 7450 2.1 */
  874. .pvr_mask = 0xffffffff,
  875. .pvr_value = 0x80000201,
  876. .cpu_name = "7450",
  877. .cpu_features = CPU_FTRS_7450_21,
  878. .cpu_user_features = COMMON_USER |
  879. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  880. .mmu_features = MMU_FTR_HPTE_TABLE,
  881. .icache_bsize = 32,
  882. .dcache_bsize = 32,
  883. .num_pmcs = 6,
  884. .pmc_type = PPC_PMC_G4,
  885. .cpu_setup = __setup_cpu_745x,
  886. .oprofile_cpu_type = "ppc/7450",
  887. .oprofile_type = PPC_OPROFILE_G4,
  888. .machine_check = machine_check_generic,
  889. .platform = "ppc7450",
  890. },
  891. { /* 7450 2.3 and newer */
  892. .pvr_mask = 0xffff0000,
  893. .pvr_value = 0x80000000,
  894. .cpu_name = "7450",
  895. .cpu_features = CPU_FTRS_7450_23,
  896. .cpu_user_features = COMMON_USER |
  897. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  898. .mmu_features = MMU_FTR_HPTE_TABLE,
  899. .icache_bsize = 32,
  900. .dcache_bsize = 32,
  901. .num_pmcs = 6,
  902. .pmc_type = PPC_PMC_G4,
  903. .cpu_setup = __setup_cpu_745x,
  904. .oprofile_cpu_type = "ppc/7450",
  905. .oprofile_type = PPC_OPROFILE_G4,
  906. .machine_check = machine_check_generic,
  907. .platform = "ppc7450",
  908. },
  909. { /* 7455 rev 1.x */
  910. .pvr_mask = 0xffffff00,
  911. .pvr_value = 0x80010100,
  912. .cpu_name = "7455",
  913. .cpu_features = CPU_FTRS_7455_1,
  914. .cpu_user_features = COMMON_USER |
  915. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  916. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  917. .icache_bsize = 32,
  918. .dcache_bsize = 32,
  919. .num_pmcs = 6,
  920. .pmc_type = PPC_PMC_G4,
  921. .cpu_setup = __setup_cpu_745x,
  922. .oprofile_cpu_type = "ppc/7450",
  923. .oprofile_type = PPC_OPROFILE_G4,
  924. .machine_check = machine_check_generic,
  925. .platform = "ppc7450",
  926. },
  927. { /* 7455 rev 2.0 */
  928. .pvr_mask = 0xffffffff,
  929. .pvr_value = 0x80010200,
  930. .cpu_name = "7455",
  931. .cpu_features = CPU_FTRS_7455_20,
  932. .cpu_user_features = COMMON_USER |
  933. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  934. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  935. .icache_bsize = 32,
  936. .dcache_bsize = 32,
  937. .num_pmcs = 6,
  938. .pmc_type = PPC_PMC_G4,
  939. .cpu_setup = __setup_cpu_745x,
  940. .oprofile_cpu_type = "ppc/7450",
  941. .oprofile_type = PPC_OPROFILE_G4,
  942. .machine_check = machine_check_generic,
  943. .platform = "ppc7450",
  944. },
  945. { /* 7455 others */
  946. .pvr_mask = 0xffff0000,
  947. .pvr_value = 0x80010000,
  948. .cpu_name = "7455",
  949. .cpu_features = CPU_FTRS_7455,
  950. .cpu_user_features = COMMON_USER |
  951. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  952. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  953. .icache_bsize = 32,
  954. .dcache_bsize = 32,
  955. .num_pmcs = 6,
  956. .pmc_type = PPC_PMC_G4,
  957. .cpu_setup = __setup_cpu_745x,
  958. .oprofile_cpu_type = "ppc/7450",
  959. .oprofile_type = PPC_OPROFILE_G4,
  960. .machine_check = machine_check_generic,
  961. .platform = "ppc7450",
  962. },
  963. { /* 7447/7457 Rev 1.0 */
  964. .pvr_mask = 0xffffffff,
  965. .pvr_value = 0x80020100,
  966. .cpu_name = "7447/7457",
  967. .cpu_features = CPU_FTRS_7447_10,
  968. .cpu_user_features = COMMON_USER |
  969. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  970. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  971. .icache_bsize = 32,
  972. .dcache_bsize = 32,
  973. .num_pmcs = 6,
  974. .pmc_type = PPC_PMC_G4,
  975. .cpu_setup = __setup_cpu_745x,
  976. .oprofile_cpu_type = "ppc/7450",
  977. .oprofile_type = PPC_OPROFILE_G4,
  978. .machine_check = machine_check_generic,
  979. .platform = "ppc7450",
  980. },
  981. { /* 7447/7457 Rev 1.1 */
  982. .pvr_mask = 0xffffffff,
  983. .pvr_value = 0x80020101,
  984. .cpu_name = "7447/7457",
  985. .cpu_features = CPU_FTRS_7447_10,
  986. .cpu_user_features = COMMON_USER |
  987. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  988. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  989. .icache_bsize = 32,
  990. .dcache_bsize = 32,
  991. .num_pmcs = 6,
  992. .pmc_type = PPC_PMC_G4,
  993. .cpu_setup = __setup_cpu_745x,
  994. .oprofile_cpu_type = "ppc/7450",
  995. .oprofile_type = PPC_OPROFILE_G4,
  996. .machine_check = machine_check_generic,
  997. .platform = "ppc7450",
  998. },
  999. { /* 7447/7457 Rev 1.2 and later */
  1000. .pvr_mask = 0xffff0000,
  1001. .pvr_value = 0x80020000,
  1002. .cpu_name = "7447/7457",
  1003. .cpu_features = CPU_FTRS_7447,
  1004. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1005. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1006. .icache_bsize = 32,
  1007. .dcache_bsize = 32,
  1008. .num_pmcs = 6,
  1009. .pmc_type = PPC_PMC_G4,
  1010. .cpu_setup = __setup_cpu_745x,
  1011. .oprofile_cpu_type = "ppc/7450",
  1012. .oprofile_type = PPC_OPROFILE_G4,
  1013. .machine_check = machine_check_generic,
  1014. .platform = "ppc7450",
  1015. },
  1016. { /* 7447A */
  1017. .pvr_mask = 0xffff0000,
  1018. .pvr_value = 0x80030000,
  1019. .cpu_name = "7447A",
  1020. .cpu_features = CPU_FTRS_7447A,
  1021. .cpu_user_features = COMMON_USER |
  1022. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1023. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1024. .icache_bsize = 32,
  1025. .dcache_bsize = 32,
  1026. .num_pmcs = 6,
  1027. .pmc_type = PPC_PMC_G4,
  1028. .cpu_setup = __setup_cpu_745x,
  1029. .oprofile_cpu_type = "ppc/7450",
  1030. .oprofile_type = PPC_OPROFILE_G4,
  1031. .machine_check = machine_check_generic,
  1032. .platform = "ppc7450",
  1033. },
  1034. { /* 7448 */
  1035. .pvr_mask = 0xffff0000,
  1036. .pvr_value = 0x80040000,
  1037. .cpu_name = "7448",
  1038. .cpu_features = CPU_FTRS_7448,
  1039. .cpu_user_features = COMMON_USER |
  1040. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1041. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1042. .icache_bsize = 32,
  1043. .dcache_bsize = 32,
  1044. .num_pmcs = 6,
  1045. .pmc_type = PPC_PMC_G4,
  1046. .cpu_setup = __setup_cpu_745x,
  1047. .oprofile_cpu_type = "ppc/7450",
  1048. .oprofile_type = PPC_OPROFILE_G4,
  1049. .machine_check = machine_check_generic,
  1050. .platform = "ppc7450",
  1051. },
  1052. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1053. .pvr_mask = 0x7fff0000,
  1054. .pvr_value = 0x00810000,
  1055. .cpu_name = "82xx",
  1056. .cpu_features = CPU_FTRS_82XX,
  1057. .cpu_user_features = COMMON_USER,
  1058. .mmu_features = 0,
  1059. .icache_bsize = 32,
  1060. .dcache_bsize = 32,
  1061. .cpu_setup = __setup_cpu_603,
  1062. .machine_check = machine_check_generic,
  1063. .platform = "ppc603",
  1064. },
  1065. { /* All G2_LE (603e core, plus some) have the same pvr */
  1066. .pvr_mask = 0x7fff0000,
  1067. .pvr_value = 0x00820000,
  1068. .cpu_name = "G2_LE",
  1069. .cpu_features = CPU_FTRS_G2_LE,
  1070. .cpu_user_features = COMMON_USER,
  1071. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1072. .icache_bsize = 32,
  1073. .dcache_bsize = 32,
  1074. .cpu_setup = __setup_cpu_603,
  1075. .machine_check = machine_check_generic,
  1076. .platform = "ppc603",
  1077. },
  1078. { /* e300c1 (a 603e core, plus some) on 83xx */
  1079. .pvr_mask = 0x7fff0000,
  1080. .pvr_value = 0x00830000,
  1081. .cpu_name = "e300c1",
  1082. .cpu_features = CPU_FTRS_E300,
  1083. .cpu_user_features = COMMON_USER,
  1084. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1085. .icache_bsize = 32,
  1086. .dcache_bsize = 32,
  1087. .cpu_setup = __setup_cpu_603,
  1088. .machine_check = machine_check_generic,
  1089. .platform = "ppc603",
  1090. },
  1091. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1092. .pvr_mask = 0x7fff0000,
  1093. .pvr_value = 0x00840000,
  1094. .cpu_name = "e300c2",
  1095. .cpu_features = CPU_FTRS_E300C2,
  1096. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1097. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1098. MMU_FTR_NEED_DTLB_SW_LRU,
  1099. .icache_bsize = 32,
  1100. .dcache_bsize = 32,
  1101. .cpu_setup = __setup_cpu_603,
  1102. .machine_check = machine_check_generic,
  1103. .platform = "ppc603",
  1104. },
  1105. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1106. .pvr_mask = 0x7fff0000,
  1107. .pvr_value = 0x00850000,
  1108. .cpu_name = "e300c3",
  1109. .cpu_features = CPU_FTRS_E300,
  1110. .cpu_user_features = COMMON_USER,
  1111. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1112. MMU_FTR_NEED_DTLB_SW_LRU,
  1113. .icache_bsize = 32,
  1114. .dcache_bsize = 32,
  1115. .cpu_setup = __setup_cpu_603,
  1116. .num_pmcs = 4,
  1117. .oprofile_cpu_type = "ppc/e300",
  1118. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1119. .platform = "ppc603",
  1120. },
  1121. { /* e300c4 (e300c1, plus one IU) */
  1122. .pvr_mask = 0x7fff0000,
  1123. .pvr_value = 0x00860000,
  1124. .cpu_name = "e300c4",
  1125. .cpu_features = CPU_FTRS_E300,
  1126. .cpu_user_features = COMMON_USER,
  1127. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1128. MMU_FTR_NEED_DTLB_SW_LRU,
  1129. .icache_bsize = 32,
  1130. .dcache_bsize = 32,
  1131. .cpu_setup = __setup_cpu_603,
  1132. .machine_check = machine_check_generic,
  1133. .num_pmcs = 4,
  1134. .oprofile_cpu_type = "ppc/e300",
  1135. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1136. .platform = "ppc603",
  1137. },
  1138. { /* default match, we assume split I/D cache & TB (non-601)... */
  1139. .pvr_mask = 0x00000000,
  1140. .pvr_value = 0x00000000,
  1141. .cpu_name = "(generic PPC)",
  1142. .cpu_features = CPU_FTRS_CLASSIC32,
  1143. .cpu_user_features = COMMON_USER,
  1144. .mmu_features = MMU_FTR_HPTE_TABLE,
  1145. .icache_bsize = 32,
  1146. .dcache_bsize = 32,
  1147. .machine_check = machine_check_generic,
  1148. .platform = "ppc603",
  1149. },
  1150. #endif /* CLASSIC_PPC */
  1151. #ifdef CONFIG_8xx
  1152. { /* 8xx */
  1153. .pvr_mask = 0xffff0000,
  1154. .pvr_value = 0x00500000,
  1155. .cpu_name = "8xx",
  1156. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1157. * if the 8xx code is there.... */
  1158. .cpu_features = CPU_FTRS_8XX,
  1159. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1160. .mmu_features = MMU_FTR_TYPE_8xx,
  1161. .icache_bsize = 16,
  1162. .dcache_bsize = 16,
  1163. .platform = "ppc823",
  1164. },
  1165. #endif /* CONFIG_8xx */
  1166. #ifdef CONFIG_40x
  1167. { /* 403GC */
  1168. .pvr_mask = 0xffffff00,
  1169. .pvr_value = 0x00200200,
  1170. .cpu_name = "403GC",
  1171. .cpu_features = CPU_FTRS_40X,
  1172. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1173. .mmu_features = MMU_FTR_TYPE_40x,
  1174. .icache_bsize = 16,
  1175. .dcache_bsize = 16,
  1176. .machine_check = machine_check_4xx,
  1177. .platform = "ppc403",
  1178. },
  1179. { /* 403GCX */
  1180. .pvr_mask = 0xffffff00,
  1181. .pvr_value = 0x00201400,
  1182. .cpu_name = "403GCX",
  1183. .cpu_features = CPU_FTRS_40X,
  1184. .cpu_user_features = PPC_FEATURE_32 |
  1185. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1186. .mmu_features = MMU_FTR_TYPE_40x,
  1187. .icache_bsize = 16,
  1188. .dcache_bsize = 16,
  1189. .machine_check = machine_check_4xx,
  1190. .platform = "ppc403",
  1191. },
  1192. { /* 403G ?? */
  1193. .pvr_mask = 0xffff0000,
  1194. .pvr_value = 0x00200000,
  1195. .cpu_name = "403G ??",
  1196. .cpu_features = CPU_FTRS_40X,
  1197. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1198. .mmu_features = MMU_FTR_TYPE_40x,
  1199. .icache_bsize = 16,
  1200. .dcache_bsize = 16,
  1201. .machine_check = machine_check_4xx,
  1202. .platform = "ppc403",
  1203. },
  1204. { /* 405GP */
  1205. .pvr_mask = 0xffff0000,
  1206. .pvr_value = 0x40110000,
  1207. .cpu_name = "405GP",
  1208. .cpu_features = CPU_FTRS_40X,
  1209. .cpu_user_features = PPC_FEATURE_32 |
  1210. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1211. .mmu_features = MMU_FTR_TYPE_40x,
  1212. .icache_bsize = 32,
  1213. .dcache_bsize = 32,
  1214. .machine_check = machine_check_4xx,
  1215. .platform = "ppc405",
  1216. },
  1217. { /* STB 03xxx */
  1218. .pvr_mask = 0xffff0000,
  1219. .pvr_value = 0x40130000,
  1220. .cpu_name = "STB03xxx",
  1221. .cpu_features = CPU_FTRS_40X,
  1222. .cpu_user_features = PPC_FEATURE_32 |
  1223. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1224. .mmu_features = MMU_FTR_TYPE_40x,
  1225. .icache_bsize = 32,
  1226. .dcache_bsize = 32,
  1227. .machine_check = machine_check_4xx,
  1228. .platform = "ppc405",
  1229. },
  1230. { /* STB 04xxx */
  1231. .pvr_mask = 0xffff0000,
  1232. .pvr_value = 0x41810000,
  1233. .cpu_name = "STB04xxx",
  1234. .cpu_features = CPU_FTRS_40X,
  1235. .cpu_user_features = PPC_FEATURE_32 |
  1236. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1237. .mmu_features = MMU_FTR_TYPE_40x,
  1238. .icache_bsize = 32,
  1239. .dcache_bsize = 32,
  1240. .machine_check = machine_check_4xx,
  1241. .platform = "ppc405",
  1242. },
  1243. { /* NP405L */
  1244. .pvr_mask = 0xffff0000,
  1245. .pvr_value = 0x41610000,
  1246. .cpu_name = "NP405L",
  1247. .cpu_features = CPU_FTRS_40X,
  1248. .cpu_user_features = PPC_FEATURE_32 |
  1249. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1250. .mmu_features = MMU_FTR_TYPE_40x,
  1251. .icache_bsize = 32,
  1252. .dcache_bsize = 32,
  1253. .machine_check = machine_check_4xx,
  1254. .platform = "ppc405",
  1255. },
  1256. { /* NP4GS3 */
  1257. .pvr_mask = 0xffff0000,
  1258. .pvr_value = 0x40B10000,
  1259. .cpu_name = "NP4GS3",
  1260. .cpu_features = CPU_FTRS_40X,
  1261. .cpu_user_features = PPC_FEATURE_32 |
  1262. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1263. .mmu_features = MMU_FTR_TYPE_40x,
  1264. .icache_bsize = 32,
  1265. .dcache_bsize = 32,
  1266. .machine_check = machine_check_4xx,
  1267. .platform = "ppc405",
  1268. },
  1269. { /* NP405H */
  1270. .pvr_mask = 0xffff0000,
  1271. .pvr_value = 0x41410000,
  1272. .cpu_name = "NP405H",
  1273. .cpu_features = CPU_FTRS_40X,
  1274. .cpu_user_features = PPC_FEATURE_32 |
  1275. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1276. .mmu_features = MMU_FTR_TYPE_40x,
  1277. .icache_bsize = 32,
  1278. .dcache_bsize = 32,
  1279. .machine_check = machine_check_4xx,
  1280. .platform = "ppc405",
  1281. },
  1282. { /* 405GPr */
  1283. .pvr_mask = 0xffff0000,
  1284. .pvr_value = 0x50910000,
  1285. .cpu_name = "405GPr",
  1286. .cpu_features = CPU_FTRS_40X,
  1287. .cpu_user_features = PPC_FEATURE_32 |
  1288. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1289. .mmu_features = MMU_FTR_TYPE_40x,
  1290. .icache_bsize = 32,
  1291. .dcache_bsize = 32,
  1292. .machine_check = machine_check_4xx,
  1293. .platform = "ppc405",
  1294. },
  1295. { /* STBx25xx */
  1296. .pvr_mask = 0xffff0000,
  1297. .pvr_value = 0x51510000,
  1298. .cpu_name = "STBx25xx",
  1299. .cpu_features = CPU_FTRS_40X,
  1300. .cpu_user_features = PPC_FEATURE_32 |
  1301. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1302. .mmu_features = MMU_FTR_TYPE_40x,
  1303. .icache_bsize = 32,
  1304. .dcache_bsize = 32,
  1305. .machine_check = machine_check_4xx,
  1306. .platform = "ppc405",
  1307. },
  1308. { /* 405LP */
  1309. .pvr_mask = 0xffff0000,
  1310. .pvr_value = 0x41F10000,
  1311. .cpu_name = "405LP",
  1312. .cpu_features = CPU_FTRS_40X,
  1313. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1314. .mmu_features = MMU_FTR_TYPE_40x,
  1315. .icache_bsize = 32,
  1316. .dcache_bsize = 32,
  1317. .machine_check = machine_check_4xx,
  1318. .platform = "ppc405",
  1319. },
  1320. { /* Xilinx Virtex-II Pro */
  1321. .pvr_mask = 0xfffff000,
  1322. .pvr_value = 0x20010000,
  1323. .cpu_name = "Virtex-II Pro",
  1324. .cpu_features = CPU_FTRS_40X,
  1325. .cpu_user_features = PPC_FEATURE_32 |
  1326. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1327. .mmu_features = MMU_FTR_TYPE_40x,
  1328. .icache_bsize = 32,
  1329. .dcache_bsize = 32,
  1330. .machine_check = machine_check_4xx,
  1331. .platform = "ppc405",
  1332. },
  1333. { /* Xilinx Virtex-4 FX */
  1334. .pvr_mask = 0xfffff000,
  1335. .pvr_value = 0x20011000,
  1336. .cpu_name = "Virtex-4 FX",
  1337. .cpu_features = CPU_FTRS_40X,
  1338. .cpu_user_features = PPC_FEATURE_32 |
  1339. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1340. .mmu_features = MMU_FTR_TYPE_40x,
  1341. .icache_bsize = 32,
  1342. .dcache_bsize = 32,
  1343. .machine_check = machine_check_4xx,
  1344. .platform = "ppc405",
  1345. },
  1346. { /* 405EP */
  1347. .pvr_mask = 0xffff0000,
  1348. .pvr_value = 0x51210000,
  1349. .cpu_name = "405EP",
  1350. .cpu_features = CPU_FTRS_40X,
  1351. .cpu_user_features = PPC_FEATURE_32 |
  1352. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1353. .mmu_features = MMU_FTR_TYPE_40x,
  1354. .icache_bsize = 32,
  1355. .dcache_bsize = 32,
  1356. .machine_check = machine_check_4xx,
  1357. .platform = "ppc405",
  1358. },
  1359. { /* 405EX */
  1360. .pvr_mask = 0xffff0004,
  1361. .pvr_value = 0x12910004,
  1362. .cpu_name = "405EX",
  1363. .cpu_features = CPU_FTRS_40X,
  1364. .cpu_user_features = PPC_FEATURE_32 |
  1365. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1366. .mmu_features = MMU_FTR_TYPE_40x,
  1367. .icache_bsize = 32,
  1368. .dcache_bsize = 32,
  1369. .machine_check = machine_check_4xx,
  1370. .platform = "ppc405",
  1371. },
  1372. { /* 405EXr */
  1373. .pvr_mask = 0xffff0004,
  1374. .pvr_value = 0x12910000,
  1375. .cpu_name = "405EXr",
  1376. .cpu_features = CPU_FTRS_40X,
  1377. .cpu_user_features = PPC_FEATURE_32 |
  1378. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1379. .mmu_features = MMU_FTR_TYPE_40x,
  1380. .icache_bsize = 32,
  1381. .dcache_bsize = 32,
  1382. .machine_check = machine_check_4xx,
  1383. .platform = "ppc405",
  1384. },
  1385. {
  1386. /* 405EZ */
  1387. .pvr_mask = 0xffff0000,
  1388. .pvr_value = 0x41510000,
  1389. .cpu_name = "405EZ",
  1390. .cpu_features = CPU_FTRS_40X,
  1391. .cpu_user_features = PPC_FEATURE_32 |
  1392. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1393. .mmu_features = MMU_FTR_TYPE_40x,
  1394. .icache_bsize = 32,
  1395. .dcache_bsize = 32,
  1396. .machine_check = machine_check_4xx,
  1397. .platform = "ppc405",
  1398. },
  1399. { /* default match */
  1400. .pvr_mask = 0x00000000,
  1401. .pvr_value = 0x00000000,
  1402. .cpu_name = "(generic 40x PPC)",
  1403. .cpu_features = CPU_FTRS_40X,
  1404. .cpu_user_features = PPC_FEATURE_32 |
  1405. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1406. .mmu_features = MMU_FTR_TYPE_40x,
  1407. .icache_bsize = 32,
  1408. .dcache_bsize = 32,
  1409. .machine_check = machine_check_4xx,
  1410. .platform = "ppc405",
  1411. }
  1412. #endif /* CONFIG_40x */
  1413. #ifdef CONFIG_44x
  1414. {
  1415. .pvr_mask = 0xf0000fff,
  1416. .pvr_value = 0x40000850,
  1417. .cpu_name = "440GR Rev. A",
  1418. .cpu_features = CPU_FTRS_44X,
  1419. .cpu_user_features = COMMON_USER_BOOKE,
  1420. .mmu_features = MMU_FTR_TYPE_44x,
  1421. .icache_bsize = 32,
  1422. .dcache_bsize = 32,
  1423. .machine_check = machine_check_4xx,
  1424. .platform = "ppc440",
  1425. },
  1426. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1427. .pvr_mask = 0xf0000fff,
  1428. .pvr_value = 0x40000858,
  1429. .cpu_name = "440EP Rev. A",
  1430. .cpu_features = CPU_FTRS_44X,
  1431. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1432. .mmu_features = MMU_FTR_TYPE_44x,
  1433. .icache_bsize = 32,
  1434. .dcache_bsize = 32,
  1435. .cpu_setup = __setup_cpu_440ep,
  1436. .machine_check = machine_check_4xx,
  1437. .platform = "ppc440",
  1438. },
  1439. {
  1440. .pvr_mask = 0xf0000fff,
  1441. .pvr_value = 0x400008d3,
  1442. .cpu_name = "440GR Rev. B",
  1443. .cpu_features = CPU_FTRS_44X,
  1444. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1445. .mmu_features = MMU_FTR_TYPE_44x,
  1446. .icache_bsize = 32,
  1447. .dcache_bsize = 32,
  1448. .machine_check = machine_check_4xx,
  1449. .platform = "ppc440",
  1450. },
  1451. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1452. .pvr_mask = 0xf0000ff7,
  1453. .pvr_value = 0x400008d4,
  1454. .cpu_name = "440EP Rev. C",
  1455. .cpu_features = CPU_FTRS_44X,
  1456. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1457. .mmu_features = MMU_FTR_TYPE_44x,
  1458. .icache_bsize = 32,
  1459. .dcache_bsize = 32,
  1460. .cpu_setup = __setup_cpu_440ep,
  1461. .machine_check = machine_check_4xx,
  1462. .platform = "ppc440",
  1463. },
  1464. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1465. .pvr_mask = 0xf0000fff,
  1466. .pvr_value = 0x400008db,
  1467. .cpu_name = "440EP Rev. B",
  1468. .cpu_features = CPU_FTRS_44X,
  1469. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1470. .mmu_features = MMU_FTR_TYPE_44x,
  1471. .icache_bsize = 32,
  1472. .dcache_bsize = 32,
  1473. .cpu_setup = __setup_cpu_440ep,
  1474. .machine_check = machine_check_4xx,
  1475. .platform = "ppc440",
  1476. },
  1477. { /* 440GRX */
  1478. .pvr_mask = 0xf0000ffb,
  1479. .pvr_value = 0x200008D0,
  1480. .cpu_name = "440GRX",
  1481. .cpu_features = CPU_FTRS_44X,
  1482. .cpu_user_features = COMMON_USER_BOOKE,
  1483. .mmu_features = MMU_FTR_TYPE_44x,
  1484. .icache_bsize = 32,
  1485. .dcache_bsize = 32,
  1486. .cpu_setup = __setup_cpu_440grx,
  1487. .machine_check = machine_check_440A,
  1488. .platform = "ppc440",
  1489. },
  1490. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1491. .pvr_mask = 0xf0000ffb,
  1492. .pvr_value = 0x200008D8,
  1493. .cpu_name = "440EPX",
  1494. .cpu_features = CPU_FTRS_44X,
  1495. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1496. .mmu_features = MMU_FTR_TYPE_44x,
  1497. .icache_bsize = 32,
  1498. .dcache_bsize = 32,
  1499. .cpu_setup = __setup_cpu_440epx,
  1500. .machine_check = machine_check_440A,
  1501. .platform = "ppc440",
  1502. },
  1503. { /* 440GP Rev. B */
  1504. .pvr_mask = 0xf0000fff,
  1505. .pvr_value = 0x40000440,
  1506. .cpu_name = "440GP Rev. B",
  1507. .cpu_features = CPU_FTRS_44X,
  1508. .cpu_user_features = COMMON_USER_BOOKE,
  1509. .mmu_features = MMU_FTR_TYPE_44x,
  1510. .icache_bsize = 32,
  1511. .dcache_bsize = 32,
  1512. .machine_check = machine_check_4xx,
  1513. .platform = "ppc440gp",
  1514. },
  1515. { /* 440GP Rev. C */
  1516. .pvr_mask = 0xf0000fff,
  1517. .pvr_value = 0x40000481,
  1518. .cpu_name = "440GP Rev. C",
  1519. .cpu_features = CPU_FTRS_44X,
  1520. .cpu_user_features = COMMON_USER_BOOKE,
  1521. .mmu_features = MMU_FTR_TYPE_44x,
  1522. .icache_bsize = 32,
  1523. .dcache_bsize = 32,
  1524. .machine_check = machine_check_4xx,
  1525. .platform = "ppc440gp",
  1526. },
  1527. { /* 440GX Rev. A */
  1528. .pvr_mask = 0xf0000fff,
  1529. .pvr_value = 0x50000850,
  1530. .cpu_name = "440GX Rev. A",
  1531. .cpu_features = CPU_FTRS_44X,
  1532. .cpu_user_features = COMMON_USER_BOOKE,
  1533. .mmu_features = MMU_FTR_TYPE_44x,
  1534. .icache_bsize = 32,
  1535. .dcache_bsize = 32,
  1536. .cpu_setup = __setup_cpu_440gx,
  1537. .machine_check = machine_check_440A,
  1538. .platform = "ppc440",
  1539. },
  1540. { /* 440GX Rev. B */
  1541. .pvr_mask = 0xf0000fff,
  1542. .pvr_value = 0x50000851,
  1543. .cpu_name = "440GX Rev. B",
  1544. .cpu_features = CPU_FTRS_44X,
  1545. .cpu_user_features = COMMON_USER_BOOKE,
  1546. .mmu_features = MMU_FTR_TYPE_44x,
  1547. .icache_bsize = 32,
  1548. .dcache_bsize = 32,
  1549. .cpu_setup = __setup_cpu_440gx,
  1550. .machine_check = machine_check_440A,
  1551. .platform = "ppc440",
  1552. },
  1553. { /* 440GX Rev. C */
  1554. .pvr_mask = 0xf0000fff,
  1555. .pvr_value = 0x50000892,
  1556. .cpu_name = "440GX Rev. C",
  1557. .cpu_features = CPU_FTRS_44X,
  1558. .cpu_user_features = COMMON_USER_BOOKE,
  1559. .mmu_features = MMU_FTR_TYPE_44x,
  1560. .icache_bsize = 32,
  1561. .dcache_bsize = 32,
  1562. .cpu_setup = __setup_cpu_440gx,
  1563. .machine_check = machine_check_440A,
  1564. .platform = "ppc440",
  1565. },
  1566. { /* 440GX Rev. F */
  1567. .pvr_mask = 0xf0000fff,
  1568. .pvr_value = 0x50000894,
  1569. .cpu_name = "440GX Rev. F",
  1570. .cpu_features = CPU_FTRS_44X,
  1571. .cpu_user_features = COMMON_USER_BOOKE,
  1572. .mmu_features = MMU_FTR_TYPE_44x,
  1573. .icache_bsize = 32,
  1574. .dcache_bsize = 32,
  1575. .cpu_setup = __setup_cpu_440gx,
  1576. .machine_check = machine_check_440A,
  1577. .platform = "ppc440",
  1578. },
  1579. { /* 440SP Rev. A */
  1580. .pvr_mask = 0xfff00fff,
  1581. .pvr_value = 0x53200891,
  1582. .cpu_name = "440SP Rev. A",
  1583. .cpu_features = CPU_FTRS_44X,
  1584. .cpu_user_features = COMMON_USER_BOOKE,
  1585. .mmu_features = MMU_FTR_TYPE_44x,
  1586. .icache_bsize = 32,
  1587. .dcache_bsize = 32,
  1588. .machine_check = machine_check_4xx,
  1589. .platform = "ppc440",
  1590. },
  1591. { /* 440SPe Rev. A */
  1592. .pvr_mask = 0xfff00fff,
  1593. .pvr_value = 0x53400890,
  1594. .cpu_name = "440SPe Rev. A",
  1595. .cpu_features = CPU_FTRS_44X,
  1596. .cpu_user_features = COMMON_USER_BOOKE,
  1597. .mmu_features = MMU_FTR_TYPE_44x,
  1598. .icache_bsize = 32,
  1599. .dcache_bsize = 32,
  1600. .cpu_setup = __setup_cpu_440spe,
  1601. .machine_check = machine_check_440A,
  1602. .platform = "ppc440",
  1603. },
  1604. { /* 440SPe Rev. B */
  1605. .pvr_mask = 0xfff00fff,
  1606. .pvr_value = 0x53400891,
  1607. .cpu_name = "440SPe Rev. B",
  1608. .cpu_features = CPU_FTRS_44X,
  1609. .cpu_user_features = COMMON_USER_BOOKE,
  1610. .mmu_features = MMU_FTR_TYPE_44x,
  1611. .icache_bsize = 32,
  1612. .dcache_bsize = 32,
  1613. .cpu_setup = __setup_cpu_440spe,
  1614. .machine_check = machine_check_440A,
  1615. .platform = "ppc440",
  1616. },
  1617. { /* 440 in Xilinx Virtex-5 FXT */
  1618. .pvr_mask = 0xfffffff0,
  1619. .pvr_value = 0x7ff21910,
  1620. .cpu_name = "440 in Virtex-5 FXT",
  1621. .cpu_features = CPU_FTRS_44X,
  1622. .cpu_user_features = COMMON_USER_BOOKE,
  1623. .mmu_features = MMU_FTR_TYPE_44x,
  1624. .icache_bsize = 32,
  1625. .dcache_bsize = 32,
  1626. .cpu_setup = __setup_cpu_440x5,
  1627. .machine_check = machine_check_440A,
  1628. .platform = "ppc440",
  1629. },
  1630. { /* 460EX */
  1631. .pvr_mask = 0xffff0006,
  1632. .pvr_value = 0x13020002,
  1633. .cpu_name = "460EX",
  1634. .cpu_features = CPU_FTRS_440x6,
  1635. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1636. .mmu_features = MMU_FTR_TYPE_44x,
  1637. .icache_bsize = 32,
  1638. .dcache_bsize = 32,
  1639. .cpu_setup = __setup_cpu_460ex,
  1640. .machine_check = machine_check_440A,
  1641. .platform = "ppc440",
  1642. },
  1643. { /* 460EX Rev B */
  1644. .pvr_mask = 0xffff0007,
  1645. .pvr_value = 0x13020004,
  1646. .cpu_name = "460EX Rev. B",
  1647. .cpu_features = CPU_FTRS_440x6,
  1648. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1649. .mmu_features = MMU_FTR_TYPE_44x,
  1650. .icache_bsize = 32,
  1651. .dcache_bsize = 32,
  1652. .cpu_setup = __setup_cpu_460ex,
  1653. .machine_check = machine_check_440A,
  1654. .platform = "ppc440",
  1655. },
  1656. { /* 460GT */
  1657. .pvr_mask = 0xffff0006,
  1658. .pvr_value = 0x13020000,
  1659. .cpu_name = "460GT",
  1660. .cpu_features = CPU_FTRS_440x6,
  1661. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1662. .mmu_features = MMU_FTR_TYPE_44x,
  1663. .icache_bsize = 32,
  1664. .dcache_bsize = 32,
  1665. .cpu_setup = __setup_cpu_460gt,
  1666. .machine_check = machine_check_440A,
  1667. .platform = "ppc440",
  1668. },
  1669. { /* 460GT Rev B */
  1670. .pvr_mask = 0xffff0007,
  1671. .pvr_value = 0x13020005,
  1672. .cpu_name = "460GT Rev. B",
  1673. .cpu_features = CPU_FTRS_440x6,
  1674. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1675. .mmu_features = MMU_FTR_TYPE_44x,
  1676. .icache_bsize = 32,
  1677. .dcache_bsize = 32,
  1678. .cpu_setup = __setup_cpu_460gt,
  1679. .machine_check = machine_check_440A,
  1680. .platform = "ppc440",
  1681. },
  1682. { /* 460SX */
  1683. .pvr_mask = 0xffffff00,
  1684. .pvr_value = 0x13541800,
  1685. .cpu_name = "460SX",
  1686. .cpu_features = CPU_FTRS_44X,
  1687. .cpu_user_features = COMMON_USER_BOOKE,
  1688. .mmu_features = MMU_FTR_TYPE_44x,
  1689. .icache_bsize = 32,
  1690. .dcache_bsize = 32,
  1691. .cpu_setup = __setup_cpu_460sx,
  1692. .machine_check = machine_check_440A,
  1693. .platform = "ppc440",
  1694. },
  1695. { /* default match */
  1696. .pvr_mask = 0x00000000,
  1697. .pvr_value = 0x00000000,
  1698. .cpu_name = "(generic 44x PPC)",
  1699. .cpu_features = CPU_FTRS_44X,
  1700. .cpu_user_features = COMMON_USER_BOOKE,
  1701. .mmu_features = MMU_FTR_TYPE_44x,
  1702. .icache_bsize = 32,
  1703. .dcache_bsize = 32,
  1704. .machine_check = machine_check_4xx,
  1705. .platform = "ppc440",
  1706. }
  1707. #endif /* CONFIG_44x */
  1708. #ifdef CONFIG_E200
  1709. { /* e200z5 */
  1710. .pvr_mask = 0xfff00000,
  1711. .pvr_value = 0x81000000,
  1712. .cpu_name = "e200z5",
  1713. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1714. .cpu_features = CPU_FTRS_E200,
  1715. .cpu_user_features = COMMON_USER_BOOKE |
  1716. PPC_FEATURE_HAS_EFP_SINGLE |
  1717. PPC_FEATURE_UNIFIED_CACHE,
  1718. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1719. .dcache_bsize = 32,
  1720. .machine_check = machine_check_e200,
  1721. .platform = "ppc5554",
  1722. },
  1723. { /* e200z6 */
  1724. .pvr_mask = 0xfff00000,
  1725. .pvr_value = 0x81100000,
  1726. .cpu_name = "e200z6",
  1727. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1728. .cpu_features = CPU_FTRS_E200,
  1729. .cpu_user_features = COMMON_USER_BOOKE |
  1730. PPC_FEATURE_HAS_SPE_COMP |
  1731. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1732. PPC_FEATURE_UNIFIED_CACHE,
  1733. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1734. .dcache_bsize = 32,
  1735. .machine_check = machine_check_e200,
  1736. .platform = "ppc5554",
  1737. },
  1738. { /* default match */
  1739. .pvr_mask = 0x00000000,
  1740. .pvr_value = 0x00000000,
  1741. .cpu_name = "(generic E200 PPC)",
  1742. .cpu_features = CPU_FTRS_E200,
  1743. .cpu_user_features = COMMON_USER_BOOKE |
  1744. PPC_FEATURE_HAS_EFP_SINGLE |
  1745. PPC_FEATURE_UNIFIED_CACHE,
  1746. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1747. .dcache_bsize = 32,
  1748. .cpu_setup = __setup_cpu_e200,
  1749. .machine_check = machine_check_e200,
  1750. .platform = "ppc5554",
  1751. }
  1752. #endif /* CONFIG_E200 */
  1753. #ifdef CONFIG_E500
  1754. { /* e500 */
  1755. .pvr_mask = 0xffff0000,
  1756. .pvr_value = 0x80200000,
  1757. .cpu_name = "e500",
  1758. .cpu_features = CPU_FTRS_E500,
  1759. .cpu_user_features = COMMON_USER_BOOKE |
  1760. PPC_FEATURE_HAS_SPE_COMP |
  1761. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1762. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1763. .icache_bsize = 32,
  1764. .dcache_bsize = 32,
  1765. .num_pmcs = 4,
  1766. .oprofile_cpu_type = "ppc/e500",
  1767. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1768. .cpu_setup = __setup_cpu_e500v1,
  1769. .machine_check = machine_check_e500,
  1770. .platform = "ppc8540",
  1771. },
  1772. { /* e500v2 */
  1773. .pvr_mask = 0xffff0000,
  1774. .pvr_value = 0x80210000,
  1775. .cpu_name = "e500v2",
  1776. .cpu_features = CPU_FTRS_E500_2,
  1777. .cpu_user_features = COMMON_USER_BOOKE |
  1778. PPC_FEATURE_HAS_SPE_COMP |
  1779. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1780. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1781. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  1782. .icache_bsize = 32,
  1783. .dcache_bsize = 32,
  1784. .num_pmcs = 4,
  1785. .oprofile_cpu_type = "ppc/e500",
  1786. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1787. .cpu_setup = __setup_cpu_e500v2,
  1788. .machine_check = machine_check_e500,
  1789. .platform = "ppc8548",
  1790. },
  1791. { /* e500mc */
  1792. .pvr_mask = 0xffff0000,
  1793. .pvr_value = 0x80230000,
  1794. .cpu_name = "e500mc",
  1795. .cpu_features = CPU_FTRS_E500MC,
  1796. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1797. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1798. MMU_FTR_USE_TLBILX,
  1799. .icache_bsize = 64,
  1800. .dcache_bsize = 64,
  1801. .num_pmcs = 4,
  1802. .oprofile_cpu_type = "ppc/e500", /* xxx - galak, e500mc? */
  1803. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1804. .cpu_setup = __setup_cpu_e500mc,
  1805. .machine_check = machine_check_e500,
  1806. .platform = "ppce500mc",
  1807. },
  1808. { /* default match */
  1809. .pvr_mask = 0x00000000,
  1810. .pvr_value = 0x00000000,
  1811. .cpu_name = "(generic E500 PPC)",
  1812. .cpu_features = CPU_FTRS_E500,
  1813. .cpu_user_features = COMMON_USER_BOOKE |
  1814. PPC_FEATURE_HAS_SPE_COMP |
  1815. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1816. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1817. .icache_bsize = 32,
  1818. .dcache_bsize = 32,
  1819. .machine_check = machine_check_e500,
  1820. .platform = "powerpc",
  1821. }
  1822. #endif /* CONFIG_E500 */
  1823. #endif /* CONFIG_PPC32 */
  1824. #ifdef CONFIG_PPC_BOOK3E_64
  1825. { /* This is a default entry to get going, to be replaced by
  1826. * a real one at some stage
  1827. */
  1828. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  1829. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  1830. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  1831. .pvr_mask = 0x00000000,
  1832. .pvr_value = 0x00000000,
  1833. .cpu_name = "Book3E",
  1834. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  1835. .cpu_user_features = COMMON_USER_PPC64,
  1836. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  1837. MMU_FTR_USE_TLBIVAX_BCAST |
  1838. MMU_FTR_LOCK_BCAST_INVAL,
  1839. .icache_bsize = 64,
  1840. .dcache_bsize = 64,
  1841. .num_pmcs = 0,
  1842. .machine_check = machine_check_generic,
  1843. .platform = "power6",
  1844. },
  1845. #endif
  1846. };
  1847. static struct cpu_spec the_cpu_spec;
  1848. static void __init setup_cpu_spec(unsigned long offset, struct cpu_spec *s)
  1849. {
  1850. struct cpu_spec *t = &the_cpu_spec;
  1851. struct cpu_spec old;
  1852. t = PTRRELOC(t);
  1853. old = *t;
  1854. /* Copy everything, then do fixups */
  1855. *t = *s;
  1856. /*
  1857. * If we are overriding a previous value derived from the real
  1858. * PVR with a new value obtained using a logical PVR value,
  1859. * don't modify the performance monitor fields.
  1860. */
  1861. if (old.num_pmcs && !s->num_pmcs) {
  1862. t->num_pmcs = old.num_pmcs;
  1863. t->pmc_type = old.pmc_type;
  1864. t->oprofile_type = old.oprofile_type;
  1865. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  1866. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  1867. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  1868. /*
  1869. * If we have passed through this logic once before and
  1870. * have pulled the default case because the real PVR was
  1871. * not found inside cpu_specs[], then we are possibly
  1872. * running in compatibility mode. In that case, let the
  1873. * oprofiler know which set of compatibility counters to
  1874. * pull from by making sure the oprofile_cpu_type string
  1875. * is set to that of compatibility mode. If the
  1876. * oprofile_cpu_type already has a value, then we are
  1877. * possibly overriding a real PVR with a logical one,
  1878. * and, in that case, keep the current value for
  1879. * oprofile_cpu_type.
  1880. */
  1881. if (old.oprofile_cpu_type != NULL) {
  1882. t->oprofile_cpu_type = old.oprofile_cpu_type;
  1883. t->oprofile_type = old.oprofile_type;
  1884. }
  1885. }
  1886. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  1887. /*
  1888. * Set the base platform string once; assumes
  1889. * we're called with real pvr first.
  1890. */
  1891. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  1892. *PTRRELOC(&powerpc_base_platform) = t->platform;
  1893. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  1894. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  1895. * that processor. I will consolidate that at a later time, for now,
  1896. * just use #ifdef. We also don't need to PTRRELOC the function
  1897. * pointer on ppc64 and booke as we are running at 0 in real mode
  1898. * on ppc64 and reloc_offset is always 0 on booke.
  1899. */
  1900. if (s->cpu_setup) {
  1901. s->cpu_setup(offset, s);
  1902. }
  1903. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  1904. }
  1905. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  1906. {
  1907. struct cpu_spec *s = cpu_specs;
  1908. int i;
  1909. s = PTRRELOC(s);
  1910. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  1911. if ((pvr & s->pvr_mask) == s->pvr_value) {
  1912. setup_cpu_spec(offset, s);
  1913. return s;
  1914. }
  1915. }
  1916. BUG();
  1917. return NULL;
  1918. }