prcm.c 4.1 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/prcm.c
  3. *
  4. * OMAP 24xx Power Reset and Clock Management (PRCM) functions
  5. *
  6. * Copyright (C) 2005 Nokia Corporation
  7. *
  8. * Written by Tony Lindgren <tony.lindgren@nokia.com>
  9. *
  10. * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/delay.h>
  21. #include <mach/common.h>
  22. #include <mach/prcm.h>
  23. #include "clock.h"
  24. #include "prm.h"
  25. #include "prm-regbits-24xx.h"
  26. static void __iomem *prm_base;
  27. static void __iomem *cm_base;
  28. #define MAX_MODULE_ENABLE_WAIT 100000
  29. u32 omap_prcm_get_reset_sources(void)
  30. {
  31. /* XXX This presumably needs modification for 34XX */
  32. return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
  33. }
  34. EXPORT_SYMBOL(omap_prcm_get_reset_sources);
  35. /* Resets clock rates and reboots the system. Only called from system.h */
  36. void omap_prcm_arch_reset(char mode)
  37. {
  38. s16 prcm_offs;
  39. omap2_clk_prepare_for_reboot();
  40. if (cpu_is_omap24xx())
  41. prcm_offs = WKUP_MOD;
  42. else if (cpu_is_omap34xx())
  43. prcm_offs = OMAP3430_GR_MOD;
  44. else
  45. WARN_ON(1);
  46. prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
  47. }
  48. static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
  49. {
  50. BUG_ON(!base);
  51. return __raw_readl(base + module + reg);
  52. }
  53. static inline void __omap_prcm_write(u32 value, void __iomem *base,
  54. s16 module, u16 reg)
  55. {
  56. BUG_ON(!base);
  57. __raw_writel(value, base + module + reg);
  58. }
  59. /* Read a register in a PRM module */
  60. u32 prm_read_mod_reg(s16 module, u16 idx)
  61. {
  62. return __omap_prcm_read(prm_base, module, idx);
  63. }
  64. EXPORT_SYMBOL(prm_read_mod_reg);
  65. /* Write into a register in a PRM module */
  66. void prm_write_mod_reg(u32 val, s16 module, u16 idx)
  67. {
  68. __omap_prcm_write(val, prm_base, module, idx);
  69. }
  70. EXPORT_SYMBOL(prm_write_mod_reg);
  71. /* Read-modify-write a register in a PRM module. Caller must lock */
  72. u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  73. {
  74. u32 v;
  75. v = prm_read_mod_reg(module, idx);
  76. v &= ~mask;
  77. v |= bits;
  78. prm_write_mod_reg(v, module, idx);
  79. return v;
  80. }
  81. EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
  82. /* Read a register in a CM module */
  83. u32 cm_read_mod_reg(s16 module, u16 idx)
  84. {
  85. return __omap_prcm_read(cm_base, module, idx);
  86. }
  87. EXPORT_SYMBOL(cm_read_mod_reg);
  88. /* Write into a register in a CM module */
  89. void cm_write_mod_reg(u32 val, s16 module, u16 idx)
  90. {
  91. __omap_prcm_write(val, cm_base, module, idx);
  92. }
  93. EXPORT_SYMBOL(cm_write_mod_reg);
  94. /* Read-modify-write a register in a CM module. Caller must lock */
  95. u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  96. {
  97. u32 v;
  98. v = cm_read_mod_reg(module, idx);
  99. v &= ~mask;
  100. v |= bits;
  101. cm_write_mod_reg(v, module, idx);
  102. return v;
  103. }
  104. EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
  105. /**
  106. * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
  107. * @reg: physical address of module IDLEST register
  108. * @mask: value to mask against to determine if the module is active
  109. * @name: name of the clock (for printk)
  110. *
  111. * Returns 1 if the module indicated readiness in time, or 0 if it
  112. * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
  113. */
  114. int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
  115. {
  116. int i = 0;
  117. int ena = 0;
  118. /*
  119. * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
  120. * 34xx reverses this, just to keep us on our toes
  121. */
  122. if (cpu_is_omap24xx())
  123. ena = mask;
  124. else if (cpu_is_omap34xx())
  125. ena = 0;
  126. else
  127. BUG();
  128. /* Wait for lock */
  129. while (((__raw_readl(reg) & mask) != ena) &&
  130. (i++ < MAX_MODULE_ENABLE_WAIT))
  131. udelay(1);
  132. if (i < MAX_MODULE_ENABLE_WAIT)
  133. pr_debug("cm: Module associated with clock %s ready after %d "
  134. "loops\n", name, i);
  135. else
  136. pr_err("cm: Module associated with clock %s didn't enable in "
  137. "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
  138. return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
  139. };
  140. void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
  141. {
  142. prm_base = omap2_globals->prm;
  143. cm_base = omap2_globals->cm;
  144. }