tests-interrupts.dtsi 1.1 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758
  1. / {
  2. testcase-data {
  3. interrupts {
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. test_intc0: intc0 {
  7. interrupt-controller;
  8. #interrupt-cells = <1>;
  9. };
  10. test_intc1: intc1 {
  11. interrupt-controller;
  12. #interrupt-cells = <3>;
  13. };
  14. test_intc2: intc2 {
  15. interrupt-controller;
  16. #interrupt-cells = <2>;
  17. };
  18. test_intmap0: intmap0 {
  19. #interrupt-cells = <1>;
  20. #address-cells = <0>;
  21. interrupt-map = <1 &test_intc0 9>,
  22. <2 &test_intc1 10 11 12>,
  23. <3 &test_intc2 13 14>,
  24. <4 &test_intc2 15 16>;
  25. };
  26. test_intmap1: intmap1 {
  27. #interrupt-cells = <2>;
  28. interrupt-map = <0x5000 1 2 &test_intc0 15>;
  29. };
  30. interrupts0 {
  31. interrupt-parent = <&test_intc0>;
  32. interrupts = <1>, <2>, <3>, <4>;
  33. };
  34. interrupts1 {
  35. interrupt-parent = <&test_intmap0>;
  36. interrupts = <1>, <2>, <3>, <4>;
  37. };
  38. interrupts-extended0 {
  39. reg = <0x5000 0x100>;
  40. interrupts-extended = <&test_intc0 1>,
  41. <&test_intc1 2 3 4>,
  42. <&test_intc2 5 6>,
  43. <&test_intmap0 1>,
  44. <&test_intmap0 2>,
  45. <&test_intmap0 3>,
  46. <&test_intmap1 1 2>;
  47. };
  48. };
  49. };
  50. };