intel_sdvo.c 80 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633
  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "drm_crtc.h"
  35. #include "drm_edid.h"
  36. #include "intel_drv.h"
  37. #include "i915_drm.h"
  38. #include "i915_drv.h"
  39. #include "intel_sdvo_regs.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  51. static const char *tv_format_names[] = {
  52. "NTSC_M" , "NTSC_J" , "NTSC_443",
  53. "PAL_B" , "PAL_D" , "PAL_G" ,
  54. "PAL_H" , "PAL_I" , "PAL_M" ,
  55. "PAL_N" , "PAL_NC" , "PAL_60" ,
  56. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  57. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  58. "SECAM_60"
  59. };
  60. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  61. struct intel_sdvo {
  62. struct intel_encoder base;
  63. struct i2c_adapter *i2c;
  64. u8 slave_addr;
  65. struct i2c_adapter ddc;
  66. /* Register for the SDVO device: SDVOB or SDVOC */
  67. uint32_t sdvo_reg;
  68. /* Active outputs controlled by this SDVO output */
  69. uint16_t controlled_output;
  70. /*
  71. * Capabilities of the SDVO device returned by
  72. * i830_sdvo_get_capabilities()
  73. */
  74. struct intel_sdvo_caps caps;
  75. /* Pixel clock limitations reported by the SDVO device, in kHz */
  76. int pixel_clock_min, pixel_clock_max;
  77. /*
  78. * For multiple function SDVO device,
  79. * this is for current attached outputs.
  80. */
  81. uint16_t attached_output;
  82. /*
  83. * Hotplug activation bits for this device
  84. */
  85. uint8_t hotplug_active[2];
  86. /**
  87. * This is used to select the color range of RBG outputs in HDMI mode.
  88. * It is only valid when using TMDS encoding and 8 bit per color mode.
  89. */
  90. uint32_t color_range;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. /**
  110. * This is set if we detect output of sdvo device as LVDS and
  111. * have a valid fixed mode to use with the panel.
  112. */
  113. bool is_lvds;
  114. /**
  115. * This is sdvo fixed pannel mode pointer
  116. */
  117. struct drm_display_mode *sdvo_lvds_fixed_mode;
  118. /* DDC bus used by this SDVO encoder */
  119. uint8_t ddc_bus;
  120. };
  121. struct intel_sdvo_connector {
  122. struct intel_connector base;
  123. /* Mark the type of connector */
  124. uint16_t output_flag;
  125. enum hdmi_force_audio force_audio;
  126. /* This contains all current supported TV format */
  127. u8 tv_format_supported[TV_FORMAT_NUM];
  128. int format_supported_num;
  129. struct drm_property *tv_format;
  130. /* add the property for the SDVO-TV */
  131. struct drm_property *left;
  132. struct drm_property *right;
  133. struct drm_property *top;
  134. struct drm_property *bottom;
  135. struct drm_property *hpos;
  136. struct drm_property *vpos;
  137. struct drm_property *contrast;
  138. struct drm_property *saturation;
  139. struct drm_property *hue;
  140. struct drm_property *sharpness;
  141. struct drm_property *flicker_filter;
  142. struct drm_property *flicker_filter_adaptive;
  143. struct drm_property *flicker_filter_2d;
  144. struct drm_property *tv_chroma_filter;
  145. struct drm_property *tv_luma_filter;
  146. struct drm_property *dot_crawl;
  147. /* add the property for the SDVO-TV/LVDS */
  148. struct drm_property *brightness;
  149. /* Add variable to record current setting for the above property */
  150. u32 left_margin, right_margin, top_margin, bottom_margin;
  151. /* this is to get the range of margin.*/
  152. u32 max_hscan, max_vscan;
  153. u32 max_hpos, cur_hpos;
  154. u32 max_vpos, cur_vpos;
  155. u32 cur_brightness, max_brightness;
  156. u32 cur_contrast, max_contrast;
  157. u32 cur_saturation, max_saturation;
  158. u32 cur_hue, max_hue;
  159. u32 cur_sharpness, max_sharpness;
  160. u32 cur_flicker_filter, max_flicker_filter;
  161. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  162. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  163. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  164. u32 cur_tv_luma_filter, max_tv_luma_filter;
  165. u32 cur_dot_crawl, max_dot_crawl;
  166. };
  167. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  168. {
  169. return container_of(encoder, struct intel_sdvo, base.base);
  170. }
  171. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  172. {
  173. return container_of(intel_attached_encoder(connector),
  174. struct intel_sdvo, base);
  175. }
  176. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  177. {
  178. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  179. }
  180. static bool
  181. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  182. static bool
  183. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  184. struct intel_sdvo_connector *intel_sdvo_connector,
  185. int type);
  186. static bool
  187. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  188. struct intel_sdvo_connector *intel_sdvo_connector);
  189. /**
  190. * Writes the SDVOB or SDVOC with the given value, but always writes both
  191. * SDVOB and SDVOC to work around apparent hardware issues (according to
  192. * comments in the BIOS).
  193. */
  194. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  195. {
  196. struct drm_device *dev = intel_sdvo->base.base.dev;
  197. struct drm_i915_private *dev_priv = dev->dev_private;
  198. u32 bval = val, cval = val;
  199. int i;
  200. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  201. I915_WRITE(intel_sdvo->sdvo_reg, val);
  202. I915_READ(intel_sdvo->sdvo_reg);
  203. return;
  204. }
  205. if (intel_sdvo->sdvo_reg == SDVOB) {
  206. cval = I915_READ(SDVOC);
  207. } else {
  208. bval = I915_READ(SDVOB);
  209. }
  210. /*
  211. * Write the registers twice for luck. Sometimes,
  212. * writing them only once doesn't appear to 'stick'.
  213. * The BIOS does this too. Yay, magic
  214. */
  215. for (i = 0; i < 2; i++)
  216. {
  217. I915_WRITE(SDVOB, bval);
  218. I915_READ(SDVOB);
  219. I915_WRITE(SDVOC, cval);
  220. I915_READ(SDVOC);
  221. }
  222. }
  223. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  224. {
  225. struct i2c_msg msgs[] = {
  226. {
  227. .addr = intel_sdvo->slave_addr,
  228. .flags = 0,
  229. .len = 1,
  230. .buf = &addr,
  231. },
  232. {
  233. .addr = intel_sdvo->slave_addr,
  234. .flags = I2C_M_RD,
  235. .len = 1,
  236. .buf = ch,
  237. }
  238. };
  239. int ret;
  240. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  241. return true;
  242. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  243. return false;
  244. }
  245. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  246. /** Mapping of command numbers to names, for debug output */
  247. static const struct _sdvo_cmd_name {
  248. u8 cmd;
  249. const char *name;
  250. } sdvo_cmd_names[] = {
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  294. /* Add the op code for SDVO enhancements */
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  339. /* HDMI op code */
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  360. };
  361. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  362. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  363. const void *args, int args_len)
  364. {
  365. int i;
  366. DRM_DEBUG_KMS("%s: W: %02X ",
  367. SDVO_NAME(intel_sdvo), cmd);
  368. for (i = 0; i < args_len; i++)
  369. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  370. for (; i < 8; i++)
  371. DRM_LOG_KMS(" ");
  372. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  373. if (cmd == sdvo_cmd_names[i].cmd) {
  374. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  375. break;
  376. }
  377. }
  378. if (i == ARRAY_SIZE(sdvo_cmd_names))
  379. DRM_LOG_KMS("(%02X)", cmd);
  380. DRM_LOG_KMS("\n");
  381. }
  382. static const char *cmd_status_names[] = {
  383. "Power on",
  384. "Success",
  385. "Not supported",
  386. "Invalid arg",
  387. "Pending",
  388. "Target not specified",
  389. "Scaling not supported"
  390. };
  391. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  392. const void *args, int args_len)
  393. {
  394. u8 *buf, status;
  395. struct i2c_msg *msgs;
  396. int i, ret = true;
  397. /* Would be simpler to allocate both in one go ? */
  398. buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
  399. if (!buf)
  400. return false;
  401. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  402. if (!msgs) {
  403. kfree(buf);
  404. return false;
  405. }
  406. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  407. for (i = 0; i < args_len; i++) {
  408. msgs[i].addr = intel_sdvo->slave_addr;
  409. msgs[i].flags = 0;
  410. msgs[i].len = 2;
  411. msgs[i].buf = buf + 2 *i;
  412. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  413. buf[2*i + 1] = ((u8*)args)[i];
  414. }
  415. msgs[i].addr = intel_sdvo->slave_addr;
  416. msgs[i].flags = 0;
  417. msgs[i].len = 2;
  418. msgs[i].buf = buf + 2*i;
  419. buf[2*i + 0] = SDVO_I2C_OPCODE;
  420. buf[2*i + 1] = cmd;
  421. /* the following two are to read the response */
  422. status = SDVO_I2C_CMD_STATUS;
  423. msgs[i+1].addr = intel_sdvo->slave_addr;
  424. msgs[i+1].flags = 0;
  425. msgs[i+1].len = 1;
  426. msgs[i+1].buf = &status;
  427. msgs[i+2].addr = intel_sdvo->slave_addr;
  428. msgs[i+2].flags = I2C_M_RD;
  429. msgs[i+2].len = 1;
  430. msgs[i+2].buf = &status;
  431. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  432. if (ret < 0) {
  433. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  434. ret = false;
  435. goto out;
  436. }
  437. if (ret != i+3) {
  438. /* failure in I2C transfer */
  439. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  440. ret = false;
  441. }
  442. out:
  443. kfree(msgs);
  444. kfree(buf);
  445. return ret;
  446. }
  447. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  448. void *response, int response_len)
  449. {
  450. u8 retry = 5;
  451. u8 status;
  452. int i;
  453. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  454. /*
  455. * The documentation states that all commands will be
  456. * processed within 15µs, and that we need only poll
  457. * the status byte a maximum of 3 times in order for the
  458. * command to be complete.
  459. *
  460. * Check 5 times in case the hardware failed to read the docs.
  461. */
  462. if (!intel_sdvo_read_byte(intel_sdvo,
  463. SDVO_I2C_CMD_STATUS,
  464. &status))
  465. goto log_fail;
  466. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  467. udelay(15);
  468. if (!intel_sdvo_read_byte(intel_sdvo,
  469. SDVO_I2C_CMD_STATUS,
  470. &status))
  471. goto log_fail;
  472. }
  473. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  474. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  475. else
  476. DRM_LOG_KMS("(??? %d)", status);
  477. if (status != SDVO_CMD_STATUS_SUCCESS)
  478. goto log_fail;
  479. /* Read the command response */
  480. for (i = 0; i < response_len; i++) {
  481. if (!intel_sdvo_read_byte(intel_sdvo,
  482. SDVO_I2C_RETURN_0 + i,
  483. &((u8 *)response)[i]))
  484. goto log_fail;
  485. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  486. }
  487. DRM_LOG_KMS("\n");
  488. return true;
  489. log_fail:
  490. DRM_LOG_KMS("... failed\n");
  491. return false;
  492. }
  493. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  494. {
  495. if (mode->clock >= 100000)
  496. return 1;
  497. else if (mode->clock >= 50000)
  498. return 2;
  499. else
  500. return 4;
  501. }
  502. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  503. u8 ddc_bus)
  504. {
  505. /* This must be the immediately preceding write before the i2c xfer */
  506. return intel_sdvo_write_cmd(intel_sdvo,
  507. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  508. &ddc_bus, 1);
  509. }
  510. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  511. {
  512. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  513. return false;
  514. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  515. }
  516. static bool
  517. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  518. {
  519. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  520. return false;
  521. return intel_sdvo_read_response(intel_sdvo, value, len);
  522. }
  523. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  524. {
  525. struct intel_sdvo_set_target_input_args targets = {0};
  526. return intel_sdvo_set_value(intel_sdvo,
  527. SDVO_CMD_SET_TARGET_INPUT,
  528. &targets, sizeof(targets));
  529. }
  530. /**
  531. * Return whether each input is trained.
  532. *
  533. * This function is making an assumption about the layout of the response,
  534. * which should be checked against the docs.
  535. */
  536. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  537. {
  538. struct intel_sdvo_get_trained_inputs_response response;
  539. BUILD_BUG_ON(sizeof(response) != 1);
  540. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  541. &response, sizeof(response)))
  542. return false;
  543. *input_1 = response.input0_trained;
  544. *input_2 = response.input1_trained;
  545. return true;
  546. }
  547. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  548. u16 outputs)
  549. {
  550. return intel_sdvo_set_value(intel_sdvo,
  551. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  552. &outputs, sizeof(outputs));
  553. }
  554. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  555. int mode)
  556. {
  557. u8 state = SDVO_ENCODER_STATE_ON;
  558. switch (mode) {
  559. case DRM_MODE_DPMS_ON:
  560. state = SDVO_ENCODER_STATE_ON;
  561. break;
  562. case DRM_MODE_DPMS_STANDBY:
  563. state = SDVO_ENCODER_STATE_STANDBY;
  564. break;
  565. case DRM_MODE_DPMS_SUSPEND:
  566. state = SDVO_ENCODER_STATE_SUSPEND;
  567. break;
  568. case DRM_MODE_DPMS_OFF:
  569. state = SDVO_ENCODER_STATE_OFF;
  570. break;
  571. }
  572. return intel_sdvo_set_value(intel_sdvo,
  573. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  574. }
  575. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  576. int *clock_min,
  577. int *clock_max)
  578. {
  579. struct intel_sdvo_pixel_clock_range clocks;
  580. BUILD_BUG_ON(sizeof(clocks) != 4);
  581. if (!intel_sdvo_get_value(intel_sdvo,
  582. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  583. &clocks, sizeof(clocks)))
  584. return false;
  585. /* Convert the values from units of 10 kHz to kHz. */
  586. *clock_min = clocks.min * 10;
  587. *clock_max = clocks.max * 10;
  588. return true;
  589. }
  590. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  591. u16 outputs)
  592. {
  593. return intel_sdvo_set_value(intel_sdvo,
  594. SDVO_CMD_SET_TARGET_OUTPUT,
  595. &outputs, sizeof(outputs));
  596. }
  597. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  598. struct intel_sdvo_dtd *dtd)
  599. {
  600. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  601. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  602. }
  603. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  604. struct intel_sdvo_dtd *dtd)
  605. {
  606. return intel_sdvo_set_timing(intel_sdvo,
  607. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  608. }
  609. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  610. struct intel_sdvo_dtd *dtd)
  611. {
  612. return intel_sdvo_set_timing(intel_sdvo,
  613. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  614. }
  615. static bool
  616. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  617. uint16_t clock,
  618. uint16_t width,
  619. uint16_t height)
  620. {
  621. struct intel_sdvo_preferred_input_timing_args args;
  622. memset(&args, 0, sizeof(args));
  623. args.clock = clock;
  624. args.width = width;
  625. args.height = height;
  626. args.interlace = 0;
  627. if (intel_sdvo->is_lvds &&
  628. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  629. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  630. args.scaled = 1;
  631. return intel_sdvo_set_value(intel_sdvo,
  632. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  633. &args, sizeof(args));
  634. }
  635. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  636. struct intel_sdvo_dtd *dtd)
  637. {
  638. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  639. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  640. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  641. &dtd->part1, sizeof(dtd->part1)) &&
  642. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  643. &dtd->part2, sizeof(dtd->part2));
  644. }
  645. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  646. {
  647. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  648. }
  649. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  650. const struct drm_display_mode *mode)
  651. {
  652. uint16_t width, height;
  653. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  654. uint16_t h_sync_offset, v_sync_offset;
  655. int mode_clock;
  656. width = mode->hdisplay;
  657. height = mode->vdisplay;
  658. /* do some mode translations */
  659. h_blank_len = mode->htotal - mode->hdisplay;
  660. h_sync_len = mode->hsync_end - mode->hsync_start;
  661. v_blank_len = mode->vtotal - mode->vdisplay;
  662. v_sync_len = mode->vsync_end - mode->vsync_start;
  663. h_sync_offset = mode->hsync_start - mode->hdisplay;
  664. v_sync_offset = mode->vsync_start - mode->vdisplay;
  665. mode_clock = mode->clock;
  666. mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
  667. mode_clock /= 10;
  668. dtd->part1.clock = mode_clock;
  669. dtd->part1.h_active = width & 0xff;
  670. dtd->part1.h_blank = h_blank_len & 0xff;
  671. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  672. ((h_blank_len >> 8) & 0xf);
  673. dtd->part1.v_active = height & 0xff;
  674. dtd->part1.v_blank = v_blank_len & 0xff;
  675. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  676. ((v_blank_len >> 8) & 0xf);
  677. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  678. dtd->part2.h_sync_width = h_sync_len & 0xff;
  679. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  680. (v_sync_len & 0xf);
  681. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  682. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  683. ((v_sync_len & 0x30) >> 4);
  684. dtd->part2.dtd_flags = 0x18;
  685. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  686. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  687. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  688. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  689. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  690. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  691. dtd->part2.sdvo_flags = 0;
  692. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  693. dtd->part2.reserved = 0;
  694. }
  695. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  696. const struct intel_sdvo_dtd *dtd)
  697. {
  698. mode->hdisplay = dtd->part1.h_active;
  699. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  700. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  701. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  702. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  703. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  704. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  705. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  706. mode->vdisplay = dtd->part1.v_active;
  707. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  708. mode->vsync_start = mode->vdisplay;
  709. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  710. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  711. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  712. mode->vsync_end = mode->vsync_start +
  713. (dtd->part2.v_sync_off_width & 0xf);
  714. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  715. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  716. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  717. mode->clock = dtd->part1.clock * 10;
  718. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  719. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  720. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  721. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  722. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  723. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  724. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  725. }
  726. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  727. {
  728. struct intel_sdvo_encode encode;
  729. BUILD_BUG_ON(sizeof(encode) != 2);
  730. return intel_sdvo_get_value(intel_sdvo,
  731. SDVO_CMD_GET_SUPP_ENCODE,
  732. &encode, sizeof(encode));
  733. }
  734. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  735. uint8_t mode)
  736. {
  737. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  738. }
  739. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  740. uint8_t mode)
  741. {
  742. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  743. }
  744. #if 0
  745. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  746. {
  747. int i, j;
  748. uint8_t set_buf_index[2];
  749. uint8_t av_split;
  750. uint8_t buf_size;
  751. uint8_t buf[48];
  752. uint8_t *pos;
  753. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  754. for (i = 0; i <= av_split; i++) {
  755. set_buf_index[0] = i; set_buf_index[1] = 0;
  756. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  757. set_buf_index, 2);
  758. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  759. intel_sdvo_read_response(encoder, &buf_size, 1);
  760. pos = buf;
  761. for (j = 0; j <= buf_size; j += 8) {
  762. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  763. NULL, 0);
  764. intel_sdvo_read_response(encoder, pos, 8);
  765. pos += 8;
  766. }
  767. }
  768. }
  769. #endif
  770. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  771. {
  772. struct dip_infoframe avi_if = {
  773. .type = DIP_TYPE_AVI,
  774. .ver = DIP_VERSION_AVI,
  775. .len = DIP_LEN_AVI,
  776. };
  777. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  778. uint8_t set_buf_index[2] = { 1, 0 };
  779. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  780. uint64_t *data = (uint64_t *)sdvo_data;
  781. unsigned i;
  782. intel_dip_infoframe_csum(&avi_if);
  783. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  784. * we must not send the ecc field, either. */
  785. memcpy(sdvo_data, &avi_if, 3);
  786. sdvo_data[3] = avi_if.checksum;
  787. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  788. if (!intel_sdvo_set_value(intel_sdvo,
  789. SDVO_CMD_SET_HBUF_INDEX,
  790. set_buf_index, 2))
  791. return false;
  792. for (i = 0; i < sizeof(sdvo_data); i += 8) {
  793. if (!intel_sdvo_set_value(intel_sdvo,
  794. SDVO_CMD_SET_HBUF_DATA,
  795. data, 8))
  796. return false;
  797. data++;
  798. }
  799. return intel_sdvo_set_value(intel_sdvo,
  800. SDVO_CMD_SET_HBUF_TXRATE,
  801. &tx_rate, 1);
  802. }
  803. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  804. {
  805. struct intel_sdvo_tv_format format;
  806. uint32_t format_map;
  807. format_map = 1 << intel_sdvo->tv_format_index;
  808. memset(&format, 0, sizeof(format));
  809. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  810. BUILD_BUG_ON(sizeof(format) != 6);
  811. return intel_sdvo_set_value(intel_sdvo,
  812. SDVO_CMD_SET_TV_FORMAT,
  813. &format, sizeof(format));
  814. }
  815. static bool
  816. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  817. const struct drm_display_mode *mode)
  818. {
  819. struct intel_sdvo_dtd output_dtd;
  820. if (!intel_sdvo_set_target_output(intel_sdvo,
  821. intel_sdvo->attached_output))
  822. return false;
  823. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  824. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  825. return false;
  826. return true;
  827. }
  828. /* Asks the sdvo controller for the preferred input mode given the output mode.
  829. * Unfortunately we have to set up the full output mode to do that. */
  830. static bool
  831. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  832. const struct drm_display_mode *mode,
  833. struct drm_display_mode *adjusted_mode)
  834. {
  835. struct intel_sdvo_dtd input_dtd;
  836. /* Reset the input timing to the screen. Assume always input 0. */
  837. if (!intel_sdvo_set_target_input(intel_sdvo))
  838. return false;
  839. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  840. mode->clock / 10,
  841. mode->hdisplay,
  842. mode->vdisplay))
  843. return false;
  844. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  845. &input_dtd))
  846. return false;
  847. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  848. return true;
  849. }
  850. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  851. const struct drm_display_mode *mode,
  852. struct drm_display_mode *adjusted_mode)
  853. {
  854. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  855. int multiplier;
  856. /* We need to construct preferred input timings based on our
  857. * output timings. To do that, we have to set the output
  858. * timings, even though this isn't really the right place in
  859. * the sequence to do it. Oh well.
  860. */
  861. if (intel_sdvo->is_tv) {
  862. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  863. return false;
  864. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  865. mode,
  866. adjusted_mode);
  867. } else if (intel_sdvo->is_lvds) {
  868. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  869. intel_sdvo->sdvo_lvds_fixed_mode))
  870. return false;
  871. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  872. mode,
  873. adjusted_mode);
  874. }
  875. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  876. * SDVO device will factor out the multiplier during mode_set.
  877. */
  878. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  879. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  880. return true;
  881. }
  882. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  883. struct drm_display_mode *mode,
  884. struct drm_display_mode *adjusted_mode)
  885. {
  886. struct drm_device *dev = encoder->dev;
  887. struct drm_i915_private *dev_priv = dev->dev_private;
  888. struct drm_crtc *crtc = encoder->crtc;
  889. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  890. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  891. u32 sdvox;
  892. struct intel_sdvo_in_out_map in_out;
  893. struct intel_sdvo_dtd input_dtd, output_dtd;
  894. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  895. int rate;
  896. if (!mode)
  897. return;
  898. /* First, set the input mapping for the first input to our controlled
  899. * output. This is only correct if we're a single-input device, in
  900. * which case the first input is the output from the appropriate SDVO
  901. * channel on the motherboard. In a two-input device, the first input
  902. * will be SDVOB and the second SDVOC.
  903. */
  904. in_out.in0 = intel_sdvo->attached_output;
  905. in_out.in1 = 0;
  906. intel_sdvo_set_value(intel_sdvo,
  907. SDVO_CMD_SET_IN_OUT_MAP,
  908. &in_out, sizeof(in_out));
  909. /* Set the output timings to the screen */
  910. if (!intel_sdvo_set_target_output(intel_sdvo,
  911. intel_sdvo->attached_output))
  912. return;
  913. /* lvds has a special fixed output timing. */
  914. if (intel_sdvo->is_lvds)
  915. intel_sdvo_get_dtd_from_mode(&output_dtd,
  916. intel_sdvo->sdvo_lvds_fixed_mode);
  917. else
  918. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  919. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  920. DRM_INFO("Setting output timings on %s failed\n",
  921. SDVO_NAME(intel_sdvo));
  922. /* Set the input timing to the screen. Assume always input 0. */
  923. if (!intel_sdvo_set_target_input(intel_sdvo))
  924. return;
  925. if (intel_sdvo->has_hdmi_monitor) {
  926. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  927. intel_sdvo_set_colorimetry(intel_sdvo,
  928. SDVO_COLORIMETRY_RGB256);
  929. intel_sdvo_set_avi_infoframe(intel_sdvo);
  930. } else
  931. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  932. if (intel_sdvo->is_tv &&
  933. !intel_sdvo_set_tv_format(intel_sdvo))
  934. return;
  935. /* We have tried to get input timing in mode_fixup, and filled into
  936. * adjusted_mode.
  937. */
  938. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  939. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  940. DRM_INFO("Setting input timings on %s failed\n",
  941. SDVO_NAME(intel_sdvo));
  942. switch (pixel_multiplier) {
  943. default:
  944. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  945. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  946. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  947. }
  948. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  949. return;
  950. /* Set the SDVO control regs. */
  951. if (INTEL_INFO(dev)->gen >= 4) {
  952. /* The real mode polarity is set by the SDVO commands, using
  953. * struct intel_sdvo_dtd. */
  954. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  955. if (intel_sdvo->is_hdmi)
  956. sdvox |= intel_sdvo->color_range;
  957. if (INTEL_INFO(dev)->gen < 5)
  958. sdvox |= SDVO_BORDER_ENABLE;
  959. } else {
  960. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  961. switch (intel_sdvo->sdvo_reg) {
  962. case SDVOB:
  963. sdvox &= SDVOB_PRESERVE_MASK;
  964. break;
  965. case SDVOC:
  966. sdvox &= SDVOC_PRESERVE_MASK;
  967. break;
  968. }
  969. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  970. }
  971. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  972. sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
  973. else
  974. sdvox |= TRANSCODER(intel_crtc->pipe);
  975. if (intel_sdvo->has_hdmi_audio)
  976. sdvox |= SDVO_AUDIO_ENABLE;
  977. if (INTEL_INFO(dev)->gen >= 4) {
  978. /* done in crtc_mode_set as the dpll_md reg must be written early */
  979. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  980. /* done in crtc_mode_set as it lives inside the dpll register */
  981. } else {
  982. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  983. }
  984. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  985. INTEL_INFO(dev)->gen < 5)
  986. sdvox |= SDVO_STALL_SELECT;
  987. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  988. }
  989. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  990. {
  991. struct drm_device *dev = encoder->dev;
  992. struct drm_i915_private *dev_priv = dev->dev_private;
  993. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  994. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  995. u32 temp;
  996. if (mode != DRM_MODE_DPMS_ON) {
  997. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  998. if (0)
  999. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1000. if (mode == DRM_MODE_DPMS_OFF) {
  1001. temp = I915_READ(intel_sdvo->sdvo_reg);
  1002. if ((temp & SDVO_ENABLE) != 0) {
  1003. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1004. }
  1005. }
  1006. } else {
  1007. bool input1, input2;
  1008. int i;
  1009. u8 status;
  1010. temp = I915_READ(intel_sdvo->sdvo_reg);
  1011. if ((temp & SDVO_ENABLE) == 0)
  1012. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1013. for (i = 0; i < 2; i++)
  1014. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1015. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1016. /* Warn if the device reported failure to sync.
  1017. * A lot of SDVO devices fail to notify of sync, but it's
  1018. * a given it the status is a success, we succeeded.
  1019. */
  1020. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1021. DRM_DEBUG_KMS("First %s output reported failure to "
  1022. "sync\n", SDVO_NAME(intel_sdvo));
  1023. }
  1024. if (0)
  1025. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1026. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1027. }
  1028. return;
  1029. }
  1030. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1031. struct drm_display_mode *mode)
  1032. {
  1033. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1034. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1035. return MODE_NO_DBLESCAN;
  1036. if (intel_sdvo->pixel_clock_min > mode->clock)
  1037. return MODE_CLOCK_LOW;
  1038. if (intel_sdvo->pixel_clock_max < mode->clock)
  1039. return MODE_CLOCK_HIGH;
  1040. if (intel_sdvo->is_lvds) {
  1041. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1042. return MODE_PANEL;
  1043. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1044. return MODE_PANEL;
  1045. }
  1046. return MODE_OK;
  1047. }
  1048. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1049. {
  1050. BUILD_BUG_ON(sizeof(*caps) != 8);
  1051. if (!intel_sdvo_get_value(intel_sdvo,
  1052. SDVO_CMD_GET_DEVICE_CAPS,
  1053. caps, sizeof(*caps)))
  1054. return false;
  1055. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1056. " vendor_id: %d\n"
  1057. " device_id: %d\n"
  1058. " device_rev_id: %d\n"
  1059. " sdvo_version_major: %d\n"
  1060. " sdvo_version_minor: %d\n"
  1061. " sdvo_inputs_mask: %d\n"
  1062. " smooth_scaling: %d\n"
  1063. " sharp_scaling: %d\n"
  1064. " up_scaling: %d\n"
  1065. " down_scaling: %d\n"
  1066. " stall_support: %d\n"
  1067. " output_flags: %d\n",
  1068. caps->vendor_id,
  1069. caps->device_id,
  1070. caps->device_rev_id,
  1071. caps->sdvo_version_major,
  1072. caps->sdvo_version_minor,
  1073. caps->sdvo_inputs_mask,
  1074. caps->smooth_scaling,
  1075. caps->sharp_scaling,
  1076. caps->up_scaling,
  1077. caps->down_scaling,
  1078. caps->stall_support,
  1079. caps->output_flags);
  1080. return true;
  1081. }
  1082. static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
  1083. {
  1084. struct drm_device *dev = intel_sdvo->base.base.dev;
  1085. u8 response[2];
  1086. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1087. * on the line. */
  1088. if (IS_I945G(dev) || IS_I945GM(dev))
  1089. return false;
  1090. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1091. &response, 2) && response[0];
  1092. }
  1093. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1094. {
  1095. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1096. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
  1097. }
  1098. static bool
  1099. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1100. {
  1101. /* Is there more than one type of output? */
  1102. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1103. }
  1104. static struct edid *
  1105. intel_sdvo_get_edid(struct drm_connector *connector)
  1106. {
  1107. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1108. return drm_get_edid(connector, &sdvo->ddc);
  1109. }
  1110. /* Mac mini hack -- use the same DDC as the analog connector */
  1111. static struct edid *
  1112. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1113. {
  1114. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1115. return drm_get_edid(connector,
  1116. intel_gmbus_get_adapter(dev_priv,
  1117. dev_priv->crt_ddc_pin));
  1118. }
  1119. static enum drm_connector_status
  1120. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1121. {
  1122. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1123. enum drm_connector_status status;
  1124. struct edid *edid;
  1125. edid = intel_sdvo_get_edid(connector);
  1126. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1127. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1128. /*
  1129. * Don't use the 1 as the argument of DDC bus switch to get
  1130. * the EDID. It is used for SDVO SPD ROM.
  1131. */
  1132. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1133. intel_sdvo->ddc_bus = ddc;
  1134. edid = intel_sdvo_get_edid(connector);
  1135. if (edid)
  1136. break;
  1137. }
  1138. /*
  1139. * If we found the EDID on the other bus,
  1140. * assume that is the correct DDC bus.
  1141. */
  1142. if (edid == NULL)
  1143. intel_sdvo->ddc_bus = saved_ddc;
  1144. }
  1145. /*
  1146. * When there is no edid and no monitor is connected with VGA
  1147. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1148. */
  1149. if (edid == NULL)
  1150. edid = intel_sdvo_get_analog_edid(connector);
  1151. status = connector_status_unknown;
  1152. if (edid != NULL) {
  1153. /* DDC bus is shared, match EDID to connector type */
  1154. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1155. status = connector_status_connected;
  1156. if (intel_sdvo->is_hdmi) {
  1157. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1158. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1159. }
  1160. } else
  1161. status = connector_status_disconnected;
  1162. connector->display_info.raw_edid = NULL;
  1163. kfree(edid);
  1164. }
  1165. if (status == connector_status_connected) {
  1166. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1167. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1168. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1169. }
  1170. return status;
  1171. }
  1172. static bool
  1173. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1174. struct edid *edid)
  1175. {
  1176. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1177. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1178. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1179. connector_is_digital, monitor_is_digital);
  1180. return connector_is_digital == monitor_is_digital;
  1181. }
  1182. static enum drm_connector_status
  1183. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1184. {
  1185. uint16_t response;
  1186. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1187. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1188. enum drm_connector_status ret;
  1189. if (!intel_sdvo_write_cmd(intel_sdvo,
  1190. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1191. return connector_status_unknown;
  1192. /* add 30ms delay when the output type might be TV */
  1193. if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
  1194. msleep(30);
  1195. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1196. return connector_status_unknown;
  1197. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1198. response & 0xff, response >> 8,
  1199. intel_sdvo_connector->output_flag);
  1200. if (response == 0)
  1201. return connector_status_disconnected;
  1202. intel_sdvo->attached_output = response;
  1203. intel_sdvo->has_hdmi_monitor = false;
  1204. intel_sdvo->has_hdmi_audio = false;
  1205. if ((intel_sdvo_connector->output_flag & response) == 0)
  1206. ret = connector_status_disconnected;
  1207. else if (IS_TMDS(intel_sdvo_connector))
  1208. ret = intel_sdvo_tmds_sink_detect(connector);
  1209. else {
  1210. struct edid *edid;
  1211. /* if we have an edid check it matches the connection */
  1212. edid = intel_sdvo_get_edid(connector);
  1213. if (edid == NULL)
  1214. edid = intel_sdvo_get_analog_edid(connector);
  1215. if (edid != NULL) {
  1216. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1217. edid))
  1218. ret = connector_status_connected;
  1219. else
  1220. ret = connector_status_disconnected;
  1221. connector->display_info.raw_edid = NULL;
  1222. kfree(edid);
  1223. } else
  1224. ret = connector_status_connected;
  1225. }
  1226. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1227. if (ret == connector_status_connected) {
  1228. intel_sdvo->is_tv = false;
  1229. intel_sdvo->is_lvds = false;
  1230. intel_sdvo->base.needs_tv_clock = false;
  1231. if (response & SDVO_TV_MASK) {
  1232. intel_sdvo->is_tv = true;
  1233. intel_sdvo->base.needs_tv_clock = true;
  1234. }
  1235. if (response & SDVO_LVDS_MASK)
  1236. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1237. }
  1238. return ret;
  1239. }
  1240. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1241. {
  1242. struct edid *edid;
  1243. /* set the bus switch and get the modes */
  1244. edid = intel_sdvo_get_edid(connector);
  1245. /*
  1246. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1247. * link between analog and digital outputs. So, if the regular SDVO
  1248. * DDC fails, check to see if the analog output is disconnected, in
  1249. * which case we'll look there for the digital DDC data.
  1250. */
  1251. if (edid == NULL)
  1252. edid = intel_sdvo_get_analog_edid(connector);
  1253. if (edid != NULL) {
  1254. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1255. edid)) {
  1256. drm_mode_connector_update_edid_property(connector, edid);
  1257. drm_add_edid_modes(connector, edid);
  1258. }
  1259. connector->display_info.raw_edid = NULL;
  1260. kfree(edid);
  1261. }
  1262. }
  1263. /*
  1264. * Set of SDVO TV modes.
  1265. * Note! This is in reply order (see loop in get_tv_modes).
  1266. * XXX: all 60Hz refresh?
  1267. */
  1268. static const struct drm_display_mode sdvo_tv_modes[] = {
  1269. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1270. 416, 0, 200, 201, 232, 233, 0,
  1271. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1272. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1273. 416, 0, 240, 241, 272, 273, 0,
  1274. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1275. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1276. 496, 0, 300, 301, 332, 333, 0,
  1277. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1278. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1279. 736, 0, 350, 351, 382, 383, 0,
  1280. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1281. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1282. 736, 0, 400, 401, 432, 433, 0,
  1283. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1284. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1285. 736, 0, 480, 481, 512, 513, 0,
  1286. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1287. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1288. 800, 0, 480, 481, 512, 513, 0,
  1289. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1290. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1291. 800, 0, 576, 577, 608, 609, 0,
  1292. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1293. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1294. 816, 0, 350, 351, 382, 383, 0,
  1295. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1296. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1297. 816, 0, 400, 401, 432, 433, 0,
  1298. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1299. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1300. 816, 0, 480, 481, 512, 513, 0,
  1301. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1302. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1303. 816, 0, 540, 541, 572, 573, 0,
  1304. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1305. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1306. 816, 0, 576, 577, 608, 609, 0,
  1307. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1308. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1309. 864, 0, 576, 577, 608, 609, 0,
  1310. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1311. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1312. 896, 0, 600, 601, 632, 633, 0,
  1313. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1314. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1315. 928, 0, 624, 625, 656, 657, 0,
  1316. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1317. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1318. 1016, 0, 766, 767, 798, 799, 0,
  1319. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1320. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1321. 1120, 0, 768, 769, 800, 801, 0,
  1322. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1323. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1324. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1325. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1326. };
  1327. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1328. {
  1329. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1330. struct intel_sdvo_sdtv_resolution_request tv_res;
  1331. uint32_t reply = 0, format_map = 0;
  1332. int i;
  1333. /* Read the list of supported input resolutions for the selected TV
  1334. * format.
  1335. */
  1336. format_map = 1 << intel_sdvo->tv_format_index;
  1337. memcpy(&tv_res, &format_map,
  1338. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1339. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1340. return;
  1341. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1342. if (!intel_sdvo_write_cmd(intel_sdvo,
  1343. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1344. &tv_res, sizeof(tv_res)))
  1345. return;
  1346. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1347. return;
  1348. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1349. if (reply & (1 << i)) {
  1350. struct drm_display_mode *nmode;
  1351. nmode = drm_mode_duplicate(connector->dev,
  1352. &sdvo_tv_modes[i]);
  1353. if (nmode)
  1354. drm_mode_probed_add(connector, nmode);
  1355. }
  1356. }
  1357. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1358. {
  1359. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1360. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1361. struct drm_display_mode *newmode;
  1362. /*
  1363. * Attempt to get the mode list from DDC.
  1364. * Assume that the preferred modes are
  1365. * arranged in priority order.
  1366. */
  1367. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1368. if (list_empty(&connector->probed_modes) == false)
  1369. goto end;
  1370. /* Fetch modes from VBT */
  1371. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1372. newmode = drm_mode_duplicate(connector->dev,
  1373. dev_priv->sdvo_lvds_vbt_mode);
  1374. if (newmode != NULL) {
  1375. /* Guarantee the mode is preferred */
  1376. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1377. DRM_MODE_TYPE_DRIVER);
  1378. drm_mode_probed_add(connector, newmode);
  1379. }
  1380. }
  1381. end:
  1382. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1383. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1384. intel_sdvo->sdvo_lvds_fixed_mode =
  1385. drm_mode_duplicate(connector->dev, newmode);
  1386. intel_sdvo->is_lvds = true;
  1387. break;
  1388. }
  1389. }
  1390. }
  1391. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1392. {
  1393. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1394. if (IS_TV(intel_sdvo_connector))
  1395. intel_sdvo_get_tv_modes(connector);
  1396. else if (IS_LVDS(intel_sdvo_connector))
  1397. intel_sdvo_get_lvds_modes(connector);
  1398. else
  1399. intel_sdvo_get_ddc_modes(connector);
  1400. return !list_empty(&connector->probed_modes);
  1401. }
  1402. static void
  1403. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1404. {
  1405. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1406. struct drm_device *dev = connector->dev;
  1407. if (intel_sdvo_connector->left)
  1408. drm_property_destroy(dev, intel_sdvo_connector->left);
  1409. if (intel_sdvo_connector->right)
  1410. drm_property_destroy(dev, intel_sdvo_connector->right);
  1411. if (intel_sdvo_connector->top)
  1412. drm_property_destroy(dev, intel_sdvo_connector->top);
  1413. if (intel_sdvo_connector->bottom)
  1414. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1415. if (intel_sdvo_connector->hpos)
  1416. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1417. if (intel_sdvo_connector->vpos)
  1418. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1419. if (intel_sdvo_connector->saturation)
  1420. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1421. if (intel_sdvo_connector->contrast)
  1422. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1423. if (intel_sdvo_connector->hue)
  1424. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1425. if (intel_sdvo_connector->sharpness)
  1426. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1427. if (intel_sdvo_connector->flicker_filter)
  1428. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1429. if (intel_sdvo_connector->flicker_filter_2d)
  1430. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1431. if (intel_sdvo_connector->flicker_filter_adaptive)
  1432. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1433. if (intel_sdvo_connector->tv_luma_filter)
  1434. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1435. if (intel_sdvo_connector->tv_chroma_filter)
  1436. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1437. if (intel_sdvo_connector->dot_crawl)
  1438. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1439. if (intel_sdvo_connector->brightness)
  1440. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1441. }
  1442. static void intel_sdvo_destroy(struct drm_connector *connector)
  1443. {
  1444. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1445. if (intel_sdvo_connector->tv_format)
  1446. drm_property_destroy(connector->dev,
  1447. intel_sdvo_connector->tv_format);
  1448. intel_sdvo_destroy_enhance_property(connector);
  1449. drm_sysfs_connector_remove(connector);
  1450. drm_connector_cleanup(connector);
  1451. kfree(connector);
  1452. }
  1453. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1454. {
  1455. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1456. struct edid *edid;
  1457. bool has_audio = false;
  1458. if (!intel_sdvo->is_hdmi)
  1459. return false;
  1460. edid = intel_sdvo_get_edid(connector);
  1461. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1462. has_audio = drm_detect_monitor_audio(edid);
  1463. return has_audio;
  1464. }
  1465. static int
  1466. intel_sdvo_set_property(struct drm_connector *connector,
  1467. struct drm_property *property,
  1468. uint64_t val)
  1469. {
  1470. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1471. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1472. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1473. uint16_t temp_value;
  1474. uint8_t cmd;
  1475. int ret;
  1476. ret = drm_connector_property_set_value(connector, property, val);
  1477. if (ret)
  1478. return ret;
  1479. if (property == dev_priv->force_audio_property) {
  1480. int i = val;
  1481. bool has_audio;
  1482. if (i == intel_sdvo_connector->force_audio)
  1483. return 0;
  1484. intel_sdvo_connector->force_audio = i;
  1485. if (i == HDMI_AUDIO_AUTO)
  1486. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1487. else
  1488. has_audio = (i == HDMI_AUDIO_ON);
  1489. if (has_audio == intel_sdvo->has_hdmi_audio)
  1490. return 0;
  1491. intel_sdvo->has_hdmi_audio = has_audio;
  1492. goto done;
  1493. }
  1494. if (property == dev_priv->broadcast_rgb_property) {
  1495. if (val == !!intel_sdvo->color_range)
  1496. return 0;
  1497. intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1498. goto done;
  1499. }
  1500. #define CHECK_PROPERTY(name, NAME) \
  1501. if (intel_sdvo_connector->name == property) { \
  1502. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1503. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1504. cmd = SDVO_CMD_SET_##NAME; \
  1505. intel_sdvo_connector->cur_##name = temp_value; \
  1506. goto set_value; \
  1507. }
  1508. if (property == intel_sdvo_connector->tv_format) {
  1509. if (val >= TV_FORMAT_NUM)
  1510. return -EINVAL;
  1511. if (intel_sdvo->tv_format_index ==
  1512. intel_sdvo_connector->tv_format_supported[val])
  1513. return 0;
  1514. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1515. goto done;
  1516. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1517. temp_value = val;
  1518. if (intel_sdvo_connector->left == property) {
  1519. drm_connector_property_set_value(connector,
  1520. intel_sdvo_connector->right, val);
  1521. if (intel_sdvo_connector->left_margin == temp_value)
  1522. return 0;
  1523. intel_sdvo_connector->left_margin = temp_value;
  1524. intel_sdvo_connector->right_margin = temp_value;
  1525. temp_value = intel_sdvo_connector->max_hscan -
  1526. intel_sdvo_connector->left_margin;
  1527. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1528. goto set_value;
  1529. } else if (intel_sdvo_connector->right == property) {
  1530. drm_connector_property_set_value(connector,
  1531. intel_sdvo_connector->left, val);
  1532. if (intel_sdvo_connector->right_margin == temp_value)
  1533. return 0;
  1534. intel_sdvo_connector->left_margin = temp_value;
  1535. intel_sdvo_connector->right_margin = temp_value;
  1536. temp_value = intel_sdvo_connector->max_hscan -
  1537. intel_sdvo_connector->left_margin;
  1538. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1539. goto set_value;
  1540. } else if (intel_sdvo_connector->top == property) {
  1541. drm_connector_property_set_value(connector,
  1542. intel_sdvo_connector->bottom, val);
  1543. if (intel_sdvo_connector->top_margin == temp_value)
  1544. return 0;
  1545. intel_sdvo_connector->top_margin = temp_value;
  1546. intel_sdvo_connector->bottom_margin = temp_value;
  1547. temp_value = intel_sdvo_connector->max_vscan -
  1548. intel_sdvo_connector->top_margin;
  1549. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1550. goto set_value;
  1551. } else if (intel_sdvo_connector->bottom == property) {
  1552. drm_connector_property_set_value(connector,
  1553. intel_sdvo_connector->top, val);
  1554. if (intel_sdvo_connector->bottom_margin == temp_value)
  1555. return 0;
  1556. intel_sdvo_connector->top_margin = temp_value;
  1557. intel_sdvo_connector->bottom_margin = temp_value;
  1558. temp_value = intel_sdvo_connector->max_vscan -
  1559. intel_sdvo_connector->top_margin;
  1560. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1561. goto set_value;
  1562. }
  1563. CHECK_PROPERTY(hpos, HPOS)
  1564. CHECK_PROPERTY(vpos, VPOS)
  1565. CHECK_PROPERTY(saturation, SATURATION)
  1566. CHECK_PROPERTY(contrast, CONTRAST)
  1567. CHECK_PROPERTY(hue, HUE)
  1568. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1569. CHECK_PROPERTY(sharpness, SHARPNESS)
  1570. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1571. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1572. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1573. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1574. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1575. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1576. }
  1577. return -EINVAL; /* unknown property */
  1578. set_value:
  1579. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1580. return -EIO;
  1581. done:
  1582. if (intel_sdvo->base.base.crtc) {
  1583. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  1584. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1585. crtc->y, crtc->fb);
  1586. }
  1587. return 0;
  1588. #undef CHECK_PROPERTY
  1589. }
  1590. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1591. .dpms = intel_sdvo_dpms,
  1592. .mode_fixup = intel_sdvo_mode_fixup,
  1593. .prepare = intel_encoder_prepare,
  1594. .mode_set = intel_sdvo_mode_set,
  1595. .commit = intel_encoder_commit,
  1596. };
  1597. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1598. .dpms = drm_helper_connector_dpms,
  1599. .detect = intel_sdvo_detect,
  1600. .fill_modes = drm_helper_probe_single_connector_modes,
  1601. .set_property = intel_sdvo_set_property,
  1602. .destroy = intel_sdvo_destroy,
  1603. };
  1604. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1605. .get_modes = intel_sdvo_get_modes,
  1606. .mode_valid = intel_sdvo_mode_valid,
  1607. .best_encoder = intel_best_encoder,
  1608. };
  1609. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1610. {
  1611. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1612. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1613. drm_mode_destroy(encoder->dev,
  1614. intel_sdvo->sdvo_lvds_fixed_mode);
  1615. i2c_del_adapter(&intel_sdvo->ddc);
  1616. intel_encoder_destroy(encoder);
  1617. }
  1618. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1619. .destroy = intel_sdvo_enc_destroy,
  1620. };
  1621. static void
  1622. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1623. {
  1624. uint16_t mask = 0;
  1625. unsigned int num_bits;
  1626. /* Make a mask of outputs less than or equal to our own priority in the
  1627. * list.
  1628. */
  1629. switch (sdvo->controlled_output) {
  1630. case SDVO_OUTPUT_LVDS1:
  1631. mask |= SDVO_OUTPUT_LVDS1;
  1632. case SDVO_OUTPUT_LVDS0:
  1633. mask |= SDVO_OUTPUT_LVDS0;
  1634. case SDVO_OUTPUT_TMDS1:
  1635. mask |= SDVO_OUTPUT_TMDS1;
  1636. case SDVO_OUTPUT_TMDS0:
  1637. mask |= SDVO_OUTPUT_TMDS0;
  1638. case SDVO_OUTPUT_RGB1:
  1639. mask |= SDVO_OUTPUT_RGB1;
  1640. case SDVO_OUTPUT_RGB0:
  1641. mask |= SDVO_OUTPUT_RGB0;
  1642. break;
  1643. }
  1644. /* Count bits to find what number we are in the priority list. */
  1645. mask &= sdvo->caps.output_flags;
  1646. num_bits = hweight16(mask);
  1647. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1648. if (num_bits > 3)
  1649. num_bits = 3;
  1650. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1651. sdvo->ddc_bus = 1 << num_bits;
  1652. }
  1653. /**
  1654. * Choose the appropriate DDC bus for control bus switch command for this
  1655. * SDVO output based on the controlled output.
  1656. *
  1657. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1658. * outputs, then LVDS outputs.
  1659. */
  1660. static void
  1661. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1662. struct intel_sdvo *sdvo, u32 reg)
  1663. {
  1664. struct sdvo_device_mapping *mapping;
  1665. if (sdvo->is_sdvob)
  1666. mapping = &(dev_priv->sdvo_mappings[0]);
  1667. else
  1668. mapping = &(dev_priv->sdvo_mappings[1]);
  1669. if (mapping->initialized)
  1670. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1671. else
  1672. intel_sdvo_guess_ddc_bus(sdvo);
  1673. }
  1674. static void
  1675. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1676. struct intel_sdvo *sdvo, u32 reg)
  1677. {
  1678. struct sdvo_device_mapping *mapping;
  1679. u8 pin;
  1680. if (sdvo->is_sdvob)
  1681. mapping = &dev_priv->sdvo_mappings[0];
  1682. else
  1683. mapping = &dev_priv->sdvo_mappings[1];
  1684. pin = GMBUS_PORT_DPB;
  1685. if (mapping->initialized)
  1686. pin = mapping->i2c_pin;
  1687. if (intel_gmbus_is_port_valid(pin)) {
  1688. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1689. intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
  1690. intel_gmbus_force_bit(sdvo->i2c, true);
  1691. } else {
  1692. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  1693. }
  1694. }
  1695. static bool
  1696. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1697. {
  1698. return intel_sdvo_check_supp_encode(intel_sdvo);
  1699. }
  1700. static u8
  1701. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1702. {
  1703. struct drm_i915_private *dev_priv = dev->dev_private;
  1704. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1705. if (sdvo->is_sdvob) {
  1706. my_mapping = &dev_priv->sdvo_mappings[0];
  1707. other_mapping = &dev_priv->sdvo_mappings[1];
  1708. } else {
  1709. my_mapping = &dev_priv->sdvo_mappings[1];
  1710. other_mapping = &dev_priv->sdvo_mappings[0];
  1711. }
  1712. /* If the BIOS described our SDVO device, take advantage of it. */
  1713. if (my_mapping->slave_addr)
  1714. return my_mapping->slave_addr;
  1715. /* If the BIOS only described a different SDVO device, use the
  1716. * address that it isn't using.
  1717. */
  1718. if (other_mapping->slave_addr) {
  1719. if (other_mapping->slave_addr == 0x70)
  1720. return 0x72;
  1721. else
  1722. return 0x70;
  1723. }
  1724. /* No SDVO device info is found for another DVO port,
  1725. * so use mapping assumption we had before BIOS parsing.
  1726. */
  1727. if (sdvo->is_sdvob)
  1728. return 0x70;
  1729. else
  1730. return 0x72;
  1731. }
  1732. static void
  1733. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1734. struct intel_sdvo *encoder)
  1735. {
  1736. drm_connector_init(encoder->base.base.dev,
  1737. &connector->base.base,
  1738. &intel_sdvo_connector_funcs,
  1739. connector->base.base.connector_type);
  1740. drm_connector_helper_add(&connector->base.base,
  1741. &intel_sdvo_connector_helper_funcs);
  1742. connector->base.base.interlace_allowed = 1;
  1743. connector->base.base.doublescan_allowed = 0;
  1744. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1745. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1746. drm_sysfs_connector_add(&connector->base.base);
  1747. }
  1748. static void
  1749. intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
  1750. {
  1751. struct drm_device *dev = connector->base.base.dev;
  1752. intel_attach_force_audio_property(&connector->base.base);
  1753. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
  1754. intel_attach_broadcast_rgb_property(&connector->base.base);
  1755. }
  1756. static bool
  1757. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1758. {
  1759. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1760. struct drm_connector *connector;
  1761. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1762. struct intel_connector *intel_connector;
  1763. struct intel_sdvo_connector *intel_sdvo_connector;
  1764. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1765. if (!intel_sdvo_connector)
  1766. return false;
  1767. if (device == 0) {
  1768. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1769. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1770. } else if (device == 1) {
  1771. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1772. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1773. }
  1774. intel_connector = &intel_sdvo_connector->base;
  1775. connector = &intel_connector->base;
  1776. if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
  1777. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1778. intel_sdvo->hotplug_active[0] |= 1 << device;
  1779. /* Some SDVO devices have one-shot hotplug interrupts.
  1780. * Ensure that they get re-enabled when an interrupt happens.
  1781. */
  1782. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1783. intel_sdvo_enable_hotplug(intel_encoder);
  1784. }
  1785. else
  1786. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1787. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1788. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1789. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1790. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1791. intel_sdvo->is_hdmi = true;
  1792. }
  1793. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1794. (1 << INTEL_ANALOG_CLONE_BIT));
  1795. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1796. if (intel_sdvo->is_hdmi)
  1797. intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
  1798. return true;
  1799. }
  1800. static bool
  1801. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1802. {
  1803. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1804. struct drm_connector *connector;
  1805. struct intel_connector *intel_connector;
  1806. struct intel_sdvo_connector *intel_sdvo_connector;
  1807. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1808. if (!intel_sdvo_connector)
  1809. return false;
  1810. intel_connector = &intel_sdvo_connector->base;
  1811. connector = &intel_connector->base;
  1812. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1813. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1814. intel_sdvo->controlled_output |= type;
  1815. intel_sdvo_connector->output_flag = type;
  1816. intel_sdvo->is_tv = true;
  1817. intel_sdvo->base.needs_tv_clock = true;
  1818. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1819. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1820. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1821. goto err;
  1822. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1823. goto err;
  1824. return true;
  1825. err:
  1826. intel_sdvo_destroy(connector);
  1827. return false;
  1828. }
  1829. static bool
  1830. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1831. {
  1832. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1833. struct drm_connector *connector;
  1834. struct intel_connector *intel_connector;
  1835. struct intel_sdvo_connector *intel_sdvo_connector;
  1836. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1837. if (!intel_sdvo_connector)
  1838. return false;
  1839. intel_connector = &intel_sdvo_connector->base;
  1840. connector = &intel_connector->base;
  1841. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1842. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1843. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1844. if (device == 0) {
  1845. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1846. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1847. } else if (device == 1) {
  1848. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1849. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1850. }
  1851. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1852. (1 << INTEL_ANALOG_CLONE_BIT));
  1853. intel_sdvo_connector_init(intel_sdvo_connector,
  1854. intel_sdvo);
  1855. return true;
  1856. }
  1857. static bool
  1858. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1859. {
  1860. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1861. struct drm_connector *connector;
  1862. struct intel_connector *intel_connector;
  1863. struct intel_sdvo_connector *intel_sdvo_connector;
  1864. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1865. if (!intel_sdvo_connector)
  1866. return false;
  1867. intel_connector = &intel_sdvo_connector->base;
  1868. connector = &intel_connector->base;
  1869. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1870. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1871. if (device == 0) {
  1872. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1873. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1874. } else if (device == 1) {
  1875. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1876. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1877. }
  1878. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1879. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1880. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1881. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1882. goto err;
  1883. return true;
  1884. err:
  1885. intel_sdvo_destroy(connector);
  1886. return false;
  1887. }
  1888. static bool
  1889. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1890. {
  1891. intel_sdvo->is_tv = false;
  1892. intel_sdvo->base.needs_tv_clock = false;
  1893. intel_sdvo->is_lvds = false;
  1894. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1895. if (flags & SDVO_OUTPUT_TMDS0)
  1896. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1897. return false;
  1898. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1899. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1900. return false;
  1901. /* TV has no XXX1 function block */
  1902. if (flags & SDVO_OUTPUT_SVID0)
  1903. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1904. return false;
  1905. if (flags & SDVO_OUTPUT_CVBS0)
  1906. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1907. return false;
  1908. if (flags & SDVO_OUTPUT_YPRPB0)
  1909. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  1910. return false;
  1911. if (flags & SDVO_OUTPUT_RGB0)
  1912. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1913. return false;
  1914. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1915. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1916. return false;
  1917. if (flags & SDVO_OUTPUT_LVDS0)
  1918. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1919. return false;
  1920. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1921. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1922. return false;
  1923. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1924. unsigned char bytes[2];
  1925. intel_sdvo->controlled_output = 0;
  1926. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1927. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1928. SDVO_NAME(intel_sdvo),
  1929. bytes[0], bytes[1]);
  1930. return false;
  1931. }
  1932. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1933. return true;
  1934. }
  1935. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1936. struct intel_sdvo_connector *intel_sdvo_connector,
  1937. int type)
  1938. {
  1939. struct drm_device *dev = intel_sdvo->base.base.dev;
  1940. struct intel_sdvo_tv_format format;
  1941. uint32_t format_map, i;
  1942. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1943. return false;
  1944. BUILD_BUG_ON(sizeof(format) != 6);
  1945. if (!intel_sdvo_get_value(intel_sdvo,
  1946. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1947. &format, sizeof(format)))
  1948. return false;
  1949. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1950. if (format_map == 0)
  1951. return false;
  1952. intel_sdvo_connector->format_supported_num = 0;
  1953. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1954. if (format_map & (1 << i))
  1955. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1956. intel_sdvo_connector->tv_format =
  1957. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1958. "mode", intel_sdvo_connector->format_supported_num);
  1959. if (!intel_sdvo_connector->tv_format)
  1960. return false;
  1961. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1962. drm_property_add_enum(
  1963. intel_sdvo_connector->tv_format, i,
  1964. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1965. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1966. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1967. intel_sdvo_connector->tv_format, 0);
  1968. return true;
  1969. }
  1970. #define ENHANCEMENT(name, NAME) do { \
  1971. if (enhancements.name) { \
  1972. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1973. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1974. return false; \
  1975. intel_sdvo_connector->max_##name = data_value[0]; \
  1976. intel_sdvo_connector->cur_##name = response; \
  1977. intel_sdvo_connector->name = \
  1978. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1979. if (!intel_sdvo_connector->name) return false; \
  1980. drm_connector_attach_property(connector, \
  1981. intel_sdvo_connector->name, \
  1982. intel_sdvo_connector->cur_##name); \
  1983. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1984. data_value[0], data_value[1], response); \
  1985. } \
  1986. } while (0)
  1987. static bool
  1988. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1989. struct intel_sdvo_connector *intel_sdvo_connector,
  1990. struct intel_sdvo_enhancements_reply enhancements)
  1991. {
  1992. struct drm_device *dev = intel_sdvo->base.base.dev;
  1993. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  1994. uint16_t response, data_value[2];
  1995. /* when horizontal overscan is supported, Add the left/right property */
  1996. if (enhancements.overscan_h) {
  1997. if (!intel_sdvo_get_value(intel_sdvo,
  1998. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1999. &data_value, 4))
  2000. return false;
  2001. if (!intel_sdvo_get_value(intel_sdvo,
  2002. SDVO_CMD_GET_OVERSCAN_H,
  2003. &response, 2))
  2004. return false;
  2005. intel_sdvo_connector->max_hscan = data_value[0];
  2006. intel_sdvo_connector->left_margin = data_value[0] - response;
  2007. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2008. intel_sdvo_connector->left =
  2009. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2010. if (!intel_sdvo_connector->left)
  2011. return false;
  2012. drm_connector_attach_property(connector,
  2013. intel_sdvo_connector->left,
  2014. intel_sdvo_connector->left_margin);
  2015. intel_sdvo_connector->right =
  2016. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2017. if (!intel_sdvo_connector->right)
  2018. return false;
  2019. drm_connector_attach_property(connector,
  2020. intel_sdvo_connector->right,
  2021. intel_sdvo_connector->right_margin);
  2022. DRM_DEBUG_KMS("h_overscan: max %d, "
  2023. "default %d, current %d\n",
  2024. data_value[0], data_value[1], response);
  2025. }
  2026. if (enhancements.overscan_v) {
  2027. if (!intel_sdvo_get_value(intel_sdvo,
  2028. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2029. &data_value, 4))
  2030. return false;
  2031. if (!intel_sdvo_get_value(intel_sdvo,
  2032. SDVO_CMD_GET_OVERSCAN_V,
  2033. &response, 2))
  2034. return false;
  2035. intel_sdvo_connector->max_vscan = data_value[0];
  2036. intel_sdvo_connector->top_margin = data_value[0] - response;
  2037. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2038. intel_sdvo_connector->top =
  2039. drm_property_create_range(dev, 0,
  2040. "top_margin", 0, data_value[0]);
  2041. if (!intel_sdvo_connector->top)
  2042. return false;
  2043. drm_connector_attach_property(connector,
  2044. intel_sdvo_connector->top,
  2045. intel_sdvo_connector->top_margin);
  2046. intel_sdvo_connector->bottom =
  2047. drm_property_create_range(dev, 0,
  2048. "bottom_margin", 0, data_value[0]);
  2049. if (!intel_sdvo_connector->bottom)
  2050. return false;
  2051. drm_connector_attach_property(connector,
  2052. intel_sdvo_connector->bottom,
  2053. intel_sdvo_connector->bottom_margin);
  2054. DRM_DEBUG_KMS("v_overscan: max %d, "
  2055. "default %d, current %d\n",
  2056. data_value[0], data_value[1], response);
  2057. }
  2058. ENHANCEMENT(hpos, HPOS);
  2059. ENHANCEMENT(vpos, VPOS);
  2060. ENHANCEMENT(saturation, SATURATION);
  2061. ENHANCEMENT(contrast, CONTRAST);
  2062. ENHANCEMENT(hue, HUE);
  2063. ENHANCEMENT(sharpness, SHARPNESS);
  2064. ENHANCEMENT(brightness, BRIGHTNESS);
  2065. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2066. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2067. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2068. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2069. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2070. if (enhancements.dot_crawl) {
  2071. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2072. return false;
  2073. intel_sdvo_connector->max_dot_crawl = 1;
  2074. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2075. intel_sdvo_connector->dot_crawl =
  2076. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2077. if (!intel_sdvo_connector->dot_crawl)
  2078. return false;
  2079. drm_connector_attach_property(connector,
  2080. intel_sdvo_connector->dot_crawl,
  2081. intel_sdvo_connector->cur_dot_crawl);
  2082. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2083. }
  2084. return true;
  2085. }
  2086. static bool
  2087. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2088. struct intel_sdvo_connector *intel_sdvo_connector,
  2089. struct intel_sdvo_enhancements_reply enhancements)
  2090. {
  2091. struct drm_device *dev = intel_sdvo->base.base.dev;
  2092. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2093. uint16_t response, data_value[2];
  2094. ENHANCEMENT(brightness, BRIGHTNESS);
  2095. return true;
  2096. }
  2097. #undef ENHANCEMENT
  2098. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2099. struct intel_sdvo_connector *intel_sdvo_connector)
  2100. {
  2101. union {
  2102. struct intel_sdvo_enhancements_reply reply;
  2103. uint16_t response;
  2104. } enhancements;
  2105. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2106. enhancements.response = 0;
  2107. intel_sdvo_get_value(intel_sdvo,
  2108. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2109. &enhancements, sizeof(enhancements));
  2110. if (enhancements.response == 0) {
  2111. DRM_DEBUG_KMS("No enhancement is supported\n");
  2112. return true;
  2113. }
  2114. if (IS_TV(intel_sdvo_connector))
  2115. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2116. else if (IS_LVDS(intel_sdvo_connector))
  2117. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2118. else
  2119. return true;
  2120. }
  2121. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2122. struct i2c_msg *msgs,
  2123. int num)
  2124. {
  2125. struct intel_sdvo *sdvo = adapter->algo_data;
  2126. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2127. return -EIO;
  2128. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2129. }
  2130. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2131. {
  2132. struct intel_sdvo *sdvo = adapter->algo_data;
  2133. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2134. }
  2135. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2136. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2137. .functionality = intel_sdvo_ddc_proxy_func
  2138. };
  2139. static bool
  2140. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2141. struct drm_device *dev)
  2142. {
  2143. sdvo->ddc.owner = THIS_MODULE;
  2144. sdvo->ddc.class = I2C_CLASS_DDC;
  2145. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2146. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2147. sdvo->ddc.algo_data = sdvo;
  2148. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2149. return i2c_add_adapter(&sdvo->ddc) == 0;
  2150. }
  2151. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2152. {
  2153. struct drm_i915_private *dev_priv = dev->dev_private;
  2154. struct intel_encoder *intel_encoder;
  2155. struct intel_sdvo *intel_sdvo;
  2156. u32 hotplug_mask;
  2157. int i;
  2158. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2159. if (!intel_sdvo)
  2160. return false;
  2161. intel_sdvo->sdvo_reg = sdvo_reg;
  2162. intel_sdvo->is_sdvob = is_sdvob;
  2163. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2164. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2165. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
  2166. kfree(intel_sdvo);
  2167. return false;
  2168. }
  2169. /* encoder type will be decided later */
  2170. intel_encoder = &intel_sdvo->base;
  2171. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2172. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2173. /* Read the regs to test if we can talk to the device */
  2174. for (i = 0; i < 0x40; i++) {
  2175. u8 byte;
  2176. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2177. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2178. SDVO_NAME(intel_sdvo));
  2179. goto err;
  2180. }
  2181. }
  2182. hotplug_mask = 0;
  2183. if (IS_G4X(dev)) {
  2184. hotplug_mask = intel_sdvo->is_sdvob ?
  2185. SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
  2186. } else if (IS_GEN4(dev)) {
  2187. hotplug_mask = intel_sdvo->is_sdvob ?
  2188. SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
  2189. } else {
  2190. hotplug_mask = intel_sdvo->is_sdvob ?
  2191. SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
  2192. }
  2193. dev_priv->hotplug_supported_mask |= hotplug_mask;
  2194. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2195. /* In default case sdvo lvds is false */
  2196. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2197. goto err;
  2198. /* Set up hotplug command - note paranoia about contents of reply.
  2199. * We assume that the hardware is in a sane state, and only touch
  2200. * the bits we think we understand.
  2201. */
  2202. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
  2203. &intel_sdvo->hotplug_active, 2);
  2204. intel_sdvo->hotplug_active[0] &= ~0x3;
  2205. if (intel_sdvo_output_setup(intel_sdvo,
  2206. intel_sdvo->caps.output_flags) != true) {
  2207. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2208. SDVO_NAME(intel_sdvo));
  2209. goto err;
  2210. }
  2211. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2212. /* Set the input timing to the screen. Assume always input 0. */
  2213. if (!intel_sdvo_set_target_input(intel_sdvo))
  2214. goto err;
  2215. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2216. &intel_sdvo->pixel_clock_min,
  2217. &intel_sdvo->pixel_clock_max))
  2218. goto err;
  2219. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2220. "clock range %dMHz - %dMHz, "
  2221. "input 1: %c, input 2: %c, "
  2222. "output 1: %c, output 2: %c\n",
  2223. SDVO_NAME(intel_sdvo),
  2224. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2225. intel_sdvo->caps.device_rev_id,
  2226. intel_sdvo->pixel_clock_min / 1000,
  2227. intel_sdvo->pixel_clock_max / 1000,
  2228. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2229. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2230. /* check currently supported outputs */
  2231. intel_sdvo->caps.output_flags &
  2232. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2233. intel_sdvo->caps.output_flags &
  2234. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2235. return true;
  2236. err:
  2237. drm_encoder_cleanup(&intel_encoder->base);
  2238. i2c_del_adapter(&intel_sdvo->ddc);
  2239. kfree(intel_sdvo);
  2240. return false;
  2241. }